various PGM protection cleanups / fixes (orlegend, olds, svgpcb) [iq_132]
This commit is contained in:
David Haywood
parent
9a6129e9d2
commit
025f0e4c28
@ -106,7 +106,7 @@ public:
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};
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/* for machine/pgmprot.c type games */
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/* for machine/pgmprot_orlegend.c type games */
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class pgm_asic3_state : public pgm_state
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{
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public:
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@ -118,16 +118,11 @@ public:
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UINT8 m_asic3_reg;
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UINT8 m_asic3_latch[3];
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UINT8 m_asic3_x;
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UINT8 m_asic3_y;
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UINT8 m_asic3_z;
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UINT16 m_asic3_h1;
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UINT16 m_asic3_h2;
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UINT16 m_asic3_hilo;
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UINT16 m_asic3_hold;
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DECLARE_DRIVER_INIT(orlegend);
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void asic3_compute_hold();
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void asic3_compute_hold(int,int);
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DECLARE_READ16_MEMBER( pgm_asic3_r );
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DECLARE_WRITE16_MEMBER( pgm_asic3_w );
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DECLARE_WRITE16_MEMBER( pgm_asic3_reg_w );
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@ -66,6 +66,7 @@ UINT32 igs028_device::olds_prot_addr(UINT16 addr)
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case 0x6: return 0x4030a4;
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case 0x7: return 0x403000;
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case 0x9: return 0x40306e;
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case 0xb: return 0x403044;
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}
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return 0;
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@ -743,7 +743,7 @@ void pgm_svgpcb_decrypt(running_machine &machine)
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IGS27_CRYPT2_ALT3
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IGS27_CRYPT3
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IGS27_CRYPT4 // ok?
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IGS27_CRYPT5_ALT //
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IGS27_CRYPT5 // ok?
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IGS27_CRYPT6_ALT // ok?
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IGS27_CRYPT7
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IGS27_CRYPT8_ALT
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@ -13,157 +13,167 @@
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#include "emu.h"
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#include "includes/pgm.h"
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/*** ASIC 3 (oriental legends protection) ****************************************/
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void pgm_asic3_state::asic3_compute_hold()
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void pgm_asic3_state::asic3_compute_hold(int y, int z)
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{
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// The mode is dependent on the region
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static const int modes[4] = { 1, 1, 3, 2 };
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int mode = modes[ioport("Region")->read() & 3];
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unsigned short old = m_asic3_hold;
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switch (mode)
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m_asic3_hold = ((old << 1) | (old >> 15));
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m_asic3_hold ^= 0x2bad;
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m_asic3_hold ^= BIT(z, y);
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m_asic3_hold ^= BIT(m_asic3_x, 1) << 6;
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m_asic3_hold ^= BIT(m_asic3_x, 2) << 10;
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m_asic3_hold ^= BIT(old, 5);
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switch (ioport("Region")->read()) // The mode is dependent on the region
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{
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case 1:
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m_asic3_hold =
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(m_asic3_hold << 1)
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^ 0x2bad
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^ BIT(m_asic3_hold, 15) ^ BIT(m_asic3_hold, 10) ^ BIT(m_asic3_hold, 8) ^ BIT(m_asic3_hold, 5)
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^ BIT(m_asic3_z, m_asic3_y)
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^ (BIT(m_asic3_x, 0) << 1) ^ (BIT(m_asic3_x, 1) << 6) ^ (BIT(m_asic3_x, 2) << 10) ^ (BIT(m_asic3_x, 3) << 14);
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case 0:
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case 1:
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m_asic3_hold ^= BIT(old, 10) ^ BIT(old, 8) ^ (BIT(m_asic3_x, 0) << 1) ^ (BIT(m_asic3_x, 3) << 14);
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break;
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case 2:
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m_asic3_hold =
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(m_asic3_hold << 1)
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^ 0x2bad
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^ BIT(m_asic3_hold, 15) ^ BIT(m_asic3_hold, 7) ^ BIT(m_asic3_hold, 6) ^ BIT(m_asic3_hold, 5)
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^ BIT(m_asic3_z, m_asic3_y)
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^ (BIT(m_asic3_x, 0) << 4) ^ (BIT(m_asic3_x, 1) << 6) ^ (BIT(m_asic3_x, 2) << 10) ^ (BIT(m_asic3_x, 3) << 12);
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case 2:
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m_asic3_hold ^= BIT(old, 10) ^ BIT(old, 8) ^ (BIT(m_asic3_x, 0) << 4) ^ (BIT(m_asic3_x, 3) << 12);
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break;
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case 3:
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m_asic3_hold =
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(m_asic3_hold << 1)
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^ 0x2bad
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^ BIT(m_asic3_hold, 15) ^ BIT(m_asic3_hold, 10) ^ BIT(m_asic3_hold, 8) ^ BIT(m_asic3_hold, 5)
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^ BIT(m_asic3_z, m_asic3_y)
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^ (BIT(m_asic3_x, 0) << 4) ^ (BIT(m_asic3_x, 1) << 6) ^ (BIT(m_asic3_x, 2) << 10) ^ (BIT(m_asic3_x, 3) << 12);
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case 3:
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m_asic3_hold ^= BIT(old, 7) ^ BIT(old, 6) ^ (BIT(m_asic3_x, 0) << 4) ^ (BIT(m_asic3_x, 3) << 12);
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break;
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}
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}
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READ16_MEMBER(pgm_asic3_state::pgm_asic3_r )
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READ16_MEMBER(pgm_asic3_state::pgm_asic3_r)
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{
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UINT8 res = 0;
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/* region is supplied by the protection device */
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switch (m_asic3_reg)
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{
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case 0x00: // region is supplied by the protection device
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return (m_asic3_latch[0] & 0xf7) | ((ioport("Region")->read() << 3) & 0x08);
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case 0x01:
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return m_asic3_latch[1];
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case 0x02: // region is supplied by the protection device
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return (m_asic3_latch[2] & 0x7f) | ((ioport("Region")->read() << 6) & 0x80);
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case 0x03:
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return BITSWAP8(m_asic3_hold, 5,2,9,7,10,13,12,15);
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// case $157674, expected return $157686
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case 0x20: return 0x49; // "IGS"
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case 0x21: return 0x47;
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case 0x22: return 0x53;
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case 0x24: return 0x41;
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case 0x25: return 0x41;
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case 0x26: return 0x7f;
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case 0x27: return 0x41;
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case 0x28: return 0x41;
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case 0x2a: return 0x3e;
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case 0x2b: return 0x41;
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case 0x2c: return 0x49;
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case 0x2d: return 0xf9;
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case 0x2e: return 0x0a;
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case 0x30: return 0x26;
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case 0x31: return 0x49;
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case 0x32: return 0x49;
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case 0x33: return 0x49;
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case 0x34: return 0x32;
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// default:
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// logerror("ASIC3 R: CMD %2.2X PC: %6.6x\n", m_asic3_reg, space.device().safe_pc());
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}
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return 0;
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}
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WRITE16_MEMBER(pgm_asic3_state::pgm_asic3_w)
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{
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if (offset == 0) {
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m_asic3_reg = data;
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return;
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}
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switch (m_asic3_reg)
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{
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case 0x00: res = (m_asic3_latch[0] & 0xf7) | ((ioport("Region")->read() << 3) & 0x08); break;
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case 0x01: res = m_asic3_latch[1]; break;
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case 0x02: res = (m_asic3_latch[2] & 0x7f) | ((ioport("Region")->read() << 6) & 0x80); break;
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case 0x03:
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res = (BIT(m_asic3_hold, 15) << 0)
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| (BIT(m_asic3_hold, 12) << 1)
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| (BIT(m_asic3_hold, 13) << 2)
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| (BIT(m_asic3_hold, 10) << 3)
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| (BIT(m_asic3_hold, 7) << 4)
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| (BIT(m_asic3_hold, 9) << 5)
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| (BIT(m_asic3_hold, 2) << 6)
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| (BIT(m_asic3_hold, 5) << 7);
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break;
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case 0x20: res = 0x49; break;
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case 0x21: res = 0x47; break;
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case 0x22: res = 0x53; break;
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case 0x24: res = 0x41; break;
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case 0x25: res = 0x41; break;
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case 0x26: res = 0x7f; break;
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case 0x27: res = 0x41; break;
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case 0x28: res = 0x41; break;
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case 0x2a: res = 0x3e; break;
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case 0x2b: res = 0x41; break;
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case 0x2c: res = 0x49; break;
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case 0x2d: res = 0xf9; break;
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case 0x2e: res = 0x0a; break;
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case 0x30: res = 0x26; break;
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case 0x31: res = 0x49; break;
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case 0x32: res = 0x49; break;
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case 0x33: res = 0x49; break;
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case 0x34: res = 0x32; break;
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}
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return res;
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}
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WRITE16_MEMBER(pgm_asic3_state::pgm_asic3_w )
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{
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if(ACCESSING_BITS_0_7)
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{
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if (m_asic3_reg < 3)
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case 0x00:
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case 0x01:
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case 0x02:
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m_asic3_latch[m_asic3_reg] = data << 1;
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else if (m_asic3_reg == 0xa0)
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m_asic3_hold = 0;
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else if (m_asic3_reg == 0x40)
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{
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m_asic3_h2 = m_asic3_h1;
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m_asic3_h1 = data;
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}
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else if (m_asic3_reg == 0x48)
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break;
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// case 0x03: // move.w #$88, $c0400e.l
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// case 0x04: // move.w #$84, $c0400e.l
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// case 0x05: // move.w #$A0, $c0400e.l
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// break;
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case 0x40:
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m_asic3_hilo = (m_asic3_hilo << 8) | data;
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break;
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case 0x41: // Same as CMD 40. What is the purpose of writing data here again??
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case 0x42:
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case 0x43:
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case 0x44:
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case 0x45:
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case 0x46:
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case 0x47:
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break;
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case 0x48:
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{
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m_asic3_x = 0;
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if (!(m_asic3_h2 & 0x0a))
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m_asic3_x |= 8;
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if (!(m_asic3_h2 & 0x90))
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m_asic3_x |= 4;
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if (!(m_asic3_h1 & 0x06))
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m_asic3_x |= 2;
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if (!(m_asic3_h1 & 0x90))
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m_asic3_x |= 1;
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}
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else if(m_asic3_reg >= 0x80 && m_asic3_reg <= 0x87)
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{
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m_asic3_y = m_asic3_reg & 7;
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m_asic3_z = data;
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asic3_compute_hold();
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if ((m_asic3_hilo & 0x0090) == 0) m_asic3_x |= 0x01;
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if ((m_asic3_hilo & 0x0006) == 0) m_asic3_x |= 0x02;
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if ((m_asic3_hilo & 0x9000) == 0) m_asic3_x |= 0x04;
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if ((m_asic3_hilo & 0x0a00) == 0) m_asic3_x |= 0x08;
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}
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break;
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// case 0x50: // move.w #$50, $c0400e.l
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// break;
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case 0x80:
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case 0x81:
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case 0x82:
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case 0x83:
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case 0x84:
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case 0x85:
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case 0x86:
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case 0x87:
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asic3_compute_hold(m_asic3_reg & 0x07, data);
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break;
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case 0xa0:
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m_asic3_hold = 0;
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break;
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default:
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logerror("ASIC3 W: CMD %2.2X DATA: %4.4x, PC: %6.6x\n", m_asic3_reg, data, space.device().safe_pc());
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}
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}
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WRITE16_MEMBER(pgm_asic3_state::pgm_asic3_reg_w )
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{
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if(ACCESSING_BITS_0_7)
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m_asic3_reg = data & 0xff;
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}
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/* Oriental Legend INIT */
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DRIVER_INIT_MEMBER(pgm_asic3_state,orlegend)
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{
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pgm_basic_init();
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m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xC0400e, 0xC0400f, read16_delegate(FUNC(pgm_asic3_state::pgm_asic3_r),this), write16_delegate(FUNC(pgm_asic3_state::pgm_asic3_w),this));
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m_maincpu->space(AS_PROGRAM).install_write_handler(0xC04000, 0xC04001, write16_delegate(FUNC(pgm_asic3_state::pgm_asic3_reg_w),this));
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m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xC04000, 0xC0400f, read16_delegate(FUNC(pgm_asic3_state::pgm_asic3_r),this), write16_delegate(FUNC(pgm_asic3_state::pgm_asic3_w),this));
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m_asic3_reg = 0;
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m_asic3_latch[0] = 0;
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m_asic3_latch[1] = 0;
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m_asic3_latch[2] = 0;
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m_asic3_x = 0;
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m_asic3_y = 0;
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m_asic3_z = 0;
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m_asic3_h1 = 0;
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m_asic3_h2 = 0;
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m_asic3_hilo = 0;
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m_asic3_hold = 0;
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save_item(NAME(m_asic3_reg));
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save_item(NAME(m_asic3_latch));
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save_item(NAME(m_asic3_x));
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save_item(NAME(m_asic3_y));
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save_item(NAME(m_asic3_z));
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save_item(NAME(m_asic3_h1));
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save_item(NAME(m_asic3_h2));
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save_item(NAME(m_asic3_hilo));
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save_item(NAME(m_asic3_hold));
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}
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