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various PGM protection cleanups / fixes (orlegend, olds, svgpcb) [iq_132]

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This commit is contained in:
David Haywood 2013-11-30 02:31:01 +00:00
parent 9a6129e9d2
commit 025f0e4c28
4 changed files with 129 additions and 123 deletions
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11
src/mame/includes/pgm.h
View File

@ -106,7 +106,7 @@ public:
}; };
/* for machine/pgmprot.c type games */ /* for machine/pgmprot_orlegend.c type games */
class pgm_asic3_state : public pgm_state class pgm_asic3_state : public pgm_state
{ {
public: public:
@ -118,16 +118,11 @@ public:
UINT8 m_asic3_reg; UINT8 m_asic3_reg;
UINT8 m_asic3_latch[3]; UINT8 m_asic3_latch[3];
UINT8 m_asic3_x; UINT8 m_asic3_x;
UINT8 m_asic3_y; UINT16 m_asic3_hilo;
UINT8 m_asic3_z;
UINT16 m_asic3_h1;
UINT16 m_asic3_h2;
UINT16 m_asic3_hold; UINT16 m_asic3_hold;
DECLARE_DRIVER_INIT(orlegend); DECLARE_DRIVER_INIT(orlegend);
void asic3_compute_hold(); void asic3_compute_hold(int,int);
DECLARE_READ16_MEMBER( pgm_asic3_r ); DECLARE_READ16_MEMBER( pgm_asic3_r );
DECLARE_WRITE16_MEMBER( pgm_asic3_w ); DECLARE_WRITE16_MEMBER( pgm_asic3_w );
DECLARE_WRITE16_MEMBER( pgm_asic3_reg_w ); DECLARE_WRITE16_MEMBER( pgm_asic3_reg_w );

1
src/mame/machine/igs028.c
View File

@ -66,6 +66,7 @@ UINT32 igs028_device::olds_prot_addr(UINT16 addr)
case 0x6: return 0x4030a4; case 0x6: return 0x4030a4;
case 0x7: return 0x403000; case 0x7: return 0x403000;
case 0x9: return 0x40306e; case 0x9: return 0x40306e;
case 0xb: return 0x403044;
} }
return 0; return 0;

2
src/mame/machine/pgmcrypt.c
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@ -743,7 +743,7 @@ void pgm_svgpcb_decrypt(running_machine &machine)
IGS27_CRYPT2_ALT3 IGS27_CRYPT2_ALT3
IGS27_CRYPT3 IGS27_CRYPT3
IGS27_CRYPT4 // ok? IGS27_CRYPT4 // ok?
IGS27_CRYPT5_ALT // IGS27_CRYPT5 // ok?
IGS27_CRYPT6_ALT // ok? IGS27_CRYPT6_ALT // ok?
IGS27_CRYPT7 IGS27_CRYPT7
IGS27_CRYPT8_ALT IGS27_CRYPT8_ALT

218
src/mame/machine/pgmprot_orlegend.c
View File

@ -13,129 +13,146 @@
#include "emu.h" #include "emu.h"
#include "includes/pgm.h" #include "includes/pgm.h"
/*** ASIC 3 (oriental legends protection) ****************************************/ void pgm_asic3_state::asic3_compute_hold(int y, int z)
void pgm_asic3_state::asic3_compute_hold()
{ {
// The mode is dependent on the region unsigned short old = m_asic3_hold;
static const int modes[4] = { 1, 1, 3, 2 };
int mode = modes[ioport("Region")->read() & 3];
switch (mode) m_asic3_hold = ((old << 1) | (old >> 15));
m_asic3_hold ^= 0x2bad;
m_asic3_hold ^= BIT(z, y);
m_asic3_hold ^= BIT(m_asic3_x, 1) << 6;
m_asic3_hold ^= BIT(m_asic3_x, 2) << 10;
m_asic3_hold ^= BIT(old, 5);
switch (ioport("Region")->read()) // The mode is dependent on the region
{ {
case 0:
case 1: case 1:
m_asic3_hold = m_asic3_hold ^= BIT(old, 10) ^ BIT(old, 8) ^ (BIT(m_asic3_x, 0) << 1) ^ (BIT(m_asic3_x, 3) << 14);
(m_asic3_hold << 1)
^ 0x2bad
^ BIT(m_asic3_hold, 15) ^ BIT(m_asic3_hold, 10) ^ BIT(m_asic3_hold, 8) ^ BIT(m_asic3_hold, 5)
^ BIT(m_asic3_z, m_asic3_y)
^ (BIT(m_asic3_x, 0) << 1) ^ (BIT(m_asic3_x, 1) << 6) ^ (BIT(m_asic3_x, 2) << 10) ^ (BIT(m_asic3_x, 3) << 14);
break; break;
case 2: case 2:
m_asic3_hold = m_asic3_hold ^= BIT(old, 10) ^ BIT(old, 8) ^ (BIT(m_asic3_x, 0) << 4) ^ (BIT(m_asic3_x, 3) << 12);
(m_asic3_hold << 1)
^ 0x2bad
^ BIT(m_asic3_hold, 15) ^ BIT(m_asic3_hold, 7) ^ BIT(m_asic3_hold, 6) ^ BIT(m_asic3_hold, 5)
^ BIT(m_asic3_z, m_asic3_y)
^ (BIT(m_asic3_x, 0) << 4) ^ (BIT(m_asic3_x, 1) << 6) ^ (BIT(m_asic3_x, 2) << 10) ^ (BIT(m_asic3_x, 3) << 12);
break; break;
case 3: case 3:
m_asic3_hold = m_asic3_hold ^= BIT(old, 7) ^ BIT(old, 6) ^ (BIT(m_asic3_x, 0) << 4) ^ (BIT(m_asic3_x, 3) << 12);
(m_asic3_hold << 1)
^ 0x2bad
^ BIT(m_asic3_hold, 15) ^ BIT(m_asic3_hold, 10) ^ BIT(m_asic3_hold, 8) ^ BIT(m_asic3_hold, 5)
^ BIT(m_asic3_z, m_asic3_y)
^ (BIT(m_asic3_x, 0) << 4) ^ (BIT(m_asic3_x, 1) << 6) ^ (BIT(m_asic3_x, 2) << 10) ^ (BIT(m_asic3_x, 3) << 12);
break; break;
} }
} }
READ16_MEMBER(pgm_asic3_state::pgm_asic3_r) READ16_MEMBER(pgm_asic3_state::pgm_asic3_r)
{ {
UINT8 res = 0;
/* region is supplied by the protection device */
switch (m_asic3_reg) switch (m_asic3_reg)
{ {
case 0x00: res = (m_asic3_latch[0] & 0xf7) | ((ioport("Region")->read() << 3) & 0x08); break; case 0x00: // region is supplied by the protection device
case 0x01: res = m_asic3_latch[1]; break; return (m_asic3_latch[0] & 0xf7) | ((ioport("Region")->read() << 3) & 0x08);
case 0x02: res = (m_asic3_latch[2] & 0x7f) | ((ioport("Region")->read() << 6) & 0x80); break;
case 0x01:
return m_asic3_latch[1];
case 0x02: // region is supplied by the protection device
return (m_asic3_latch[2] & 0x7f) | ((ioport("Region")->read() << 6) & 0x80);
case 0x03: case 0x03:
res = (BIT(m_asic3_hold, 15) << 0) return BITSWAP8(m_asic3_hold, 5,2,9,7,10,13,12,15);
| (BIT(m_asic3_hold, 12) << 1)
| (BIT(m_asic3_hold, 13) << 2) // case $157674, expected return $157686
| (BIT(m_asic3_hold, 10) << 3) case 0x20: return 0x49; // "IGS"
| (BIT(m_asic3_hold, 7) << 4) case 0x21: return 0x47;
| (BIT(m_asic3_hold, 9) << 5) case 0x22: return 0x53;
| (BIT(m_asic3_hold, 2) << 6)
| (BIT(m_asic3_hold, 5) << 7); case 0x24: return 0x41;
break; case 0x25: return 0x41;
case 0x20: res = 0x49; break; case 0x26: return 0x7f;
case 0x21: res = 0x47; break; case 0x27: return 0x41;
case 0x22: res = 0x53; break; case 0x28: return 0x41;
case 0x24: res = 0x41; break;
case 0x25: res = 0x41; break; case 0x2a: return 0x3e;
case 0x26: res = 0x7f; break; case 0x2b: return 0x41;
case 0x27: res = 0x41; break; case 0x2c: return 0x49;
case 0x28: res = 0x41; break; case 0x2d: return 0xf9;
case 0x2a: res = 0x3e; break; case 0x2e: return 0x0a;
case 0x2b: res = 0x41; break;
case 0x2c: res = 0x49; break; case 0x30: return 0x26;
case 0x2d: res = 0xf9; break; case 0x31: return 0x49;
case 0x2e: res = 0x0a; break; case 0x32: return 0x49;
case 0x30: res = 0x26; break; case 0x33: return 0x49;
case 0x31: res = 0x49; break; case 0x34: return 0x32;
case 0x32: res = 0x49; break;
case 0x33: res = 0x49; break; // default:
case 0x34: res = 0x32; break; // logerror("ASIC3 R: CMD %2.2X PC: %6.6x\n", m_asic3_reg, space.device().safe_pc());
} }
return res; return 0;
} }
WRITE16_MEMBER(pgm_asic3_state::pgm_asic3_w) WRITE16_MEMBER(pgm_asic3_state::pgm_asic3_w)
{ {
if(ACCESSING_BITS_0_7) if (offset == 0) {
{ m_asic3_reg = data;
if (m_asic3_reg < 3) return;
m_asic3_latch[m_asic3_reg] = data << 1;
else if (m_asic3_reg == 0xa0)
m_asic3_hold = 0;
else if (m_asic3_reg == 0x40)
{
m_asic3_h2 = m_asic3_h1;
m_asic3_h1 = data;
} }
else if (m_asic3_reg == 0x48)
switch (m_asic3_reg)
{
case 0x00:
case 0x01:
case 0x02:
m_asic3_latch[m_asic3_reg] = data << 1;
break;
// case 0x03: // move.w #$88, $c0400e.l
// case 0x04: // move.w #$84, $c0400e.l
// case 0x05: // move.w #$A0, $c0400e.l
// break;
case 0x40:
m_asic3_hilo = (m_asic3_hilo << 8) | data;
break;
case 0x41: // Same as CMD 40. What is the purpose of writing data here again??
case 0x42:
case 0x43:
case 0x44:
case 0x45:
case 0x46:
case 0x47:
break;
case 0x48:
{ {
m_asic3_x = 0; m_asic3_x = 0;
if (!(m_asic3_h2 & 0x0a)) if ((m_asic3_hilo & 0x0090) == 0) m_asic3_x |= 0x01;
m_asic3_x |= 8; if ((m_asic3_hilo & 0x0006) == 0) m_asic3_x |= 0x02;
if (!(m_asic3_h2 & 0x90)) if ((m_asic3_hilo & 0x9000) == 0) m_asic3_x |= 0x04;
m_asic3_x |= 4; if ((m_asic3_hilo & 0x0a00) == 0) m_asic3_x |= 0x08;
if (!(m_asic3_h1 & 0x06))
m_asic3_x |= 2;
if (!(m_asic3_h1 & 0x90))
m_asic3_x |= 1;
} }
else if(m_asic3_reg >= 0x80 && m_asic3_reg <= 0x87) break;
{
m_asic3_y = m_asic3_reg & 7; // case 0x50: // move.w #$50, $c0400e.l
m_asic3_z = data; // break;
asic3_compute_hold();
case 0x80:
case 0x81:
case 0x82:
case 0x83:
case 0x84:
case 0x85:
case 0x86:
case 0x87:
asic3_compute_hold(m_asic3_reg & 0x07, data);
break;
case 0xa0:
m_asic3_hold = 0;
break;
default:
logerror("ASIC3 W: CMD %2.2X DATA: %4.4x, PC: %6.6x\n", m_asic3_reg, data, space.device().safe_pc());
} }
} }
}
WRITE16_MEMBER(pgm_asic3_state::pgm_asic3_reg_w )
{
if(ACCESSING_BITS_0_7)
m_asic3_reg = data & 0xff;
}
/* Oriental Legend INIT */ /* Oriental Legend INIT */
@ -143,27 +160,20 @@ DRIVER_INIT_MEMBER(pgm_asic3_state,orlegend)
{ {
pgm_basic_init(); pgm_basic_init();
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xC0400e, 0xC0400f, read16_delegate(FUNC(pgm_asic3_state::pgm_asic3_r),this), write16_delegate(FUNC(pgm_asic3_state::pgm_asic3_w),this)); m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xC04000, 0xC0400f, read16_delegate(FUNC(pgm_asic3_state::pgm_asic3_r),this), write16_delegate(FUNC(pgm_asic3_state::pgm_asic3_w),this));
m_maincpu->space(AS_PROGRAM).install_write_handler(0xC04000, 0xC04001, write16_delegate(FUNC(pgm_asic3_state::pgm_asic3_reg_w),this));
m_asic3_reg = 0; m_asic3_reg = 0;
m_asic3_latch[0] = 0; m_asic3_latch[0] = 0;
m_asic3_latch[1] = 0; m_asic3_latch[1] = 0;
m_asic3_latch[2] = 0; m_asic3_latch[2] = 0;
m_asic3_x = 0; m_asic3_x = 0;
m_asic3_y = 0; m_asic3_hilo = 0;
m_asic3_z = 0;
m_asic3_h1 = 0;
m_asic3_h2 = 0;
m_asic3_hold = 0; m_asic3_hold = 0;
save_item(NAME(m_asic3_reg)); save_item(NAME(m_asic3_reg));
save_item(NAME(m_asic3_latch)); save_item(NAME(m_asic3_latch));
save_item(NAME(m_asic3_x)); save_item(NAME(m_asic3_x));
save_item(NAME(m_asic3_y)); save_item(NAME(m_asic3_hilo));
save_item(NAME(m_asic3_z));
save_item(NAME(m_asic3_h1));
save_item(NAME(m_asic3_h2));
save_item(NAME(m_asic3_hold)); save_item(NAME(m_asic3_hold));
} }