mirror of
https://github.com/holub/mame
synced 2025-04-24 09:20:02 +03:00
cleaned up the ide controller enough to change the irq to a DEVCB2 [smf]
This commit is contained in:
smf-
parent
7f4308a886
commit
029ef2cd18
File diff suppressed because it is too large
Load Diff
@ -130,13 +130,11 @@ extern const device_type IDE_HARDDISK_IMAGE;
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TYPE DEFINITIONS
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***************************************************************************/
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struct ide_config
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{
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void (*interrupt)(device_t *device, int state);
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const char *bmcpu; /* name of bus master CPU */
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UINT32 bmspace; /* address space of bus master transfer */
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};
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#define MCFG_IDE_CONTROLLER_IRQ_HANDLER(_devcb) \
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devcb = &ide_controller_device::set_irq_handler(*device, DEVCB2_##_devcb);
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#define MCFG_IDE_CONTROLLER_BUS_MASTER(bmcpu, bmspace) \
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ide_controller_device::set_bus_master(*device, bmcpu, bmspace);
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SLOT_INTERFACE_EXTERN(ide_devices);
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SLOT_INTERFACE_EXTERN(ide_image_devices);
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@ -145,27 +143,20 @@ SLOT_INTERFACE_EXTERN(ide_image_devices);
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DEVICE CONFIGURATION MACROS
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***************************************************************************/
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#define MCFG_IDE_CONTROLLER_ADD(_tag, _config, _slotintf, _master, _slave, _fixed) \
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#define MCFG_IDE_CONTROLLER_ADD(_tag, _slotintf, _master, _slave, _fixed) \
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MCFG_DEVICE_ADD(_tag, IDE_CONTROLLER, 0) \
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MCFG_DEVICE_CONFIG(_config) \
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MCFG_IDE_SLOT_ADD("drive_0", _slotintf, _master, NULL, _fixed) \
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MCFG_IDE_SLOT_ADD("drive_1", _slotintf, _slave, NULL, _fixed) \
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MCFG_DEVICE_MODIFY(_tag)
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#define MCFG_IDE_SLOT_ADD(_tag, _slot_intf, _def_slot, _def_inp, _fixed) \
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MCFG_DEVICE_ADD(_tag, IDE_SLOT, 0) \
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MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, _def_inp, _fixed) \
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MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, _def_inp, _fixed)
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/***************************************************************************
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FUNCTION PROTOTYPES
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***************************************************************************/
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UINT8 *ide_get_features(device_t *device, int drive);
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void ide_set_master_password(device_t *device, const UINT8 *password);
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void ide_set_user_password(device_t *device, const UINT8 *password);
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void ide_set_gnet_readlock(device_t *device, const UINT8 onoff);
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int ide_bus_r(device_t *config, int select, int offset);
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void ide_bus_w(device_t *config, int select, int offset, int data);
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@ -182,6 +173,20 @@ DECLARE_WRITE32_DEVICE_HANDLER( ide_bus_master32_w );
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DECLARE_READ16_DEVICE_HANDLER( ide_controller16_r );
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DECLARE_WRITE16_DEVICE_HANDLER( ide_controller16_w );
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/***************************************************************************
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TYPE DEFINITIONS
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***************************************************************************/
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struct ide_device
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{
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UINT16 cur_cylinder;
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UINT8 cur_sector;
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UINT8 cur_head;
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UINT8 cur_head_reg;
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UINT32 cur_lba;
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ide_slot_device *slot;
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};
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#define IDE_CONFIG_REGISTERS 0x10
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/* ----- device interface ----- */
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@ -189,18 +194,91 @@ class ide_controller_device : public device_t
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{
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public:
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ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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~ide_controller_device() { global_free(m_token); }
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// access to legacy token
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void *token() const { assert(m_token != NULL); return m_token; }
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// static configuration helpers
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template<class _Object> static devcb2_base &set_irq_handler(device_t &device, _Object object) { return downcast<ide_controller_device &>(device).m_irq_handler.set_callback(object); }
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static void set_bus_master(device_t &device, const char *bmcpu, UINT32 bmspace) {ide_controller_device &ide = downcast<ide_controller_device &>(device); ide.bmcpu = bmcpu; ide.bmspace = bmspace; }
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UINT8 *ide_get_features(int drive);
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void ide_set_gnet_readlock(const UINT8 onoff);
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void ide_set_master_password(const UINT8 *password);
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void ide_set_user_password(const UINT8 *password);
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UINT32 ide_controller_read(int bank, offs_t offset, int size);
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void ide_controller_write(int bank, offs_t offset, int size, UINT32 data);
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UINT32 ide_bus_master_read(offs_t offset, int size);
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void ide_bus_master_write(offs_t offset, int size, UINT32 data);
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void signal_interrupt();
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void clear_interrupt();
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void read_sector_done();
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void write_sector_done();
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UINT8 status;
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protected:
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// device-level overrides
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virtual void device_config_complete();
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virtual void device_start();
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virtual void device_reset();
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private:
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// internal state
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void *m_token;
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void signal_delayed_interrupt(attotime time, int buffer_ready);
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UINT32 lba_address();
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void next_sector();
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void security_error();
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void continue_read();
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void write_buffer_to_dma();
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void read_first_sector();
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void read_next_sector();
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void read_buffer_from_dma();
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void handle_command(UINT8 _command);
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void continue_write();
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UINT8 adapter_control;
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UINT8 error;
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UINT8 command;
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UINT8 interrupt_pending;
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UINT8 precomp_offset;
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UINT8 buffer[IDE_DISK_SECTOR_SIZE];
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UINT16 buffer_offset;
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UINT16 sector_count;
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UINT16 block_count;
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UINT16 sectors_until_int;
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UINT8 verify_only;
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UINT8 dma_active;
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address_space *dma_space;
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UINT8 dma_address_xor;
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UINT8 dma_last_buffer;
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offs_t dma_address;
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offs_t dma_descriptor;
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UINT32 dma_bytes_left;
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UINT8 bus_master_command;
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UINT8 bus_master_status;
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UINT32 bus_master_descriptor;
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UINT8 config_unknown;
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UINT8 config_register[IDE_CONFIG_REGISTERS];
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UINT8 config_register_num;
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emu_timer * last_status_timer;
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emu_timer * reset_timer;
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UINT8 master_password_enable;
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UINT8 user_password_enable;
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const UINT8 * master_password;
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const UINT8 * user_password;
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UINT8 gnetreadlock;
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UINT8 cur_drive;
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ide_device drive[2];
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devcb2_write_line m_irq_handler;
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const char *bmcpu;
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UINT32 bmspace;
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};
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extern const device_type IDE_CONTROLLER;
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@ -178,14 +178,13 @@ void jaguar_state::update_gpu_irq()
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}
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void jaguar_state::external_int(device_t *device, int newstate)
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WRITE_LINE_MEMBER( jaguar_state::external_int )
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{
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jaguar_state &state = *device->machine().driver_data<jaguar_state>();
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if (newstate != CLEAR_LINE)
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state.m_gpu_irq_state |= 1;
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if (state != CLEAR_LINE)
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m_gpu_irq_state |= 1;
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else
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state.m_gpu_irq_state &= ~1;
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state.update_gpu_irq();
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m_gpu_irq_state &= ~1;
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update_gpu_irq();
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}
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@ -93,16 +93,6 @@ UINT32 atlantis_state::screen_update_mwskins(screen_device &screen, bitmap_ind16
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/*************************************
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*
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* Interrupt handling
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*
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*************************************/
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static void ide_interrupt(device_t *device, int state)
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{
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}
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/*************************************
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*
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* Main CPU memory handlers
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@ -142,13 +132,6 @@ static const mips3_config r4310_config =
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16384 /* data cache size */
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};
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static const ide_config ide_intf =
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{
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ide_interrupt,
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NULL,
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0
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};
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static MACHINE_CONFIG_START( mwskins, atlantis_state )
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/* basic machine hardware */
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@ -157,7 +140,7 @@ static MACHINE_CONFIG_START( mwskins, atlantis_state )
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MCFG_CPU_PROGRAM_MAP(main_map)
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MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
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MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
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/* video hardware */
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MCFG_VIDEO_ATTRIBUTES(VIDEO_UPDATE_BEFORE_VBLANK)
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@ -171,6 +171,7 @@ public:
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DECLARE_WRITE16_MEMBER(calchase_dac_l_w);
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DECLARE_WRITE16_MEMBER(calchase_dac_r_w);
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DECLARE_WRITE_LINE_MEMBER(calchase_pic8259_1_set_int_line);
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DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
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DECLARE_READ8_MEMBER(get_slave_ack);
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DECLARE_DRIVER_INIT(calchase);
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virtual void machine_start();
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@ -178,7 +179,6 @@ public:
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};
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static void ide_interrupt(device_t *device, int state);
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READ8_MEMBER(calchase_state::at_dma8237_2_r)
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@ -896,10 +896,9 @@ static void keyboard_interrupt(running_machine &machine, int state)
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pic8259_ir1_w(drvstate->m_pic8259_1, state);
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}
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static void ide_interrupt(device_t *device, int state)
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WRITE_LINE_MEMBER( calchase_state::ide_interrupt )
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{
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calchase_state *drvstate = device->machine().driver_data<calchase_state>();
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pic8259_ir6_w(drvstate->m_pic8259_2, state);
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pic8259_ir6_w(m_pic8259_2, state);
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}
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static int calchase_get_out2(running_machine &machine)
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@ -919,13 +918,6 @@ static void calchase_set_keyb_int(running_machine &machine, int state)
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pic8259_ir1_w(drvstate->m_pic8259_1, state);
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}
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static const ide_config ide_intf =
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{
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ide_interrupt,
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NULL,
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0
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};
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static MACHINE_CONFIG_START( calchase, calchase_state )
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MCFG_CPU_ADD("maincpu", PENTIUM, 133000000) // Cyrix 686MX-PR200 CPU
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MCFG_CPU_PROGRAM_MAP(calchase_map)
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@ -937,7 +929,8 @@ static MACHINE_CONFIG_START( calchase, calchase_state )
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MCFG_I8237_ADD( "dma8237_2", XTAL_14_31818MHz/3, dma8237_2_config )
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MCFG_PIC8259_ADD( "pic8259_1", calchase_pic8259_1_config )
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MCFG_PIC8259_ADD( "pic8259_2", calchase_pic8259_2_config )
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MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
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MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
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MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, calchase_state, ide_interrupt))
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MCFG_MC146818_ADD( "rtc", MC146818_STANDARD )
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MCFG_PCI_BUS_LEGACY_ADD("pcibus", 0)
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@ -418,6 +418,7 @@ public:
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DECLARE_READ8_MEMBER(get_slave_ack);
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DECLARE_WRITE_LINE_MEMBER(chihiro_pit8254_out0_changed);
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DECLARE_WRITE_LINE_MEMBER(chihiro_pit8254_out2_changed);
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DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
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};
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/*
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@ -1471,10 +1472,9 @@ WRITE32_MEMBER( chihiro_state::ide_w )
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ide_controller_w(chihiro_devs.ide, offset+0x01f0, size, data);
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}
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static void ide_interrupt(device_t *device, int state)
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WRITE_LINE_MEMBER(chihiro_state::ide_interrupt)
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{
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chihiro_state *chst=device->machine().driver_data<chihiro_state>();
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pic8259_ir6_w(chst->chihiro_devs.pic8259_2, state); // IRQ 14
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pic8259_ir6_w(chihiro_devs.pic8259_2, state); // IRQ 14
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}
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// ======================> ide_baseboard_device
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@ -1823,13 +1823,6 @@ static SLOT_INTERFACE_START(ide_baseboard)
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SLOT_INTERFACE("bb", IDE_BASEBOARD)
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SLOT_INTERFACE_END
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static const ide_config ide_intf =
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{
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ide_interrupt,
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"maincpu",
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AS_PROGRAM
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};
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static MACHINE_CONFIG_START( chihiro_base, chihiro_state )
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/* basic machine hardware */
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@ -1851,7 +1844,9 @@ static MACHINE_CONFIG_START( chihiro_base, chihiro_state )
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MCFG_PIC8259_ADD( "pic8259_1", chihiro_pic8259_1_config )
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MCFG_PIC8259_ADD( "pic8259_2", chihiro_pic8259_2_config )
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MCFG_PIT8254_ADD( "pit8254", chihiro_pit8254_config )
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MCFG_IDE_CONTROLLER_ADD( "ide", ide_intf , ide_baseboard, NULL, "bb", true)
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MCFG_IDE_CONTROLLER_ADD( "ide", ide_baseboard, NULL, "bb", true)
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MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, chihiro_state, ide_interrupt))
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MCFG_IDE_CONTROLLER_BUS_MASTER("maincpu", AS_PROGRAM)
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/* video hardware */
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MCFG_SCREEN_ADD("screen", RASTER)
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@ -652,6 +652,8 @@ public:
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DECLARE_READ64_MEMBER(gfx_fifo_r);
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DECLARE_WRITE64_MEMBER(gfx_buf_w);
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DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
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cobra_renderer *m_renderer;
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cobra_fifo *m_gfxfifo_in;
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@ -3173,17 +3175,15 @@ static const k001604_interface cobra_k001604_intf =
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};
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static void ide_interrupt(device_t *device, int state)
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WRITE_LINE_MEMBER(cobra_state::ide_interrupt)
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{
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cobra_state *cobra = device->machine().driver_data<cobra_state>();
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if (state == CLEAR_LINE)
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{
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cobra->m_sub_interrupt |= 0x80;
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m_sub_interrupt |= 0x80;
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}
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else
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{
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cobra->m_sub_interrupt &= ~0x80;
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m_sub_interrupt &= ~0x80;
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}
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}
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@ -3200,10 +3200,10 @@ INTERRUPT_GEN_MEMBER(cobra_state::cobra_vblank)
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void cobra_state::machine_reset()
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{
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m_sub_interrupt = 0xff;
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UINT8 *ide_features = ide_get_features(machine().device("ide"), 0);
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ide_controller_device *ide = (ide_controller_device *) machine().device("ide");
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UINT8 *ide_features = ide->ide_get_features(0);
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// Cobra expects these settings or the BIOS fails
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ide_features[51*2+0] = 0; /* 51: PIO data transfer cycle timing mode */
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@ -3223,13 +3223,6 @@ void cobra_state::machine_reset()
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dmadac_set_frequency(&m_dmadac[1], 1, 44100);
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}
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static const ide_config ide_intf =
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{
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ide_interrupt,
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NULL,
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0
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};
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static MACHINE_CONFIG_START( cobra, cobra_state )
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/* basic machine hardware */
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@ -3251,7 +3244,8 @@ static MACHINE_CONFIG_START( cobra, cobra_state )
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MCFG_PCI_BUS_LEGACY_ADD("pcibus", 0)
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MCFG_PCI_BUS_LEGACY_DEVICE(0, NULL, mpc106_pci_r, mpc106_pci_w)
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MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
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MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
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MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, cobra_state, ide_interrupt))
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/* video hardware */
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@ -411,17 +411,17 @@ INTERRUPT_GEN_MEMBER(djmain_state::vb_interrupt)
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}
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static void ide_interrupt(device_t *device, int state)
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WRITE_LINE_MEMBER( djmain_state::ide_interrupt )
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{
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if (state != CLEAR_LINE)
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{
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//logerror("IDE interrupt asserted\n");
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device->machine().device("maincpu")->execute().set_input_line(M68K_IRQ_1, HOLD_LINE);
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device().machine().device("maincpu")->execute().set_input_line(M68K_IRQ_1, HOLD_LINE);
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}
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else
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{
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//logerror("IDE interrupt cleared\n");
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device->machine().device("maincpu")->execute().set_input_line(M68K_IRQ_1, CLEAR_LINE);
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device().machine().device("maincpu")->execute().set_input_line(M68K_IRQ_1, CLEAR_LINE);
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}
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}
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@ -1397,12 +1397,12 @@ static const k054539_interface k054539_config =
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void djmain_state::machine_start()
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{
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device_t *ide = machine().device("ide");
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ide_controller_device *ide = (ide_controller_device *) machine().device("ide");
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if (ide != NULL && m_ide_master_password != NULL)
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ide_set_master_password(ide, m_ide_master_password);
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ide->ide_set_master_password(m_ide_master_password);
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if (ide != NULL && m_ide_user_password != NULL)
|
||||
ide_set_user_password(ide, m_ide_user_password);
|
||||
ide->ide_set_user_password(m_ide_user_password);
|
||||
|
||||
state_save_register_global(machine(), m_sndram_bank);
|
||||
state_save_register_global(machine(), m_pending_vb_int);
|
||||
@ -1445,13 +1445,6 @@ static const k056832_interface djmain_k056832_intf =
|
||||
djmain_tile_callback, "none"
|
||||
};
|
||||
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
ide_interrupt,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
|
||||
static MACHINE_CONFIG_START( djmain, djmain_state )
|
||||
|
||||
/* basic machine hardware */
|
||||
@ -1462,7 +1455,8 @@ static MACHINE_CONFIG_START( djmain, djmain_state )
|
||||
MCFG_CPU_VBLANK_INT_DRIVER("screen", djmain_state, vb_interrupt)
|
||||
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, djmain_state, ide_interrupt))
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_ADD("screen", RASTER)
|
||||
|
||||
@ -162,6 +162,7 @@ public:
|
||||
DECLARE_READ8_MEMBER(io20_r);
|
||||
DECLARE_WRITE8_MEMBER(io20_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(funkball_pic8259_1_set_int_line);
|
||||
DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
|
||||
virtual void machine_start();
|
||||
virtual void machine_reset();
|
||||
UINT32 screen_update_funkball(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
|
||||
@ -1100,10 +1101,9 @@ static IRQ_CALLBACK(irq_callback)
|
||||
return pic8259_acknowledge( state->m_pic8259_1);
|
||||
}
|
||||
|
||||
static void ide_interrupt(device_t *device, int state)
|
||||
WRITE_LINE_MEMBER(funkball_state::ide_interrupt)
|
||||
{
|
||||
funkball_state *drvstate = device->machine().driver_data<funkball_state>();
|
||||
pic8259_ir6_w(drvstate->m_pic8259_2, state);
|
||||
pic8259_ir6_w(m_pic8259_2, state);
|
||||
}
|
||||
|
||||
void funkball_state::machine_start()
|
||||
@ -1141,13 +1141,6 @@ UINT32 funkball_state::screen_update_funkball(screen_device &screen, bitmap_rgb3
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
ide_interrupt,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
|
||||
static const voodoo_config voodoo_intf =
|
||||
{
|
||||
2, // fbmem;
|
||||
@ -1177,7 +1170,8 @@ static MACHINE_CONFIG_START( funkball, funkball_state )
|
||||
MCFG_PCI_BUS_LEGACY_DEVICE(7, "voodoo_0", voodoo_0_pci_r, voodoo_0_pci_w)
|
||||
MCFG_PCI_BUS_LEGACY_DEVICE(18, NULL, cx5510_pci_r, cx5510_pci_w)
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, funkball_state, ide_interrupt))
|
||||
|
||||
/* video hardware */
|
||||
MCFG_3DFX_VOODOO_1_ADD("voodoo_0", STD_VOODOO_1_CLOCK, voodoo_intf)
|
||||
|
||||
@ -114,6 +114,7 @@ public:
|
||||
DECLARE_WRITE_LINE_MEMBER(pc_dack2_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(pc_dack3_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(gamecstl_pic8259_1_set_int_line);
|
||||
DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
|
||||
DECLARE_READ8_MEMBER(get_slave_ack);
|
||||
DECLARE_DRIVER_INIT(gamecstl);
|
||||
virtual void machine_start();
|
||||
@ -123,9 +124,6 @@ public:
|
||||
};
|
||||
|
||||
|
||||
static void ide_interrupt(device_t *device, int state);
|
||||
|
||||
|
||||
static const rgb_t cga_palette[16] =
|
||||
{
|
||||
MAKE_RGB( 0x00, 0x00, 0x00 ), MAKE_RGB( 0x00, 0x00, 0xaa ), MAKE_RGB( 0x00, 0xaa, 0x00 ), MAKE_RGB( 0x00, 0xaa, 0xaa ),
|
||||
@ -687,13 +685,6 @@ static const struct pit8253_config gamecstl_pit8254_config =
|
||||
}
|
||||
};
|
||||
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
ide_interrupt,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
|
||||
static MACHINE_CONFIG_START( gamecstl, gamecstl_state )
|
||||
|
||||
/* basic machine hardware */
|
||||
@ -716,7 +707,8 @@ static MACHINE_CONFIG_START( gamecstl, gamecstl_state )
|
||||
|
||||
MCFG_PIC8259_ADD( "pic8259_2", gamecstl_pic8259_2_config )
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, gamecstl_state, ide_interrupt))
|
||||
|
||||
MCFG_MC146818_ADD( "rtc", MC146818_STANDARD )
|
||||
|
||||
@ -745,10 +737,9 @@ static void keyboard_interrupt(running_machine &machine, int state)
|
||||
pic8259_ir1_w(drvstate->m_pic8259_1, state);
|
||||
}
|
||||
|
||||
static void ide_interrupt(device_t *device, int state)
|
||||
WRITE_LINE_MEMBER(gamecstl_state::ide_interrupt)
|
||||
{
|
||||
gamecstl_state *drvstate = device->machine().driver_data<gamecstl_state>();
|
||||
pic8259_ir6_w(drvstate->m_pic8259_2, state);
|
||||
pic8259_ir6_w(m_pic8259_2, state);
|
||||
}
|
||||
|
||||
static int gamecstl_get_out2(running_machine &machine)
|
||||
|
||||
@ -1564,13 +1564,6 @@ static const jaguar_cpu_config dsp_config =
|
||||
&jaguar_state::dsp_cpu_int
|
||||
};
|
||||
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
&jaguar_state::external_int,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
|
||||
static MACHINE_CONFIG_START( cojagr3k, jaguar_state )
|
||||
|
||||
/* basic machine hardware */
|
||||
@ -1588,7 +1581,8 @@ static MACHINE_CONFIG_START( cojagr3k, jaguar_state )
|
||||
|
||||
MCFG_NVRAM_ADD_1FILL("nvram")
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, jaguar_state, external_int))
|
||||
|
||||
/* video hardware */
|
||||
MCFG_VIDEO_ATTRIBUTES(VIDEO_UPDATE_BEFORE_VBLANK)
|
||||
|
||||
@ -158,6 +158,7 @@ public:
|
||||
DECLARE_WRITE32_MEMBER(kinst_ide_w);
|
||||
DECLARE_READ32_MEMBER(kinst_ide_extra_r);
|
||||
DECLARE_WRITE32_MEMBER(kinst_ide_extra_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
|
||||
DECLARE_DRIVER_INIT(kinst);
|
||||
DECLARE_DRIVER_INIT(kinst2);
|
||||
virtual void machine_start();
|
||||
@ -201,8 +202,8 @@ void kinst_state::machine_start()
|
||||
|
||||
void kinst_state::machine_reset()
|
||||
{
|
||||
device_t *ide = machine().device("ide");
|
||||
UINT8 *features = ide_get_features(ide,0);
|
||||
ide_controller_device *ide = (ide_controller_device *) machine().device("ide");
|
||||
UINT8 *features = ide->ide_get_features(0);
|
||||
|
||||
if (strncmp(machine().system().name, "kinst2", 6) != 0)
|
||||
{
|
||||
@ -290,9 +291,9 @@ INTERRUPT_GEN_MEMBER(kinst_state::irq0_start)
|
||||
}
|
||||
|
||||
|
||||
static void ide_interrupt(device_t *device, int state)
|
||||
WRITE_LINE_MEMBER(kinst_state::ide_interrupt)
|
||||
{
|
||||
device->machine().device("maincpu")->execute().set_input_line(1, state);
|
||||
machine().device("maincpu")->execute().set_input_line(1, state);
|
||||
}
|
||||
|
||||
|
||||
@ -664,13 +665,6 @@ static const mips3_config r4600_config =
|
||||
16384 /* data cache size */
|
||||
};
|
||||
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
ide_interrupt,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
|
||||
static MACHINE_CONFIG_START( kinst, kinst_state )
|
||||
|
||||
/* basic machine hardware */
|
||||
@ -680,7 +674,8 @@ static MACHINE_CONFIG_START( kinst, kinst_state )
|
||||
MCFG_CPU_VBLANK_INT_DRIVER("screen", kinst_state, irq0_start)
|
||||
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, kinst_state, ide_interrupt))
|
||||
|
||||
/* video hardware */
|
||||
MCFG_VIDEO_ATTRIBUTES(VIDEO_UPDATE_BEFORE_VBLANK)
|
||||
|
||||
@ -180,6 +180,7 @@ public:
|
||||
DECLARE_WRITE_LINE_MEMBER(pc_dack2_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(pc_dack3_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(mediagx_pic8259_1_set_int_line);
|
||||
DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
|
||||
DECLARE_READ8_MEMBER(get_slave_ack);
|
||||
DECLARE_DRIVER_INIT(a51site4);
|
||||
virtual void machine_start();
|
||||
@ -230,7 +231,6 @@ public:
|
||||
#define DC_CFIFO_DIAG 0x7c/4
|
||||
|
||||
|
||||
static void ide_interrupt(device_t *device, int state);
|
||||
|
||||
|
||||
|
||||
@ -1163,13 +1163,6 @@ static RAMDAC_INTERFACE( ramdac_intf )
|
||||
0
|
||||
};
|
||||
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
ide_interrupt,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
|
||||
static MACHINE_CONFIG_START( mediagx, mediagx_state )
|
||||
|
||||
/* basic machine hardware */
|
||||
@ -1191,7 +1184,8 @@ static MACHINE_CONFIG_START( mediagx, mediagx_state )
|
||||
|
||||
MCFG_PIC8259_ADD( "pic8259_slave", mediagx_pic8259_2_config )
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, mediagx_state, ide_interrupt))
|
||||
|
||||
MCFG_TIMER_DRIVER_ADD("sound_timer", mediagx_state, sound_timer_callback)
|
||||
|
||||
@ -1232,11 +1226,9 @@ static void keyboard_interrupt(running_machine &machine, int _state)
|
||||
pic8259_ir1_w(state->m_pic8259_1, _state);
|
||||
}
|
||||
|
||||
static void ide_interrupt(device_t *device, int _state)
|
||||
WRITE_LINE_MEMBER( mediagx_state::ide_interrupt )
|
||||
{
|
||||
mediagx_state *state = device->machine().driver_data<mediagx_state>();
|
||||
|
||||
pic8259_ir6_w(state->m_pic8259_2, _state);
|
||||
pic8259_ir6_w(m_pic8259_2, state);
|
||||
}
|
||||
|
||||
static int mediagx_get_out2(running_machine &machine)
|
||||
|
||||
@ -96,6 +96,7 @@ public:
|
||||
DECLARE_WRITE_LINE_MEMBER(pc_dack2_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(pc_dack3_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(midqslvr_pic8259_1_set_int_line);
|
||||
DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
|
||||
virtual void machine_start();
|
||||
virtual void machine_reset();
|
||||
};
|
||||
@ -649,10 +650,9 @@ static IRQ_CALLBACK(irq_callback)
|
||||
return pic8259_acknowledge( state->m_pic8259_1);
|
||||
}
|
||||
|
||||
static void ide_interrupt(device_t *device, int state)
|
||||
WRITE_LINE_MEMBER(midqslvr_state::ide_interrupt)
|
||||
{
|
||||
midqslvr_state *drvstate = device->machine().driver_data<midqslvr_state>();
|
||||
pic8259_ir6_w(drvstate->m_pic8259_2, state);
|
||||
pic8259_ir6_w(m_pic8259_2, state);
|
||||
}
|
||||
|
||||
void midqslvr_state::machine_start()
|
||||
@ -685,13 +685,6 @@ void midqslvr_state::machine_reset()
|
||||
machine().root_device().membank("video_bank2")->set_base(machine().root_device().memregion("video_bios")->base() + 0x4000);
|
||||
}
|
||||
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
ide_interrupt,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
|
||||
static MACHINE_CONFIG_START( midqslvr, midqslvr_state )
|
||||
MCFG_CPU_ADD("maincpu", PENTIUM, 333000000) // actually Celeron 333
|
||||
MCFG_CPU_PROGRAM_MAP(midqslvr_map)
|
||||
@ -710,7 +703,8 @@ static MACHINE_CONFIG_START( midqslvr, midqslvr_state )
|
||||
MCFG_PCI_BUS_LEGACY_DEVICE( 0, NULL, intel82439tx_pci_r, intel82439tx_pci_w)
|
||||
MCFG_PCI_BUS_LEGACY_DEVICE(31, NULL, intel82371ab_pci_r, intel82371ab_pci_w)
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, midqslvr_state, ide_interrupt))
|
||||
|
||||
/* video hardware */
|
||||
MCFG_FRAGMENT_ADD( pcvideo_vga )
|
||||
|
||||
@ -1037,13 +1037,6 @@ static MACHINE_CONFIG_DERIVED( midvunit, midvcommon )
|
||||
MCFG_FRAGMENT_ADD(dcs_audio_2k)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
NULL,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
|
||||
static MACHINE_CONFIG_DERIVED( midvplus, midvcommon )
|
||||
|
||||
/* basic machine hardware */
|
||||
@ -1055,7 +1048,7 @@ static MACHINE_CONFIG_DERIVED( midvplus, midvcommon )
|
||||
MCFG_DEVICE_REMOVE("nvram")
|
||||
MCFG_NVRAM_HANDLER(midway_serial_pic2)
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
|
||||
|
||||
/* sound hardware */
|
||||
MCFG_FRAGMENT_ADD(dcs2_audio_2115)
|
||||
|
||||
@ -278,15 +278,14 @@ TIMER_DEVICE_CALLBACK_MEMBER(qdrmfgp_state::qdrmfgp_interrupt)
|
||||
m_maincpu->set_input_line(3, HOLD_LINE);
|
||||
}
|
||||
|
||||
static void ide_interrupt(device_t *device, int state)
|
||||
WRITE_LINE_MEMBER(qdrmfgp_state::ide_interrupt)
|
||||
{
|
||||
qdrmfgp_state *drvstate = device->machine().driver_data<qdrmfgp_state>();
|
||||
if (drvstate->m_control & 0x0008)
|
||||
if (m_control & 0x0008)
|
||||
{
|
||||
if (state != CLEAR_LINE)
|
||||
device->machine().device("maincpu")->execute().set_input_line(4, HOLD_LINE);
|
||||
machine().device("maincpu")->execute().set_input_line(4, HOLD_LINE);
|
||||
else
|
||||
device->machine().device("maincpu")->execute().set_input_line(4, CLEAR_LINE);
|
||||
machine().device("maincpu")->execute().set_input_line(4, CLEAR_LINE);
|
||||
}
|
||||
}
|
||||
|
||||
@ -305,21 +304,20 @@ INTERRUPT_GEN_MEMBER(qdrmfgp_state::qdrmfgp2_interrupt)
|
||||
device.execute().set_input_line(4, HOLD_LINE);
|
||||
}
|
||||
|
||||
static void gp2_ide_interrupt(device_t *device, int state)
|
||||
WRITE_LINE_MEMBER(qdrmfgp_state::gp2_ide_interrupt)
|
||||
{
|
||||
qdrmfgp_state *drvstate = device->machine().driver_data<qdrmfgp_state>();
|
||||
if (drvstate->m_control & 0x0010)
|
||||
if (m_control & 0x0010)
|
||||
{
|
||||
if (state != CLEAR_LINE)
|
||||
{
|
||||
if (drvstate->m_gp2_irq_control)
|
||||
drvstate->m_gp2_irq_control = 0;
|
||||
if (m_gp2_irq_control)
|
||||
m_gp2_irq_control = 0;
|
||||
else
|
||||
device->machine().device("maincpu")->execute().set_input_line(5, HOLD_LINE);
|
||||
machine().device("maincpu")->execute().set_input_line(5, HOLD_LINE);
|
||||
}
|
||||
else
|
||||
{
|
||||
device->machine().device("maincpu")->execute().set_input_line(5, CLEAR_LINE);
|
||||
machine().device("maincpu")->execute().set_input_line(5, CLEAR_LINE);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -662,13 +660,6 @@ void qdrmfgp_state::machine_reset()
|
||||
* Machine driver
|
||||
*
|
||||
*************************************/
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
ide_interrupt,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
|
||||
static MACHINE_CONFIG_START( qdrmfgp, qdrmfgp_state )
|
||||
|
||||
/* basic machine hardware */
|
||||
@ -679,7 +670,8 @@ static MACHINE_CONFIG_START( qdrmfgp, qdrmfgp_state )
|
||||
MCFG_MACHINE_START_OVERRIDE(qdrmfgp_state,qdrmfgp)
|
||||
MCFG_NVRAM_ADD_1FILL("nvram")
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, qdrmfgp_state, ide_interrupt))
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_ADD("screen", RASTER)
|
||||
@ -704,12 +696,6 @@ static MACHINE_CONFIG_START( qdrmfgp, qdrmfgp_state )
|
||||
MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
static const ide_config qdrmfgp2_ide_intf =
|
||||
{
|
||||
gp2_ide_interrupt,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
static MACHINE_CONFIG_START( qdrmfgp2, qdrmfgp_state )
|
||||
|
||||
/* basic machine hardware */
|
||||
@ -720,7 +706,8 @@ static MACHINE_CONFIG_START( qdrmfgp2, qdrmfgp_state )
|
||||
MCFG_MACHINE_START_OVERRIDE(qdrmfgp_state,qdrmfgp2)
|
||||
MCFG_NVRAM_ADD_1FILL("nvram")
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", qdrmfgp2_ide_intf, ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, qdrmfgp_state, gp2_ide_interrupt))
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_ADD("screen", RASTER)
|
||||
|
||||
@ -107,6 +107,7 @@ public:
|
||||
DECLARE_WRITE_LINE_MEMBER(pc_dack2_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(pc_dack3_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(queen_pic8259_1_set_int_line);
|
||||
DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
|
||||
virtual void machine_start();
|
||||
virtual void machine_reset();
|
||||
};
|
||||
@ -632,10 +633,9 @@ static IRQ_CALLBACK(irq_callback)
|
||||
return pic8259_acknowledge( state->m_pic8259_1);
|
||||
}
|
||||
|
||||
static void ide_interrupt(device_t *device, int state)
|
||||
WRITE_LINE_MEMBER( queen_state::ide_interrupt )
|
||||
{
|
||||
queen_state *drvstate = device->machine().driver_data<queen_state>();
|
||||
pic8259_ir6_w(drvstate->m_pic8259_2, state);
|
||||
pic8259_ir6_w(m_pic8259_2, state);
|
||||
}
|
||||
|
||||
void queen_state::machine_start()
|
||||
@ -670,13 +670,6 @@ void queen_state::machine_reset()
|
||||
|
||||
|
||||
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
ide_interrupt,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
|
||||
static MACHINE_CONFIG_START( queen, queen_state )
|
||||
MCFG_CPU_ADD("maincpu", PENTIUM, 533000000/16) // Celeron or Pentium 3, 533 Mhz
|
||||
MCFG_CPU_PROGRAM_MAP(queen_map)
|
||||
@ -695,7 +688,8 @@ static MACHINE_CONFIG_START( queen, queen_state )
|
||||
MCFG_PCI_BUS_LEGACY_DEVICE(0, NULL, intel82439tx_pci_r, intel82439tx_pci_w)
|
||||
MCFG_PCI_BUS_LEGACY_DEVICE(7, NULL, intel82371ab_pci_r, intel82371ab_pci_w)
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, queen_state, ide_interrupt))
|
||||
|
||||
/* video hardware */
|
||||
MCFG_FRAGMENT_ADD( pcvideo_vga )
|
||||
|
||||
@ -92,6 +92,7 @@ public:
|
||||
DECLARE_WRITE_LINE_MEMBER(pc_dack2_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(pc_dack3_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(savquest_pic8259_1_set_int_line);
|
||||
DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
|
||||
virtual void machine_start();
|
||||
virtual void machine_reset();
|
||||
};
|
||||
@ -513,10 +514,9 @@ static IRQ_CALLBACK(irq_callback)
|
||||
return pic8259_acknowledge( state->m_pic8259_1);
|
||||
}
|
||||
|
||||
static void ide_interrupt(device_t *device, int state)
|
||||
WRITE_LINE_MEMBER(savquest_state::ide_interrupt)
|
||||
{
|
||||
savquest_state *drvstate = device->machine().driver_data<savquest_state>();
|
||||
pic8259_ir6_w(drvstate->m_pic8259_2, state);
|
||||
pic8259_ir6_w(m_pic8259_2, state);
|
||||
}
|
||||
|
||||
void savquest_state::machine_start()
|
||||
@ -536,13 +536,6 @@ void savquest_state::machine_reset()
|
||||
machine().root_device().membank("bank1")->set_base(machine().root_device().memregion("bios")->base() + 0x20000);
|
||||
}
|
||||
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
ide_interrupt,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
|
||||
static MACHINE_CONFIG_START( savquest, savquest_state )
|
||||
MCFG_CPU_ADD("maincpu", PENTIUM, 450000000) // actually Pentium II 450
|
||||
MCFG_CPU_PROGRAM_MAP(savquest_map)
|
||||
@ -561,7 +554,8 @@ static MACHINE_CONFIG_START( savquest, savquest_state )
|
||||
MCFG_PCI_BUS_LEGACY_DEVICE(0, NULL, intel82439tx_pci_r, intel82439tx_pci_w)
|
||||
MCFG_PCI_BUS_LEGACY_DEVICE(7, NULL, intel82371ab_pci_r, intel82371ab_pci_w)
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, savquest_state, ide_interrupt))
|
||||
|
||||
/* video hardware */
|
||||
MCFG_FRAGMENT_ADD( pcvideo_vga )
|
||||
|
||||
@ -479,6 +479,7 @@ public:
|
||||
DECLARE_READ32_MEMBER(widget_r);
|
||||
DECLARE_WRITE32_MEMBER(widget_w);
|
||||
DECLARE_READ32_MEMBER(seattle_ide_r);
|
||||
DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
|
||||
DECLARE_DRIVER_INIT(sfrush);
|
||||
DECLARE_DRIVER_INIT(blitz2k);
|
||||
DECLARE_DRIVER_INIT(carnevil);
|
||||
@ -619,9 +620,9 @@ void seattle_state::machine_reset()
|
||||
*
|
||||
*************************************/
|
||||
|
||||
static void ide_interrupt(device_t *device, int state)
|
||||
WRITE_LINE_MEMBER(seattle_state::ide_interrupt)
|
||||
{
|
||||
device->machine().device("maincpu")->execute().set_input_line(IDE_IRQ_NUM, state);
|
||||
machine().device("maincpu")->execute().set_input_line(IDE_IRQ_NUM, state);
|
||||
}
|
||||
|
||||
|
||||
@ -2523,13 +2524,6 @@ static const mips3_config r5000_config =
|
||||
SYSTEM_CLOCK /* system clock rate */
|
||||
};
|
||||
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
ide_interrupt,
|
||||
"maincpu",
|
||||
AS_PROGRAM
|
||||
};
|
||||
|
||||
static const voodoo_config voodoo_intf =
|
||||
{
|
||||
2, // fbmem;
|
||||
@ -2550,7 +2544,9 @@ static MACHINE_CONFIG_START( seattle_common, seattle_state )
|
||||
|
||||
MCFG_NVRAM_ADD_1FILL("nvram")
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, seattle_state, ide_interrupt))
|
||||
MCFG_IDE_CONTROLLER_BUS_MASTER("maincpu", AS_PROGRAM)
|
||||
|
||||
MCFG_3DFX_VOODOO_1_ADD("voodoo", STD_VOODOO_1_CLOCK, voodoo_intf)
|
||||
|
||||
|
||||
@ -405,9 +405,11 @@ static void rf5c296_reg_w(ATTR_UNUSED running_machine &machine, UINT8 reg, UINT8
|
||||
// Check for card reset
|
||||
if (!(data & 0x40))
|
||||
{
|
||||
machine.device(":card")->reset();
|
||||
ide_controller_device *card = (ide_controller_device *) machine.device(":card");
|
||||
|
||||
card->reset();
|
||||
state->m_locked = 0x1ff;
|
||||
ide_set_gnet_readlock (machine.device(":card"), 1);
|
||||
card->ide_set_gnet_readlock(1);
|
||||
}
|
||||
break;
|
||||
|
||||
@ -490,8 +492,10 @@ WRITE32_MEMBER(taitogn_state::rf5c296_mem_w)
|
||||
m_locked &= ~(1 << pos);
|
||||
else
|
||||
m_locked |= 1 << pos;
|
||||
if (!m_locked) {
|
||||
ide_set_gnet_readlock (machine().device(":card"), 0);
|
||||
if (!m_locked)
|
||||
{
|
||||
ide_controller_device *card = (ide_controller_device *) machine().device(":card");
|
||||
card->ide_set_gnet_readlock(0);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -889,8 +893,10 @@ MACHINE_RESET_MEMBER(taitogn_state,coh3002t)
|
||||
m_locked = 0x1ff;
|
||||
install_handlers(machine(), 0);
|
||||
m_control = 0;
|
||||
machine().device(":card")->reset();
|
||||
ide_set_gnet_readlock(machine().device(":card"), 1);
|
||||
|
||||
ide_controller_device *card = (ide_controller_device *) machine().device(":card");
|
||||
card->reset();
|
||||
card->ide_set_gnet_readlock(1);
|
||||
|
||||
// halt sound CPU since it has no valid program at start
|
||||
machine().device("mn10200")->execute().set_input_line(INPUT_LINE_RESET,ASSERT_LINE); /* MCU */
|
||||
@ -930,13 +936,6 @@ static ADDRESS_MAP_START( taitogn_map, AS_PROGRAM, 32, taitogn_state )
|
||||
ADDRESS_MAP_END
|
||||
|
||||
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
NULL,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
|
||||
static MACHINE_CONFIG_START( coh3002t, taitogn_state )
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD( "maincpu", CXD8661R, XTAL_100MHz )
|
||||
@ -955,7 +954,7 @@ static MACHINE_CONFIG_START( coh3002t, taitogn_state )
|
||||
MCFG_MACHINE_RESET_OVERRIDE(taitogn_state, coh3002t )
|
||||
|
||||
MCFG_AT28C16_ADD( "at28c16", 0 )
|
||||
MCFG_IDE_CONTROLLER_ADD( "card", ide_intf, ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_ADD( "card", ide_devices, "hdd", NULL, true)
|
||||
|
||||
MCFG_MB3773_ADD("mb3773")
|
||||
|
||||
|
||||
@ -530,6 +530,7 @@ public:
|
||||
DECLARE_WRITE8_MEMBER(tlcs_ide0_w);
|
||||
DECLARE_READ8_MEMBER(tlcs_ide1_r);
|
||||
DECLARE_WRITE8_MEMBER(tlcs_ide1_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
|
||||
};
|
||||
|
||||
|
||||
@ -2424,7 +2425,8 @@ INPUT_PORTS_END
|
||||
|
||||
static void set_ide_drive_serial_number(device_t *device, int drive, const char *serial)
|
||||
{
|
||||
UINT8 *ide_features = ide_get_features(device, drive);
|
||||
ide_controller_device *ide = (ide_controller_device *) device;
|
||||
UINT8 *ide_features = ide->ide_get_features(drive);
|
||||
|
||||
for (int i=0; i < 20; i++)
|
||||
{
|
||||
@ -2459,9 +2461,9 @@ INTERRUPT_GEN_MEMBER(taitotz_state::taitotz_vbi)
|
||||
machine().device("iocpu")->execute().set_input_line(TLCS900_INT3, ASSERT_LINE);
|
||||
}
|
||||
|
||||
static void ide_interrupt(device_t *device, int state)
|
||||
WRITE_LINE_MEMBER(taitotz_state::ide_interrupt)
|
||||
{
|
||||
device->machine().device("iocpu")->execute().set_input_line(TLCS900_INT2, state);
|
||||
machine().device("iocpu")->execute().set_input_line(TLCS900_INT2, state);
|
||||
}
|
||||
|
||||
static const powerpc_config ppc603e_config =
|
||||
@ -2479,13 +2481,6 @@ static const tlcs900_interface taitotz_tlcs900_interface =
|
||||
DEVCB_DRIVER_MEMBER(taitotz_state, tlcs900_port_write),
|
||||
};
|
||||
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
ide_interrupt,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
|
||||
static MACHINE_CONFIG_START( taitotz, taitotz_state )
|
||||
/* IBM EMPPC603eBG-100 */
|
||||
MCFG_CPU_ADD("maincpu", PPC603E, 100000000)
|
||||
@ -2502,8 +2497,9 @@ static MACHINE_CONFIG_START( taitotz, taitotz_state )
|
||||
|
||||
MCFG_QUANTUM_TIME(attotime::from_hz(120))
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, taitotz_state, ide_interrupt))
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
|
||||
MCFG_NVRAM_ADD_0FILL("nvram")
|
||||
|
||||
MCFG_SCREEN_ADD("screen", RASTER)
|
||||
|
||||
@ -77,6 +77,7 @@ public:
|
||||
DECLARE_WRITE_LINE_MEMBER(pc_dack2_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(pc_dack3_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(taitowlf_pic8259_1_set_int_line);
|
||||
DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
|
||||
DECLARE_READ8_MEMBER(get_slave_ack);
|
||||
DECLARE_DRIVER_INIT(taitowlf);
|
||||
virtual void machine_start();
|
||||
@ -114,8 +115,6 @@ UINT32 taitowlf_state::screen_update_taitowlf(screen_device &screen, bitmap_rgb3
|
||||
}
|
||||
#endif
|
||||
|
||||
static void ide_interrupt(device_t *device, int state);
|
||||
|
||||
|
||||
READ8_MEMBER(taitowlf_state::at_dma8237_2_r)
|
||||
{
|
||||
@ -628,13 +627,6 @@ void taitowlf_state::palette_init()
|
||||
}
|
||||
#endif
|
||||
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
ide_interrupt,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
|
||||
static MACHINE_CONFIG_START( taitowlf, taitowlf_state )
|
||||
|
||||
/* basic machine hardware */
|
||||
@ -652,7 +644,8 @@ static MACHINE_CONFIG_START( taitowlf, taitowlf_state )
|
||||
MCFG_I8237_ADD( "dma8237_2", XTAL_14_31818MHz/3, dma8237_2_config )
|
||||
MCFG_PIC8259_ADD( "pic8259_1", taitowlf_pic8259_1_config )
|
||||
MCFG_PIC8259_ADD( "pic8259_2", taitowlf_pic8259_2_config )
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, taitowlf_state, ide_interrupt))
|
||||
MCFG_MC146818_ADD( "rtc", MC146818_STANDARD )
|
||||
|
||||
/* video hardware */
|
||||
@ -681,10 +674,9 @@ static void keyboard_interrupt(running_machine &machine, int state)
|
||||
pic8259_ir1_w(drvstate->m_pic8259_1, state);
|
||||
}
|
||||
|
||||
static void ide_interrupt(device_t *device, int state)
|
||||
WRITE_LINE_MEMBER(taitowlf_state::ide_interrupt)
|
||||
{
|
||||
taitowlf_state *drvstate = device->machine().driver_data<taitowlf_state>();
|
||||
pic8259_ir6_w(drvstate->m_pic8259_2, state);
|
||||
pic8259_ir6_w(m_pic8259_2, state);
|
||||
}
|
||||
|
||||
static int taitowlf_get_out2(running_machine &machine)
|
||||
|
||||
@ -271,6 +271,7 @@ public:
|
||||
DECLARE_WRITE16_MEMBER(shared_68k_w);
|
||||
DECLARE_READ16_MEMBER(twinkle_ide_r);
|
||||
DECLARE_WRITE16_MEMBER(twinkle_ide_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
|
||||
DECLARE_DRIVER_INIT(twinkle);
|
||||
};
|
||||
|
||||
@ -656,13 +657,11 @@ ADDRESS_MAP_END
|
||||
|
||||
/* SPU board */
|
||||
|
||||
static void ide_interrupt(device_t *device, int state_)
|
||||
WRITE_LINE_MEMBER(twinkle_state::ide_interrupt)
|
||||
{
|
||||
twinkle_state *state = device->machine().driver_data<twinkle_state>();
|
||||
|
||||
if ((state_) && (state->m_spu_ctrl & 0x0400))
|
||||
if ((state) && (m_spu_ctrl & 0x0400))
|
||||
{
|
||||
device->machine().device("audiocpu")->execute().set_input_line(M68K_IRQ_6, ASSERT_LINE);
|
||||
machine().device("audiocpu")->execute().set_input_line(M68K_IRQ_6, ASSERT_LINE);
|
||||
}
|
||||
}
|
||||
|
||||
@ -870,13 +869,6 @@ static const rtc65271_interface twinkle_rtc =
|
||||
DEVCB_NULL
|
||||
};
|
||||
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
ide_interrupt,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
|
||||
static MACHINE_CONFIG_START( twinkle, twinkle_state )
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD( "maincpu", CXD8530CQ, XTAL_67_7376MHz )
|
||||
@ -897,7 +889,9 @@ static MACHINE_CONFIG_START( twinkle, twinkle_state )
|
||||
MCFG_AM53CF96_ADD("scsi:am53cf96")
|
||||
MCFG_AM53CF96_IRQ_HANDLER(DEVWRITELINE("^maincpu:irq", psxirq_device, intin10))
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, twinkle_state, ide_interrupt))
|
||||
|
||||
MCFG_RTC65271_ADD("rtc", twinkle_rtc)
|
||||
|
||||
/* video hardware */
|
||||
|
||||
@ -488,6 +488,7 @@ public:
|
||||
int m_count;
|
||||
int m_dynamic_count;
|
||||
dynamic_address m_dynamic[MAX_DYNAMIC_ADDRESSES];
|
||||
DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
|
||||
DECLARE_DRIVER_INIT(gauntleg);
|
||||
DECLARE_DRIVER_INIT(cartfury);
|
||||
DECLARE_DRIVER_INIT(tenthdeg);
|
||||
@ -514,7 +515,6 @@ public:
|
||||
*************************************/
|
||||
|
||||
|
||||
static void ide_interrupt(device_t *device, int state);
|
||||
static void remap_dynamic_addresses(running_machine &machine);
|
||||
|
||||
|
||||
@ -747,7 +747,7 @@ static WRITE32_HANDLER( pci_ide_w )
|
||||
|
||||
case 0x14: /* interrupt pending */
|
||||
if (data & 4)
|
||||
ide_interrupt(space.machine().device("ide"), 0);
|
||||
state->ide_interrupt(0);
|
||||
break;
|
||||
}
|
||||
if (LOG_PCI)
|
||||
@ -1231,15 +1231,14 @@ static WRITE32_HANDLER( nile_w )
|
||||
*
|
||||
*************************************/
|
||||
|
||||
static void ide_interrupt(device_t *device, int state)
|
||||
WRITE_LINE_MEMBER(vegas_state::ide_interrupt)
|
||||
{
|
||||
vegas_state *drvstate = device->machine().driver_data<vegas_state>();
|
||||
drvstate->m_ide_irq_state = state;
|
||||
m_ide_irq_state = state;
|
||||
if (state)
|
||||
drvstate->m_nile_irq_state |= 0x800;
|
||||
m_nile_irq_state |= 0x800;
|
||||
else
|
||||
drvstate->m_nile_irq_state &= ~0x800;
|
||||
update_nile_irqs(device->machine());
|
||||
m_nile_irq_state &= ~0x800;
|
||||
update_nile_irqs(machine());
|
||||
}
|
||||
|
||||
|
||||
@ -2221,13 +2220,6 @@ static const mips3_config r5000_config =
|
||||
SYSTEM_CLOCK /* system clock rate */
|
||||
};
|
||||
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
ide_interrupt,
|
||||
"maincpu",
|
||||
AS_PROGRAM
|
||||
};
|
||||
|
||||
static const smc91c9x_config ethernet_intf =
|
||||
{
|
||||
ethernet_interrupt
|
||||
@ -2253,7 +2245,9 @@ static MACHINE_CONFIG_START( vegascore, vegas_state )
|
||||
|
||||
MCFG_M48T37_ADD("timekeeper")
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, vegas_state, ide_interrupt))
|
||||
MCFG_IDE_CONTROLLER_BUS_MASTER("maincpu", AS_PROGRAM)
|
||||
|
||||
MCFG_SMC91C94_ADD("ethernet", ethernet_intf)
|
||||
|
||||
|
||||
@ -1996,10 +1996,6 @@ static void voodoo_vblank(device_t *device, int state)
|
||||
mpc8240_interrupt(device->machine(), MPC8240_IRQ4);
|
||||
}
|
||||
|
||||
static void ide_interrupt(device_t *device, int state)
|
||||
{
|
||||
}
|
||||
|
||||
void viper_state::machine_start()
|
||||
{
|
||||
ds2430_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(viper_state::ds2430_timer_callback),this));
|
||||
@ -2017,10 +2013,12 @@ void viper_state::machine_start()
|
||||
|
||||
void viper_state::machine_reset()
|
||||
{
|
||||
machine().device("ide")->reset();
|
||||
ide_controller_device *ide = (ide_controller_device *) machine().device("ide");
|
||||
|
||||
ide->reset();
|
||||
mpc8240_epic_reset();
|
||||
|
||||
UINT8 *ide_features = ide_get_features(machine().device("ide"), 0);
|
||||
UINT8 *ide_features = ide->ide_get_features(0);
|
||||
|
||||
// Viper expects these settings or the BIOS fails
|
||||
ide_features[51*2+0] = 0; /* 51: PIO data transfer cycle timing mode */
|
||||
@ -2029,13 +2027,6 @@ void viper_state::machine_reset()
|
||||
ide_features[67*2+1] = 0x00;
|
||||
}
|
||||
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
ide_interrupt,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
|
||||
static const voodoo_config voodoo_intf =
|
||||
{
|
||||
8, // fbmem;
|
||||
@ -2060,7 +2051,8 @@ static MACHINE_CONFIG_START( viper, viper_state )
|
||||
MCFG_PCI_BUS_LEGACY_DEVICE(0, "mpc8240", mpc8240_pci_r, mpc8240_pci_w)
|
||||
MCFG_PCI_BUS_LEGACY_DEVICE(12, "voodoo", voodoo3_pci_r, voodoo3_pci_w)
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
|
||||
|
||||
MCFG_3DFX_VOODOO_3_ADD("voodoo", STD_VOODOO_3_CLOCK, voodoo_intf)
|
||||
|
||||
/* video hardware */
|
||||
|
||||
@ -65,6 +65,7 @@ public:
|
||||
DECLARE_READ32_MEMBER(fdc_r);
|
||||
DECLARE_WRITE32_MEMBER(fdc_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(voyager_pic8259_1_set_int_line);
|
||||
DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
|
||||
DECLARE_READ8_MEMBER(get_slave_ack);
|
||||
DECLARE_DRIVER_INIT(voyager);
|
||||
virtual void machine_start();
|
||||
@ -72,9 +73,6 @@ public:
|
||||
};
|
||||
|
||||
|
||||
static void ide_interrupt(device_t *device, int state);
|
||||
|
||||
|
||||
READ8_MEMBER(voyager_state::at_dma8237_2_r)
|
||||
{
|
||||
device_t *device = machine().device("dma8237_2");
|
||||
@ -742,10 +740,9 @@ static void keyboard_interrupt(running_machine &machine, int state)
|
||||
pic8259_ir1_w(drvstate->m_pic8259_1, state);
|
||||
}
|
||||
|
||||
static void ide_interrupt(device_t *device, int state)
|
||||
WRITE_LINE_MEMBER(voyager_state::ide_interrupt)
|
||||
{
|
||||
voyager_state *drvstate = device->machine().driver_data<voyager_state>();
|
||||
pic8259_ir6_w(drvstate->m_pic8259_2, state);
|
||||
pic8259_ir6_w(m_pic8259_2, state);
|
||||
}
|
||||
|
||||
static int voyager_get_out2(running_machine &machine)
|
||||
@ -765,13 +762,6 @@ static void voyager_set_keyb_int(running_machine &machine, int state)
|
||||
pic8259_ir1_w(drvstate->m_pic8259_1, state);
|
||||
}
|
||||
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
ide_interrupt,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
|
||||
static MACHINE_CONFIG_START( voyager, voyager_state )
|
||||
MCFG_CPU_ADD("maincpu", PENTIUM, 133000000) // actually AMD Duron CPU of unknown clock
|
||||
MCFG_CPU_PROGRAM_MAP(voyager_map)
|
||||
@ -783,7 +773,8 @@ static MACHINE_CONFIG_START( voyager, voyager_state )
|
||||
MCFG_I8237_ADD( "dma8237_2", XTAL_14_31818MHz/3, dma8237_2_config )
|
||||
MCFG_PIC8259_ADD( "pic8259_1", voyager_pic8259_1_config )
|
||||
MCFG_PIC8259_ADD( "pic8259_2", voyager_pic8259_2_config )
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, voyager_state, ide_interrupt))
|
||||
|
||||
MCFG_MC146818_ADD( "rtc", MC146818_STANDARD )
|
||||
MCFG_PCI_BUS_LEGACY_ADD("pcibus", 0)
|
||||
|
||||
@ -113,6 +113,7 @@ public:
|
||||
DECLARE_WRITE_LINE_MEMBER(pc_dack2_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(pc_dack3_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(xtom3d_pic8259_1_set_int_line);
|
||||
DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
|
||||
virtual void machine_start();
|
||||
virtual void machine_reset();
|
||||
};
|
||||
@ -641,10 +642,9 @@ static IRQ_CALLBACK(irq_callback)
|
||||
return pic8259_acknowledge( state->m_pic8259_1);
|
||||
}
|
||||
|
||||
static void ide_interrupt(device_t *device, int state)
|
||||
WRITE_LINE_MEMBER(xtom3d_state::ide_interrupt)
|
||||
{
|
||||
xtom3d_state *drvstate = device->machine().driver_data<xtom3d_state>();
|
||||
pic8259_ir6_w(drvstate->m_pic8259_2, state);
|
||||
pic8259_ir6_w(m_pic8259_2, state);
|
||||
}
|
||||
|
||||
void xtom3d_state::machine_start()
|
||||
@ -677,13 +677,6 @@ void xtom3d_state::machine_reset()
|
||||
machine().root_device().membank("video_bank2")->set_base(machine().root_device().memregion("video_bios")->base() + 0x4000);
|
||||
}
|
||||
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
ide_interrupt,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
|
||||
static MACHINE_CONFIG_START( xtom3d, xtom3d_state )
|
||||
MCFG_CPU_ADD("maincpu", PENTIUM, 450000000/16) // actually Pentium II 450
|
||||
MCFG_CPU_PROGRAM_MAP(xtom3d_map)
|
||||
@ -702,7 +695,8 @@ static MACHINE_CONFIG_START( xtom3d, xtom3d_state )
|
||||
MCFG_PCI_BUS_LEGACY_DEVICE(0, NULL, intel82439tx_pci_r, intel82439tx_pci_w)
|
||||
MCFG_PCI_BUS_LEGACY_DEVICE(7, NULL, intel82371ab_pci_r, intel82371ab_pci_w)
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, xtom3d_state, ide_interrupt))
|
||||
|
||||
/* video hardware */
|
||||
MCFG_FRAGMENT_ADD( pcvideo_vga )
|
||||
|
||||
@ -1471,15 +1471,6 @@ Notes:
|
||||
*2 - Unpopulated DIP28 socket
|
||||
*/
|
||||
|
||||
static void atpsx_interrupt(device_t *device, int state)
|
||||
{
|
||||
if (state)
|
||||
{
|
||||
psxirq_device *psxirq = (psxirq_device *) device->machine().device("maincpu:irq");
|
||||
psxirq->intin10(1);
|
||||
}
|
||||
}
|
||||
|
||||
static void atpsx_dma_read( zn_state *state, UINT32 n_address, INT32 n_size )
|
||||
{
|
||||
UINT32 *p_n_psxram = state->m_p_n_psxram;
|
||||
@ -1531,17 +1522,11 @@ MACHINE_RESET_MEMBER(zn_state,coh1000w)
|
||||
machine().device("ide")->reset();
|
||||
}
|
||||
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
atpsx_interrupt,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
|
||||
static MACHINE_CONFIG_DERIVED( coh1000w, zn1_2mb_vram )
|
||||
MCFG_MACHINE_RESET_OVERRIDE(zn_state, coh1000w )
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("maincpu:irq", psxirq_device, intin10))
|
||||
MCFG_PSX_DMA_CHANNEL_READ( "maincpu", 5, psx_dma_read_delegate( FUNC( atpsx_dma_read ), (zn_state *) owner ) )
|
||||
MCFG_PSX_DMA_CHANNEL_WRITE( "maincpu", 5, psx_dma_write_delegate( FUNC( atpsx_dma_write ), (zn_state *) owner ) )
|
||||
MACHINE_CONFIG_END
|
||||
@ -2043,15 +2028,6 @@ Notes:
|
||||
* - Unpopulated DIP42 socket
|
||||
*/
|
||||
|
||||
static void jdredd_ide_interrupt(device_t *device, int state)
|
||||
{
|
||||
if (state)
|
||||
{
|
||||
psxirq_device *psxirq = (psxirq_device *) device->machine().device("maincpu:irq");
|
||||
psxirq->intin10(1);
|
||||
}
|
||||
}
|
||||
|
||||
READ32_MEMBER(zn_state::jdredd_idestat_r)
|
||||
{
|
||||
device_t *device = machine().device("ide");
|
||||
@ -2214,13 +2190,6 @@ static MACHINE_CONFIG_DERIVED( coh1000a, zn1_2mb_vram )
|
||||
MCFG_MACHINE_RESET_OVERRIDE(zn_state, coh1000a )
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
static const ide_config jdredd_ide_intf =
|
||||
{
|
||||
jdredd_ide_interrupt,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
|
||||
static MACHINE_CONFIG_DERIVED( coh1000a_ide, zn1_2mb_vram )
|
||||
|
||||
MCFG_DEVICE_MODIFY( "gpu" )
|
||||
@ -2228,7 +2197,8 @@ static MACHINE_CONFIG_DERIVED( coh1000a_ide, zn1_2mb_vram )
|
||||
|
||||
MCFG_MACHINE_RESET_OVERRIDE(zn_state, coh1000a )
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", jdredd_ide_intf, ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("maincpu:irq", psxirq_device, intin10))
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
/*
|
||||
|
||||
@ -55,6 +55,7 @@ public:
|
||||
virtual void video_start();
|
||||
UINT32 screen_update_djmain(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
|
||||
INTERRUPT_GEN_MEMBER(vb_interrupt);
|
||||
DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
|
||||
};
|
||||
|
||||
/*----------- defined in video/djmain.c -----------*/
|
||||
|
||||
@ -209,7 +209,7 @@ public:
|
||||
|
||||
static void gpu_cpu_int(device_t *device);
|
||||
static void dsp_cpu_int(device_t *device);
|
||||
static void external_int(device_t *device, int state);
|
||||
DECLARE_WRITE_LINE_MEMBER( external_int );
|
||||
|
||||
int quickload(device_image_interface &image, const char *file_type, int quickload_size);
|
||||
void cart_start();
|
||||
|
||||
@ -42,6 +42,8 @@ public:
|
||||
INTERRUPT_GEN_MEMBER(qdrmfgp2_interrupt);
|
||||
TIMER_CALLBACK_MEMBER(gp2_timer_callback);
|
||||
TIMER_DEVICE_CALLBACK_MEMBER(qdrmfgp_interrupt);
|
||||
DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
|
||||
DECLARE_WRITE_LINE_MEMBER(gp2_ide_interrupt);
|
||||
};
|
||||
|
||||
/*----------- defined in video/qdrmfgp.c -----------*/
|
||||
|
||||
@ -152,13 +152,6 @@ static SLOT_INTERFACE_START( pci_devices )
|
||||
SLOT_INTERFACE("cirrus", CIRRUS)
|
||||
SLOT_INTERFACE_END
|
||||
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
bebox_ide_interrupt,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
|
||||
static MACHINE_CONFIG_START( bebox, bebox_state )
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD("ppc1", PPC603, 66000000) /* 66 MHz */
|
||||
@ -199,7 +192,8 @@ static MACHINE_CONFIG_START( bebox, bebox_state )
|
||||
MCFG_SCSIDEV_ADD("scsi:cdrom", SCSICD, SCSI_ID_3)
|
||||
MCFG_LSI53C810_ADD( "scsi:lsi53c810", lsi53c810_intf)
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD( "ide", ide_intf, ide_image_devices, "hdd", NULL, false ) /* FIXME */
|
||||
MCFG_IDE_CONTROLLER_ADD( "ide", ide_image_devices, "hdd", NULL, false ) /* FIXME */
|
||||
MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, bebox_state, bebox_ide_interrupt))
|
||||
|
||||
/* pci */
|
||||
MCFG_PCI_BUS_ADD("pcibus", 0)
|
||||
|
||||
@ -82,6 +82,8 @@ public:
|
||||
DECLARE_WRITE64_MEMBER(scsi53c810_w);
|
||||
DECLARE_READ64_MEMBER(bb_slave_64be_r);
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER(bebox_ide_interrupt);
|
||||
|
||||
void fdc_interrupt(bool state);
|
||||
void fdc_dma_drq(bool state);
|
||||
};
|
||||
@ -99,7 +101,6 @@ extern const ins8250_interface bebox_uart_inteface_1;
|
||||
extern const ins8250_interface bebox_uart_inteface_2;
|
||||
extern const ins8250_interface bebox_uart_inteface_3;
|
||||
|
||||
void bebox_ide_interrupt(device_t *device, int state);
|
||||
void bebox_set_irq_bit(running_machine &machine, unsigned int interrupt_bit, int val);
|
||||
|
||||
UINT32 scsi53c810_pci_read(device_t *busdevice, device_t *device, int function, int offset, UINT32 mem_mask);
|
||||
|
||||
@ -31,15 +31,8 @@ const device_type A2BUS_CFFA2_6502 = &device_creator<a2bus_cffa2_6502_device>;
|
||||
#define CFFA2_ROM_REGION "cffa2_rom"
|
||||
#define CFFA2_IDE_TAG "cffa2_ide"
|
||||
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
NULL,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
|
||||
MACHINE_CONFIG_FRAGMENT( cffa2 )
|
||||
MCFG_IDE_CONTROLLER_ADD(CFFA2_IDE_TAG, ide_intf, ide_image_devices, "hdd", "hdd", false)
|
||||
MCFG_IDE_CONTROLLER_ADD(CFFA2_IDE_TAG, ide_image_devices, "hdd", "hdd", false)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
ROM_START( cffa2 )
|
||||
|
||||
@ -555,12 +555,11 @@ WRITE64_MEMBER(bebox_state::bebox_800003F0_w )
|
||||
}
|
||||
|
||||
|
||||
void bebox_ide_interrupt(device_t *device, int state)
|
||||
WRITE_LINE_MEMBER(bebox_state::bebox_ide_interrupt)
|
||||
{
|
||||
bebox_state *drvstate = device->machine().driver_data<bebox_state>();
|
||||
bebox_set_irq_bit(device->machine(), 7, state);
|
||||
if ( drvstate->m_devices.pic8259_master ) {
|
||||
pic8259_ir6_w(drvstate->m_devices.pic8259_master, state);
|
||||
bebox_set_irq_bit(machine(), 7, state);
|
||||
if ( m_devices.pic8259_master ) {
|
||||
pic8259_ir6_w(m_devices.pic8259_master, state);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -45,18 +45,11 @@ const device_type C64_IDE64 = &device_creator<c64_ide64_cartridge_device>;
|
||||
//-------------------------------------------------
|
||||
// MACHINE_CONFIG_FRAGMENT( c64_ide64 )
|
||||
//-------------------------------------------------
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
NULL,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
|
||||
static MACHINE_CONFIG_FRAGMENT( c64_ide64 )
|
||||
MCFG_ATMEL_29C010_ADD(AT29C010A_TAG)
|
||||
MCFG_DS1302_ADD(DS1302_TAG, XTAL_32_768kHz)
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD(IDE_TAG, ide_intf, ide_image_devices, "hdd", "hdd", false)
|
||||
MCFG_IDE_CONTROLLER_ADD(IDE_TAG, ide_image_devices, "hdd", "hdd", false)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
|
||||
|
||||
@ -30,25 +30,21 @@ static WRITE16_DEVICE_HANDLER( ide16_alt_w )
|
||||
ide_controller16_w(device, space, 0x3f6/2 + offset, data, 0x00ff);
|
||||
}
|
||||
|
||||
static void ide_interrupt(device_t *device, int state)
|
||||
WRITE_LINE_MEMBER(isa16_ide_device::ide_interrupt)
|
||||
{
|
||||
isa16_ide_device *ide = downcast<isa16_ide_device *>(device->owner());
|
||||
if (ide->is_primary()) {
|
||||
ide->m_isa->irq14_w(state);
|
||||
} else {
|
||||
ide->m_isa->irq15_w(state);
|
||||
if (is_primary())
|
||||
{
|
||||
m_isa->irq14_w(state);
|
||||
}
|
||||
else
|
||||
{
|
||||
m_isa->irq15_w(state);
|
||||
}
|
||||
}
|
||||
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
ide_interrupt,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
|
||||
static MACHINE_CONFIG_FRAGMENT( ide )
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_image_devices, "hdd", "hdd", false)
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_image_devices, "hdd", "hdd", false)
|
||||
MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, isa16_ide_device, ide_interrupt))
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
static INPUT_PORTS_START( ide )
|
||||
|
||||
@ -12,27 +12,29 @@
|
||||
|
||||
// ======================> isa16_ide_device
|
||||
|
||||
class isa16_ide_device :
|
||||
public device_t,
|
||||
public device_isa16_card_interface
|
||||
class isa16_ide_device : public device_t,
|
||||
public device_isa16_card_interface
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
isa16_ide_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
// construction/destruction
|
||||
isa16_ide_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
// optional information overrides
|
||||
virtual machine_config_constructor device_mconfig_additions() const;
|
||||
virtual ioport_constructor device_input_ports() const;
|
||||
// optional information overrides
|
||||
virtual machine_config_constructor device_mconfig_additions() const;
|
||||
virtual ioport_constructor device_input_ports() const;
|
||||
|
||||
bool is_primary() { return m_is_primary; }
|
||||
DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
|
||||
|
||||
bool is_primary() { return m_is_primary; }
|
||||
protected:
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_reset();
|
||||
virtual void device_config_complete() { m_shortname = "isa_ide"; }
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_reset();
|
||||
virtual void device_config_complete() { m_shortname = "isa_ide"; }
|
||||
|
||||
private:
|
||||
// internal state
|
||||
bool m_is_primary;
|
||||
// internal state
|
||||
bool m_is_primary;
|
||||
};
|
||||
|
||||
|
||||
|
||||
@ -86,20 +86,13 @@ static MACHINE_CONFIG_FRAGMENT(kc_d004)
|
||||
MCFG_FLOPPY_DRIVE_ADD(UPD765_TAG ":3", kc_d004_floppies, "525hd", 0, kc_d004_floppy_formats)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
NULL,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
|
||||
static MACHINE_CONFIG_FRAGMENT(kc_d004_gide)
|
||||
MCFG_FRAGMENT_ADD(kc_d004)
|
||||
|
||||
MCFG_CPU_MODIFY(Z80_TAG)
|
||||
MCFG_CPU_IO_MAP(kc_d004_gide_io)
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD(IDE_TAG, ide_intf, ide_image_devices, "hdd", "hdd", false)
|
||||
MCFG_IDE_CONTROLLER_ADD(IDE_TAG, ide_image_devices, "hdd", "hdd", false)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
|
||||
|
||||
@ -278,12 +278,11 @@ void nouspikel_ide_interface_device::do_inta(int state)
|
||||
ti99_ide_interrupt()
|
||||
IDE interrupt callback
|
||||
*/
|
||||
static void ide_interrupt_callback(device_t *device, int state)
|
||||
WRITE_LINE_MEMBER(nouspikel_ide_interface_device::ide_interrupt_callback)
|
||||
{
|
||||
nouspikel_ide_interface_device *card = downcast<nouspikel_ide_interface_device *>(device->owner());
|
||||
card->m_ide_irq = state;
|
||||
if (card->m_cru_register & cru_reg_int_en)
|
||||
card->do_inta(state);
|
||||
m_ide_irq = state;
|
||||
if (m_cru_register & cru_reg_int_en)
|
||||
do_inta(state);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -334,16 +333,10 @@ static const rtc65271_interface ide_rtc_cfg =
|
||||
DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, nouspikel_ide_interface_device, clock_interrupt_callback)
|
||||
};
|
||||
|
||||
static const ide_config ide_intf =
|
||||
{
|
||||
ide_interrupt_callback,
|
||||
NULL,
|
||||
0
|
||||
};
|
||||
|
||||
MACHINE_CONFIG_FRAGMENT( tn_ide )
|
||||
MCFG_RTC65271_ADD( "ide_rtc", ide_rtc_cfg )
|
||||
MCFG_IDE_CONTROLLER_ADD( "ide", ide_intf, ide_image_devices, "hdd", NULL, false) // see idectrl.c
|
||||
MCFG_IDE_CONTROLLER_ADD( "ide", ide_image_devices, "hdd", NULL, false) // see idectrl.c
|
||||
MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, nouspikel_ide_interface_device, ide_interrupt_callback))
|
||||
// MCFG_IDE_CONTROLLER_REGIONS(":peribox:idehd0:drive", NULL)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
|
||||
@ -33,6 +33,7 @@ public:
|
||||
int m_cru_register;
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER(clock_interrupt_callback);
|
||||
DECLARE_WRITE_LINE_MEMBER(ide_interrupt_callback);
|
||||
|
||||
protected:
|
||||
void device_start(void);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user