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https://github.com/holub/mame
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sun4c: Added support for full-width mem_mask on segment map writes, gets Aurora SPARC Linux to 'Booting Linux...' before it dies. [Ryan Holtz]
This commit is contained in:
mooglyguy
parent
064401bf00
commit
02f25921e8
@ -989,6 +989,7 @@ void hle_device_base::received_byte(uint8_t byte)
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switch (byte)
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{
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case COMMAND_RESET:
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printf("Resetting keyboard\n");
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device_reset();
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break;
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@ -12,6 +12,25 @@
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DEFINE_DEVICE_TYPE(SUN4C_MMU, sun4c_mmu_device, "sun4c_mmu", "Sun 4C MMU")
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#define LOG_PAGE_MAP (1U << 0)
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#define LOG_SEGMENT_MAP (1U << 1)
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#define LOG_INVALID_PTE (1U << 2)
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#define LOG_SYSTEM (1U << 3)
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#define LOG_CONTEXT (1U << 4)
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#define LOG_SYSTEM_ENABLE (1U << 5)
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#define LOG_BUSERROR (1U << 6)
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#define LOG_CACHE_TAGS (1U << 7)
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#define LOG_CACHE_DATA (1U << 8)
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#define LOG_UNKNOWN_SYSTEM (1U << 9)
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#define LOG_UNKNOWN_SEGMENT (1U << 10)
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#define LOG_TYPE0_TIMEOUT (1U << 11)
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#define LOG_UNKNOWN_SPACE (1U << 12)
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#define LOG_WRITE_PROTECT (1U << 13)
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#define LOG_ALL_ASI (1U << 14) // WARNING: Heavy!
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#define VERBOSE (0)
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#include "logmacro.h"
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sun4c_mmu_device::sun4c_mmu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: device_t(mconfig, SUN4C_MMU, tag, owner, clock)
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, m_cpu(*this, finder_base::DUMMY_TAG)
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@ -128,7 +147,6 @@ void sun4c_mmu_device::device_timer(emu_timer &timer, device_timer_id id, int pa
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{
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m_reset_timer->adjust(attotime::never);
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m_cpu->set_input_line(SPARC_RESET, CLEAR_LINE);
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//printf("Clearing reset line\n");
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}
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}
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@ -142,7 +160,7 @@ uint32_t sun4c_mmu_device::fetch_insn(const bool supervisor, const uint32_t offs
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uint32_t sun4c_mmu_device::read_asi(uint8_t asi, uint32_t offset, uint32_t mem_mask)
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{
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//logerror("read_asi %d: %08x & %08x\n", asi, offset << 2, mem_mask);
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LOGMASKED(LOG_ALL_ASI, "read_asi %d: %08x & %08x\n", asi, offset << 2, mem_mask);
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switch (asi)
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{
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case 2:
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@ -171,7 +189,7 @@ uint32_t sun4c_mmu_device::read_asi(uint8_t asi, uint32_t offset, uint32_t mem_m
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void sun4c_mmu_device::write_asi(uint8_t asi, uint32_t offset, uint32_t data, uint32_t mem_mask)
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{
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//logerror("write_asi %d: %08x = %08x & %08x\n", asi, offset << 2, data, mem_mask);
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LOGMASKED(LOG_ALL_ASI, "write_asi %d: %08x = %08x & %08x\n", asi, offset << 2, data, mem_mask);
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switch (asi)
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{
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case 2:
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@ -218,34 +236,41 @@ void sun4c_mmu_device::cache_flush_w()
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uint32_t sun4c_mmu_device::system_r(const uint32_t offset, const uint32_t mem_mask)
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{
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//logerror("%s: system_r: %08x & %08x\n", machine().describe_context(), offset << 2, mem_mask);
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LOGMASKED(LOG_SYSTEM, "%s: system_r: %08x & %08x\n", machine().describe_context(), offset << 2, mem_mask);
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switch (offset >> 26)
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{
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case 3: // context reg
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if (mem_mask == 0x00ff0000) return m_context<<16;
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{
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if (mem_mask == 0x00ff0000)
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{
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LOGMASKED(LOG_CONTEXT, "sun4c_mmu: read context %08x & %08x = %08x\n", offset << 2, mem_mask, m_context<<16);
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return m_context<<16;
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}
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LOGMASKED(LOG_CONTEXT, "sun4c_mmu: read context %08x & %08x = %08x\n", offset << 2, mem_mask, m_context<<24);
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return m_context<<24;
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}
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case 4: // system enable reg
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LOGMASKED(LOG_SYSTEM_ENABLE, "sun4c_mmu: read system enable %08x & %08x = %08x\n", offset << 2, mem_mask, m_system_enable<<24);
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return m_system_enable<<24;
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case 6: // bus error register
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{
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const uint32_t retval = m_buserr[offset & 0xf];
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//logerror("sun4c_mmu: read buserror %08x & %08x = %08x, PC=%x\n", 0x60000000 | (offset << 2), mem_mask, retval, m_cpu->pc());
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const uint32_t ret = m_buserr[offset & 0xf];
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LOGMASKED(LOG_BUSERROR, "sun4c_mmu: read buserror %08x & %08x = %08x, PC=%x\n", 0x60000000 | (offset << 2), mem_mask, ret, m_cpu->pc());
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m_buserr[offset & 0xf] = 0; // clear on reading
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return retval;
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return ret;
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}
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case 8: // (d-)cache tags
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//logerror("sun4_mmu: read dcache tags @ %x, PC = %x\n", offset, m_cpu->pc());
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LOGMASKED(LOG_CACHE_TAGS, "sun4_mmu: read dcache tags @ %x, PC = %x\n", offset, m_cpu->pc());
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return m_cachetags[offset & 0x3fff];
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case 9: // (d-)cache data
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//logerror("sun4c_mmu: read dcache data @ %x, PC = %x\n", offset, m_cpu->pc());
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LOGMASKED(LOG_CACHE_DATA, "sun4c_mmu: read dcache data @ %x, PC = %x\n", offset, m_cpu->pc());
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return m_cachedata[offset & 0x3fff];
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case 0xf: // UART bypass
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//printf("sun4c_mmu: read UART bypass @ %x mask %08x\n", offset<<2, mem_mask);
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switch (offset & 3)
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{
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case 0: if (mem_mask == 0xff000000) return m_scc->cb_r(0)<<24; else return m_scc->db_r(0)<<8; break;
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@ -255,18 +280,18 @@ uint32_t sun4c_mmu_device::system_r(const uint32_t offset, const uint32_t mem_ma
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case 0: // IDPROM - SPARCstation-1 does not have an ID prom and a timeout should occur.
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default:
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//logerror("%s: sun4c_mmu: ASI 2 space unhandled read @ %x\n", machine().describe_context(), offset<<2);
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LOGMASKED(LOG_UNKNOWN_SYSTEM, "read unhandled ASI 2 space %08x & %08x\n", offset << 2, mem_mask);
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return 0;
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}
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}
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void sun4c_mmu_device::system_w(const uint32_t offset, const uint32_t data, const uint32_t mem_mask)
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{
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//logerror("%s: system_w: %08x = %08x & %08x\n", machine().describe_context(), offset << 2, data, mem_mask);
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LOGMASKED(LOG_SYSTEM, "system_w: %08x = %08x & %08x\n", offset << 2, data, mem_mask);
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switch (offset >> 26)
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{
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case 3: // context reg
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//printf("%08x to context, mask %08x, offset %x\n", data, mem_mask, offset);
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LOGMASKED(LOG_CONTEXT, "write context = %08x & %08x\n", data, mem_mask);
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m_context = data >> 24;
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m_context_masked = m_context & m_ctx_mask;
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m_cache_context = m_context & m_ctx_mask;
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@ -276,6 +301,7 @@ void sun4c_mmu_device::system_w(const uint32_t offset, const uint32_t data, cons
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case 4: // system enable reg
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{
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LOGMASKED(LOG_SYSTEM_ENABLE, "write system enable = %08x & %08x\n", data, mem_mask);
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m_system_enable = data >> 24;
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m_fetch_bootrom = !(m_system_enable & ENA_NOTBOOT);
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@ -283,9 +309,7 @@ void sun4c_mmu_device::system_w(const uint32_t offset, const uint32_t data, cons
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{
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m_reset_timer->adjust(attotime::from_usec(1));
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m_cpu->set_input_line(SPARC_RESET, ASSERT_LINE);
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//logerror("%s: Asserting reset line\n", machine().describe_context());
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}
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//printf("%08x to system enable, mask %08x\n", data, mem_mask);
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if (m_system_enable & ENA_RESET)
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{
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m_system_enable = 0;
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@ -298,7 +322,7 @@ void sun4c_mmu_device::system_w(const uint32_t offset, const uint32_t data, cons
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case 6: // bus error
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{
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const uint32_t masked_offset = offset & 0xf;
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//logerror("%08x to bus error @ %x, mask %08x\n", data, offset << 2, mem_mask);
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LOGMASKED(LOG_BUSERROR, "write bus error %08x = %08x & %08x\n", offset << 2, data, mem_mask);
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if (masked_offset == 0)
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m_buserr[0] = (data & 0x000000ff) | 0x00008000;
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else if (masked_offset == 1)
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@ -311,17 +335,16 @@ void sun4c_mmu_device::system_w(const uint32_t offset, const uint32_t data, cons
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}
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case 8: // cache tags
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//logerror("sun4: %08x to cache tags @ %x, PC = %x\n", data, offset, m_cpu->pc());
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LOGMASKED(LOG_CACHE_TAGS, "write cache tags %08x = %08x & %08x\n", offset << 2, data, mem_mask);
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m_cachetags[offset&0x3fff] = data & 0x03f8fffc;
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return;
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case 9: // cache data
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//logerror("sun4c: %08x to cache data @ %x, PC = %x\n", data, offset, m_cpu->pc());
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LOGMASKED(LOG_CACHE_DATA, "write cache data %08x = %08x & %08x\n", offset << 2, data, mem_mask);
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m_cachedata[offset&0x3fff] = data | (1 << 19);
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return;
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case 0xf: // UART bypass
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logerror("%08x to UART bypass @ %x, mask %08x\n", data, offset<<2, mem_mask);
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switch (offset & 3)
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{
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case 0: if (mem_mask == 0xff000000) m_scc->cb_w(0, data>>24); else m_scc->db_w(0, data>>8); break;
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@ -331,31 +354,35 @@ void sun4c_mmu_device::system_w(const uint32_t offset, const uint32_t data, cons
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case 0: // IDPROM
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default:
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//logerror("sun4c: ASI 2 space unhandled write %x @ %x (mask %08x, PC=%x, shift %x)\n", data, offset<<2, mem_mask, m_cpu->pc(), offset>>26);
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LOGMASKED(LOG_UNKNOWN_SYSTEM, "write unhandled ASI 2 space %08x = %08x & %08x, PC=%08x\n", offset << 2, data, mem_mask, m_cpu->pc());
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return;
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}
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}
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uint32_t sun4c_mmu_device::segment_map_r(const uint32_t offset, const uint32_t mem_mask)
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{
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//logerror("%s: segment_map_r: %08x & %08x\n", machine().describe_context(), offset << 2, mem_mask);
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uint32_t ret = 0;
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if (mem_mask == 0xffff0000)
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return m_curr_segmap[(offset>>16) & 0xfff]<<16;
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ret = m_curr_segmap[(offset>>16) & 0xfff]<<16;
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else if (mem_mask == 0xff000000)
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return m_curr_segmap[(offset>>16) & 0xfff]<<24;
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ret = m_curr_segmap[(offset>>16) & 0xfff]<<24;
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else if (mem_mask == 0xffffffff)
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ret = m_curr_segmap[(offset>>16) & 0xfff];
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else
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logerror("sun4: read segment map w/ unknown mask %08x\n", mem_mask);
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return 0;
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LOGMASKED(LOG_UNKNOWN_SEGMENT, "read segment map w/ unknown mask %08x & %08x\n", offset << 2, mem_mask);
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LOGMASKED(LOG_SEGMENT_MAP, "read segment map %08x & %08x = %08x\n", offset << 2, mem_mask, ret);
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return ret;
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}
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void sun4c_mmu_device::segment_map_w(const uint32_t offset, const uint32_t data, const uint32_t mem_mask)
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{
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//logerror("segment_map_w: %08x = %08x & %08x\n", machine().describe_context(), offset << 2, data, mem_mask);
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LOGMASKED(LOG_SEGMENT_MAP, "write segment map %08x = %08x & %08x\n", offset << 2, data, mem_mask);
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uint8_t segdata = 0;
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if (mem_mask == 0xffff0000) segdata = (data >> 16) & 0xff;
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else if (mem_mask == 0xff000000) segdata = (data >> 24) & 0xff;
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else logerror("sun4c: writing segment map with unknown mask %08x, PC=%x\n", mem_mask, m_cpu->pc());
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else if (mem_mask == 0xffffffff) segdata = data & 0xff;
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else LOGMASKED(LOG_UNKNOWN_SEGMENT, "write segment map w/ unknown mask %08x = %08x & %08x, PC=%08x\n", offset << 2, data, mem_mask, m_cpu->pc());
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const uint32_t seg = (offset>>16) & 0xfff;
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m_curr_segmap[seg] = segdata;
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@ -365,21 +392,22 @@ void sun4c_mmu_device::segment_map_w(const uint32_t offset, const uint32_t data,
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uint32_t sun4c_mmu_device::page_map_r(const uint32_t offset, const uint32_t mem_mask)
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{
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const uint32_t page = m_curr_segmap_masked[(offset >> 16) & 0xfff] | ((offset >> 10) & 0x3f);
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const uint32_t retval = m_pagemap[page].to_uint();
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logerror("%s: page_map_r: %08x (%x, %x) & %08x = %08x\n", machine().describe_context(), offset << 2, page, (m_curr_segmap[(offset >> 16) & 0xfff] << 6) | ((offset >> 10) & 0x3f), mem_mask, retval);
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return retval;
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const uint32_t ret = m_pagemap[page].to_uint();
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LOGMASKED(LOG_PAGE_MAP, "read page map %08x & %08x (%x) = %08x\n", offset << 2, mem_mask, page, ret);
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return ret;
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}
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void sun4c_mmu_device::page_map_w(const uint32_t offset, const uint32_t data, const uint32_t mem_mask)
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{
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uint32_t page = m_curr_segmap_masked[(offset >> 16) & 0xfff] | ((offset >> 10) & 0x3f);
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logerror("%s: page_map_w: %08x (%x, %x) = %08x & %08x\n", machine().describe_context(), offset << 2, page, (m_curr_segmap[(offset >> 16) & 0xfff] << 6) | ((offset >> 10) & 0x3f), data, mem_mask);
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LOGMASKED(LOG_PAGE_MAP, "write page map %08x (%x) = %08x & %08x\n", offset << 2, page, data, mem_mask);
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m_pagemap[page].merge_uint(data, mem_mask);
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m_page_valid[page] = m_pagemap[page].valid;
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}
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void sun4c_mmu_device::type0_timeout_r(const uint32_t offset)
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{
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LOGMASKED(LOG_TYPE0_TIMEOUT, "type 0 read timeout %08x, PC=%08x\n", offset << 2, m_cpu->pc());
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m_buserr[0] = 0x20; // read timeout
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m_buserr[1] = 0x04000000 + (offset << 2);
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m_host->set_mae();
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@ -387,6 +415,7 @@ void sun4c_mmu_device::type0_timeout_r(const uint32_t offset)
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void sun4c_mmu_device::type0_timeout_w(const uint32_t offset)
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{
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LOGMASKED(LOG_TYPE0_TIMEOUT, "type 0 write timeout %08x, PC=%08x\n", offset << 2, m_cpu->pc());
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m_buserr[0] = 0x8020; // write timeout
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m_buserr[1] = 0x04000000 + (offset << 2);
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m_host->set_mae();
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@ -435,18 +464,14 @@ uint32_t sun4c_mmu_device::insn_data_r(const uint32_t offset, const uint32_t mem
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const uint32_t tmp = entry.page | (offset & 0x3ff);
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//printf("sun4c: read translated vaddr %08x to phys %08x type %d, PTE %08x, PC=%x\n", offset<<2, tmp<<2, entry.type, entry.to_uint(), m_cpu->pc());
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switch (entry.type)
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{
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case 0: // type 0 space
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//return m_type0space->read32(space, tmp, mem_mask);
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if (tmp < m_populated_ram_words)
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{
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const uint32_t set = (tmp >> 22) & 3;
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const uint32_t addr_mask = m_ram_set_mask[set];
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const uint32_t masked_addr = m_ram_set_base[set] + (tmp & addr_mask);
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//printf("mask %08x, masked %08x\n", addr_mask, masked_addr);
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return m_ram_ptr[masked_addr];
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}
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else if (tmp >= 0x4000000 >> 2 && tmp < 0x10000000 >> 2)
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@ -459,7 +484,7 @@ uint32_t sun4c_mmu_device::insn_data_r(const uint32_t offset, const uint32_t mem
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return m_type1_r(tmp, mem_mask);
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default:
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//logerror("sun4c_mmu: read from to memory type not defined in sun4c, %d, %08x & %08x\n", entry.type, tmp << 2, mem_mask);
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LOGMASKED(LOG_UNKNOWN_SPACE, "read unknown space type %d, %08x & %08x, PC=%08x\n", entry.type, tmp << 2, mem_mask, m_cpu->pc());
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m_host->set_mae();
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m_buserr[0] = 0x20;
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m_buserr[1] = offset << 2;
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@ -470,7 +495,7 @@ uint32_t sun4c_mmu_device::insn_data_r(const uint32_t offset, const uint32_t mem
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{
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if (!machine().side_effects_disabled())
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{
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//logerror("sun4c: INVALID PTE entry %d %08x read! vaddr=%x PC=%x\n", entry_index, m_pagemap[entry_index].to_uint(), offset << 2, m_cpu->pc());
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LOGMASKED(LOG_INVALID_PTE, "read invalid PTE %d (%08x), %08x & %08x, PC=%08x\n", entry_index, m_pagemap[entry_index].to_uint(), offset << 2, mem_mask, m_cpu->pc());
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m_host->set_mae();
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m_buserr[0] |= 0x80; // invalid PTE
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m_buserr[0] &= ~0x8000; // read
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@ -512,7 +537,7 @@ void sun4c_mmu_device::insn_data_w(const uint32_t offset, const uint32_t data, c
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page_entry_t &entry = m_pagemap[entry_index];
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if ((!entry.writable) || (entry.supervisor && MODE != SUPER_DATA && MODE != SUPER_INSN))
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{
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//logerror("sun4c: write protect MMU error (PC=%x)\n", m_cpu->pc());
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LOGMASKED(LOG_WRITE_PROTECT, "write protect error with PTE %d (%08x), %08x = %08x & %08x, PC=%08x\n", entry_index, m_pagemap[entry_index].to_uint(), offset << 2, data, mem_mask, m_cpu->pc());
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m_buserr[0] |= 0x8040; // write, protection error
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m_buserr[1] = offset << 2;
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m_host->set_mae();
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@ -524,8 +549,6 @@ void sun4c_mmu_device::insn_data_w(const uint32_t offset, const uint32_t data, c
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const uint32_t tmp = entry.page | (offset & 0x3ff);
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||||
//printf("sun4: write translated vaddr %08x to phys %08x type %d, PTE %08x, ASI %d, PC=%x\n", offset<<2, tmp<<2, entry.type, entry.to_uint(), asi, m_cpu->pc());
|
||||
|
||||
switch (entry.type)
|
||||
{
|
||||
case 0: // type 0
|
||||
@ -535,7 +558,6 @@ void sun4c_mmu_device::insn_data_w(const uint32_t offset, const uint32_t data, c
|
||||
const uint32_t addr_mask = m_ram_set_mask[set];
|
||||
const uint32_t masked_addr = m_ram_set_base[set] + (tmp & addr_mask);
|
||||
COMBINE_DATA((m_ram_ptr + masked_addr));
|
||||
//printf("mask %08x, masked %08x\n", addr_mask, masked_addr);
|
||||
}
|
||||
else if (tmp >= 0x4000000 >> 2 && tmp < 0x10000000 >> 2)
|
||||
{
|
||||
@ -544,12 +566,11 @@ void sun4c_mmu_device::insn_data_w(const uint32_t offset, const uint32_t data, c
|
||||
return;
|
||||
|
||||
case 1: // type 1
|
||||
//printf("write device space @ %x = %08x\n", tmp << 2, data);
|
||||
m_type1_w(tmp, data, mem_mask);
|
||||
return;
|
||||
|
||||
default:
|
||||
//logerror("sun4c_mmu: access to memory type not defined, %d %08x = %08x & %08x\n", entry.type, tmp, data, mem_mask);
|
||||
LOGMASKED(LOG_UNKNOWN_SPACE, "write unknown space type %d, %08x = %08x & %08x, PC=%08x\n", entry.type, tmp << 2, data, mem_mask, m_cpu->pc());
|
||||
m_host->set_mae();
|
||||
m_buserr[0] = 0x8020;
|
||||
m_buserr[1] = offset << 2;
|
||||
@ -558,7 +579,7 @@ void sun4c_mmu_device::insn_data_w(const uint32_t offset, const uint32_t data, c
|
||||
}
|
||||
else
|
||||
{
|
||||
//logerror("sun4c: INVALID PTE entry %d %08x written! data=%08x vaddr=%x PC=%x\n", entry_index, m_pagemap[entry_index].to_uint(), data, offset << 2, m_cpu->pc());
|
||||
LOGMASKED(LOG_INVALID_PTE, "write invalid PTE %d (%08x), %08x = %08x & %08x, PC=%08x\n", entry_index, m_pagemap[entry_index].to_uint(), offset << 2, data, mem_mask, m_cpu->pc());
|
||||
m_host->set_mae();
|
||||
m_buserr[0] |= 0x8080; // write cycle, invalid PTE
|
||||
m_buserr[1] = offset << 2;
|
||||
|
||||
@ -887,6 +887,8 @@ READ32_MEMBER( sun4_state::sun4_segment_map_r )
|
||||
return m_curr_segmap[(offset>>16) & 0xfff]<<16;
|
||||
else if (mem_mask == 0xff000000)
|
||||
return m_curr_segmap[(offset>>16) & 0xfff]<<24;
|
||||
else if (mem_mask == 0xffffffff)
|
||||
return m_curr_segmap[(offset>>16) & 0xfff];
|
||||
else
|
||||
logerror("sun4: read segment map w/ unknown mask %08x\n", mem_mask);
|
||||
return 0x0;
|
||||
@ -1440,16 +1442,10 @@ WRITE8_MEMBER( sun4_state::irq_w )
|
||||
|
||||
if (BIT(changed, 0))
|
||||
{
|
||||
if (BIT(m_irq_reg, 7))
|
||||
{
|
||||
//logerror("Changing interrupt enable, %s IRQ14\n", BIT(data, 0) && BIT(m_counter[2] | m_counter[3], 31) ? "asserting" : "deasserting");
|
||||
m_maincpu->set_input_line(SPARC_IRQ14, BIT(data, 0) && BIT(m_counter[2] | m_counter[3], 31) ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
if (BIT(m_irq_reg, 5))
|
||||
{
|
||||
//logerror("Changing interrupt enable, %s IRQ10\n", BIT(data, 0) && BIT(m_counter[0] | m_counter[1], 31) ? "asserting" : "deasserting");
|
||||
m_maincpu->set_input_line(SPARC_IRQ10, BIT(data, 0) && BIT(m_counter[0] | m_counter[1], 31) ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
if (BIT(m_irq_reg, 7) && BIT(m_counter[2] | m_counter[3], 31))
|
||||
m_maincpu->set_input_line(SPARC_IRQ14, BIT(data, 0) ? ASSERT_LINE : CLEAR_LINE);
|
||||
if (BIT(m_irq_reg, 5) && BIT(m_counter[0] | m_counter[1], 31))
|
||||
m_maincpu->set_input_line(SPARC_IRQ10, BIT(data, 0) ? ASSERT_LINE : CLEAR_LINE);
|
||||
if (BIT(m_irq_reg, 3))
|
||||
m_maincpu->set_input_line(SPARC_IRQ6, BIT(data, 0) ? ASSERT_LINE : CLEAR_LINE);
|
||||
if (BIT(m_irq_reg, 2))
|
||||
@ -1459,16 +1455,10 @@ WRITE8_MEMBER( sun4_state::irq_w )
|
||||
}
|
||||
else if (BIT(m_irq_reg, 0))
|
||||
{
|
||||
if (BIT(changed, 7))
|
||||
{
|
||||
//logerror("Changing IRQ14 enable, %s IRQ14\n", BIT(data, 7) && BIT(m_counter[2] | m_counter[3], 31) ? "asserting" : "deasserting");
|
||||
m_maincpu->set_input_line(SPARC_IRQ14, BIT(m_irq_reg, 7) && BIT(m_counter[2] | m_counter[3], 31) ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
if (BIT(changed, 5))
|
||||
{
|
||||
//logerror("Changing IRQ10 enable, %s IRQ10\n", BIT(data, 7) && BIT(m_counter[0] | m_counter[1], 31) ? "asserting" : "deasserting");
|
||||
m_maincpu->set_input_line(SPARC_IRQ10, BIT(m_irq_reg, 5) && BIT(m_counter[0] | m_counter[1], 31) ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
if (BIT(changed, 7) && BIT(m_counter[2] | m_counter[3], 31))
|
||||
m_maincpu->set_input_line(SPARC_IRQ14, BIT(m_irq_reg, 7) ? ASSERT_LINE : CLEAR_LINE);
|
||||
if (BIT(changed, 5) && BIT(m_counter[0] | m_counter[1], 31))
|
||||
m_maincpu->set_input_line(SPARC_IRQ10, BIT(m_irq_reg, 5) ? ASSERT_LINE : CLEAR_LINE);
|
||||
if (BIT(changed, 3))
|
||||
m_maincpu->set_input_line(SPARC_IRQ6, BIT(m_irq_reg, 3) ? ASSERT_LINE : CLEAR_LINE);
|
||||
if (BIT(changed, 2))
|
||||
|
||||
Loading…
Reference in New Issue
Block a user