From 0314b102e56dec0a0a9a106fa9f11073d74bb069 Mon Sep 17 00:00:00 2001 From: Brandon Munger Date: Mon, 14 Mar 2016 00:00:34 -0400 Subject: [PATCH] r9751: Fix more DMA issues and add more logging --- src/mame/drivers/r9751.cpp | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/src/mame/drivers/r9751.cpp b/src/mame/drivers/r9751.cpp index fd93f310e2e..89cd7da81b0 100644 --- a/src/mame/drivers/r9751.cpp +++ b/src/mame/drivers/r9751.cpp @@ -51,6 +51,7 @@ #define TRACE_SMIOC 0 #define TRACE_CPU_REG 0 #define TRACE_LED 0 +#define TRACE_DMA 0 class r9751_state : public driver_device { @@ -116,14 +117,16 @@ READ8_MEMBER(r9751_state::pdc_dma_r) { /* This callback function takes the value written to 0xFF01000C as the bank offset */ UINT32 address = (fdd_dma_bank & 0x7FFFF800) + (offset&0xFFFF); + if(TRACE_DMA) logerror("DMA READ: %08X DATA: %08X\n", address, m_maincpu->space(AS_PROGRAM).read_byte(address)); return m_maincpu->space(AS_PROGRAM).read_byte(address); } WRITE8_MEMBER(r9751_state::pdc_dma_w) { /* This callback function takes the value written to 0xFF01000C as the bank offset */ - UINT32 address = (fdd_dma_bank & 0x7FFFF800) + (data&0xFFFF); - m_maincpu->space(AS_PROGRAM).write_byte(m_pdc->fdd_68k_dma_address,address); + UINT32 address = (fdd_dma_bank & 0x7FFFF800) + (m_pdc->fdd_68k_dma_address&0xFFFF); + m_maincpu->space(AS_PROGRAM).write_byte(address,data); + if(TRACE_DMA) logerror("DMA WRITE: %08X DATA: %08X\n", address,data); } DRIVER_INIT_MEMBER(r9751_state,r9751) @@ -177,7 +180,7 @@ READ32_MEMBER( r9751_state::r9751_mmio_5ff_r ) return 0; case 0x30B0: /* FDD command completion status */ data = (m_pdc->reg_p5 << 8) + m_pdc->reg_p4; - if(TRACE_FDC) logerror("--- SCSI FDD command completion status - Read: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000); + if(TRACE_FDC && data != 0) logerror("--- SCSI FDD command completion status - Read: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000); return data; default: if(TRACE_FDC || TRACE_HDC || TRACE_SMIOC) logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000, 0, mem_mask); @@ -229,7 +232,7 @@ WRITE32_MEMBER( r9751_state::r9751_mmio_5ff_w ) if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000); break; case 0x04B0: /* FDD RESET PDC */ - if(TRACE_FDC) logerror("PDC RESET, PC: %08X\n", space.machine().firstcpu->pc()); + if(TRACE_FDC) logerror("PDC RESET, PC: %08X DATA: %08X\n", space.machine().firstcpu->pc(),data); m_pdc->reset(); break; case 0x08B0: /* FDD SCSI read command */ @@ -249,16 +252,16 @@ WRITE32_MEMBER( r9751_state::r9751_mmio_5ff_w ) m_pdc->reg_p38 |= 0x2; /* Set bit 1 on port 38 register, PDC polls this port looking for a command */ if(TRACE_FDC) logerror("--- FDD Old Command: %02X and %02X\n", data_b0, data_b1); break; - case 0x80B0: /* fdd_dest_address register */ + case 0xC0B0: + case 0xC1B0: /* fdd_dest_address register */ fdd_dest_address = data << 1; - if(TRACE_FDC) logerror("--- FDD destination address: %08X\n", fdd_dest_address); + if(TRACE_FDC) logerror("--- FDD destination address: %08X PC: %08X Register: %08X\n", (fdd_dma_bank & 0x7FFFF800) + (fdd_dest_address&0xFFFF), space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000); data_b0 = data & 0xFF; data_b1 = (data & 0xFF00) >> 8; m_pdc->reg_p6 = data_b0; m_pdc->reg_p7 = data_b1; break; - case 0xC0B0: - case 0xC1B0: /* FDD command address register */ + case 0x80B0: /* FDD command address register */ UINT32 fdd_scsi_command; UINT32 fdd_scsi_command2; unsigned char c_fdd_scsi_command[8]; // Array for SCSI command @@ -269,14 +272,14 @@ WRITE32_MEMBER( r9751_state::r9751_mmio_5ff_w ) m_pdc->reg_p5 = 0; /* Send FDD SCSI command location address to PDC 0x2, 0x3 */ - if(TRACE_FDC) logerror("--- FDD command address: %08X\n", data); + if(TRACE_FDC) logerror("--- FDD command address: %08X PC: %08X Register: %08X\n", (fdd_dma_bank & 0x7FFFF800) + ((data << 1)&0xFFFF), space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000); data_b0 = data & 0xFF; data_b1 = (data & 0xFF00) >> 8; m_pdc->reg_p2 = data_b0; m_pdc->reg_p3 = data_b1; - fdd_scsi_command = swap_uint32(m_mem->read_dword(data << 1)); - fdd_scsi_command2 = swap_uint32(m_mem->read_dword((data << 1)+4)); + fdd_scsi_command = swap_uint32(m_mem->read_dword((fdd_dma_bank & 0x7FFFF800) + ((data << 1)&0xFFFF))); + fdd_scsi_command2 = swap_uint32(m_mem->read_dword(((fdd_dma_bank & 0x7FFFF800) + ((data << 1)&0xFFFF))+4)); memcpy(c_fdd_scsi_command,&fdd_scsi_command,4); memcpy(c_fdd_scsi_command+4,&fdd_scsi_command2,4); @@ -326,11 +329,14 @@ WRITE32_MEMBER( r9751_state::r9751_mmio_ff01_w ) { case 0x000C: /* FDD DMA Offset */ fdd_dma_bank = data; + if(TRACE_DMA) logerror("Banking register(FDD): %08X PC: %08X Data: %08X\n", offset << 2 | 0xFF010000, space.machine().firstcpu->pc(), data); return; case 0x0010: /* SMIOC DMA Offset */ smioc_dma_bank = data; + if(TRACE_DMA) logerror("Banking register(SMIOC): %08X PC: %08X Data: %08X\n", offset << 2 | 0xFF010000, space.machine().firstcpu->pc(), data); return; default: + if(TRACE_DMA) logerror("Banking register(Unknown): %08X PC: %08X Data: %08X\n", offset << 2 | 0xFF010000, space.machine().firstcpu->pc(), data); return; } } @@ -376,6 +382,7 @@ WRITE32_MEMBER( r9751_state::r9751_mmio_ff05_w ) return; case 0x0320: timer_32khz_last = machine().time(); + return; default: if(TRACE_CPU_REG) logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), offset << 2 | 0xFF050000, data, mem_mask); return;