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bml3: Define master clock in xtal.cpp (nw)

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ti_fdc: Schematic shows a 2 MHz XTAL on board (nw)
This commit is contained in:
AJR 2019-05-18 17:56:11 -04:00
parent 52f299f616
commit 0330e67285
3 changed files with 3 additions and 2 deletions
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2
src/devices/bus/ti99/peb/ti_fdc.cpp
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@ -407,7 +407,7 @@ ROM_END
void ti_fdc_device::device_add_mconfig(machine_config& config)
{
FD1771(config, m_fd1771, 1_MHz_XTAL);
FD1771(config, m_fd1771, 2_MHz_XTAL / 2);
m_fd1771->intrq_wr_callback().set(FUNC(ti_fdc_device::fdc_irq_w));
m_fd1771->drq_wr_callback().set(FUNC(ti_fdc_device::fdc_drq_w));
m_fd1771->hld_wr_callback().set(FUNC(ti_fdc_device::fdc_hld_w));

1
src/emu/xtal.cpp
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@ -332,6 +332,7 @@ const double XTAL::known_xtals[] = {
32'000'000, /* 32_MHz_XTAL - */
32'147'000, /* 32.147_MHz_XTAL Ampex 210+ 132-column display clock */
32'220'000, /* 32.22_MHz_XTAL Typically used on 90's Data East PCBs (close to 9x NTSC subcarrier which is 32.215905Mhz */
32'256'000, /* 32.256_MHz_XTAL Hitachi MB-6890 */
32'317'400, /* 32.3174_MHz_XTAL DEC VT330, VT340 */
32'530'400, /* 32.5304_MHz_XTAL Seta 2 */
33'000'000, /* 33_MHz_XTAL Sega Model 3 video board */

2
src/mame/drivers/bml3.cpp
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@ -37,7 +37,7 @@
// System clock definitions, from the MB-6890 servce manual, p.48:
#define MASTER_CLOCK ( 32256000 ) // Master clock crystal (X1) frequency, 32.256 MHz. "fx" in the manual.
#define MASTER_CLOCK ( 32.256_MHz_XTAL ) // Master clock crystal (X1) frequency, 32.256 MHz. "fx" in the manual.
#define D80_CLOCK ( MASTER_CLOCK / 2 ) // Graphics dot clock in 80-column mode. ~16 MHz.
#define D40_CLOCK ( D80_CLOCK / 2 ) // Graphics dot clock in 40-column mode. ~8 MHz.