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netlist: More dip macros and device refactoring

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* Updated 7450, 7473/7473A, 7474, 7475/7477 devices to use DIP macros
instead of C++ DIPs.
* Reworked 7475/7477 more in the style of 7474, leveraging system signal
activation and edge detection.
This commit is contained in:
Aaron Giles 2020-08-01 18:25:54 +02:00 committed by couriersud
parent 15172f15ca
commit 0487858692
11 changed files with 267 additions and 374 deletions
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10
src/lib/netlist/devices/net_lib.cpp
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@ -74,17 +74,11 @@ namespace devices
LIB_ENTRY(7448)
#endif
LIB_ENTRY(7450)
LIB_ENTRY(7450_dip)
LIB_ENTRY(7473)
LIB_ENTRY(7473_dip)
LIB_ENTRY(7473A)
LIB_ENTRY(7473A_dip)
LIB_ENTRY(7474)
LIB_ENTRY(7474_dip)
LIB_ENTRY(7475)
LIB_ENTRY(7475_dip)
LIB_ENTRY(7477)
LIB_ENTRY(7477_dip)
LIB_ENTRY(7475_GATE)
LIB_ENTRY(7477_GATE)
LIB_ENTRY(7483)
LIB_ENTRY(7483_dip)
LIB_ENTRY(7485)

34
src/lib/netlist/devices/nld_7450.cpp
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@ -71,41 +71,7 @@ namespace netlist
nld_power_pins m_power_pins;
};
NETLIB_OBJECT(7450_dip)
{
NETLIB_CONSTRUCTOR(7450_dip)
, m_A(*this, "A")
, m_B(*this, "B")
{
register_subalias("1", m_A.m_A);
register_subalias("2", m_B.m_A);
register_subalias("3", m_B.m_B);
register_subalias("4", m_B.m_C);
register_subalias("5", m_B.m_D);
register_subalias("6", m_B.m_Q);
register_subalias("7", "A.GND");
register_subalias("8", m_A.m_Q);
register_subalias("9", m_A.m_C);
register_subalias("10", m_A.m_D);
//register_subalias("11", m_1.m_X1);
//register_subalias("12", m_1.m_X1Q);
register_subalias("13", m_A.m_B);
register_subalias("14", "A.VCC");
connect("A.GND", "B.GND");
connect("A.VCC", "B.VCC");
}
//NETLIB_RESETI();
//NETLIB_UPDATEI();
NETLIB_SUB(7450) m_A;
NETLIB_SUB(7450) m_B;
};
NETLIB_DEVICE_IMPL(7450, "TTL_7450_ANDORINVERT", "+A,+B,+C,+D,@VCC,@GND")
NETLIB_DEVICE_IMPL(7450_dip, "TTL_7450_DIP", "")
} //namespace devices
} // namespace netlist

14
src/lib/netlist/devices/nld_7450.h
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@ -26,16 +26,8 @@
#include "netlist/nl_setup.h"
#define TTL_7450_ANDORINVERT(name, cI1, cI2, cI3, cI4) \
NET_REGISTER_DEV(TTL_7450_ANDORINVERT, name) \
NET_CONNECT(name, GND, GND) \
NET_CONNECT(name, VCC, VCC) \
NET_CONNECT(name, A, cI1) \
NET_CONNECT(name, B, cI2) \
NET_CONNECT(name, C, cI3) \
NET_CONNECT(name, D, cI4)
#define TTL_7450_DIP(name) \
NET_REGISTER_DEV(TTL_7450_DIP, name)
// usage: TTL_7450_ANDORINVERT(name, cI1, cI2, cI3, cI4)
#define TTL_7450_ANDORINVERT(...) \
NET_REGISTER_DEVEXT(TTL_7450_ANDORINVERT, __VA_ARGS__)
#endif /* NLD_7450_H_ */

64
src/lib/netlist/devices/nld_7473.cpp
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@ -85,72 +85,8 @@ namespace netlist
};
NETLIB_OBJECT(7473_dip)
{
NETLIB_CONSTRUCTOR(7473_dip)
, m_A(*this, "A")
, m_B(*this, "B")
{
register_subalias("1", m_A.m_CLK);
register_subalias("2", m_A.m_CLRQ);
register_subalias("3", m_A.m_K);
register_subalias("4", "A.VCC");
register_subalias("5", m_B.m_CLK);
register_subalias("6", m_B.m_CLRQ);
register_subalias("7", m_B.m_J);
register_subalias("8", m_B.m_QQ);
register_subalias("9", m_B.m_Q);
register_subalias("10", m_B.m_K);
register_subalias("11", "A.GND");
register_subalias("12", m_B.m_Q);
register_subalias("13", m_A.m_QQ);
register_subalias("14", m_A.m_J);
connect("A.GND", "B.GND");
connect("A.VCC", "B.VCC");
}
private:
NETLIB_SUB(7473) m_A;
NETLIB_SUB(7473) m_B;
};
NETLIB_OBJECT(7473A_dip)
{
NETLIB_CONSTRUCTOR(7473A_dip)
, m_A(*this, "A")
, m_B(*this, "B")
{
register_subalias("1", m_A.m_CLK);
register_subalias("2", m_A.m_CLRQ);
register_subalias("3", m_A.m_K);
register_subalias("4", "A.VCC");
register_subalias("5", m_B.m_CLK);
register_subalias("6", m_B.m_CLRQ);
register_subalias("7", m_B.m_J);
register_subalias("8", m_B.m_QQ);
register_subalias("9", m_B.m_Q);
register_subalias("10", m_B.m_K);
register_subalias("11", "A.GND");
register_subalias("12", m_B.m_Q);
register_subalias("13", m_A.m_QQ);
register_subalias("14", m_A.m_J);
connect("A.GND", "B.GND");
connect("A.VCC", "B.VCC");
}
private:
NETLIB_SUB(7473A) m_A;
NETLIB_SUB(7473A) m_B;
};
NETLIB_DEVICE_IMPL(7473, "TTL_7473", "+CLK,+J,+K,+CLRQ,@VCC,@GND")
NETLIB_DEVICE_IMPL(7473A, "TTL_7473A", "+CLK,+J,+K,+CLRQ,@VCC,@GND")
NETLIB_DEVICE_IMPL(7473_dip, "TTL_7473_DIP", "")
NETLIB_DEVICE_IMPL(7473A_dip, "TTL_7473A_DIP", "")
} //namespace devices
} // namespace netlist

22
src/lib/netlist/devices/nld_7473.h
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@ -62,23 +62,11 @@
#include "netlist/nl_setup.h"
#define TTL_7473(name, cCLK, cJ, cK, cCLRQ) \
NET_REGISTER_DEV(TTL_7473, name) \
NET_CONNECT(name, GND, GND) \
NET_CONNECT(name, VCC, VCC) \
NET_CONNECT(name, CLK, cCLK) \
NET_CONNECT(name, J, cJ) \
NET_CONNECT(name, K, cK) \
NET_CONNECT(name, CLRQ, cCLRQ)
// usage: TTL_7473(name, cCLK, cJ, cK, cCLRQ)
#define TTL_7473(...) \
NET_REGISTER_DEVEXT(TTL_7473, __VA_ARGS__)
#define TTL_7473A(name, cCLK, cJ, cK, cCLRQ) \
TTL_7473(name, cCLK, cJ, cK, cCLRQ)
#define TTL_7473_DIP(name) \
NET_REGISTER_DEV(TTL_7473_DIP, name)
#define TTL_7473A_DIP(name) \
NET_REGISTER_DEV(TTL_7473A_DIP, name)
#define TTL_7473A(...) \
TTL_7473(__VA_ARGS__)
#endif /* NLD_7473_H_ */

34
src/lib/netlist/devices/nld_7474.cpp
View File

@ -82,41 +82,7 @@ namespace netlist
}
};
NETLIB_OBJECT(7474_dip)
{
NETLIB_CONSTRUCTOR(7474_dip)
, m_A(*this, "A")
, m_B(*this, "B")
{
register_subalias("1", "A.CLRQ");
register_subalias("2", "A.D");
register_subalias("3", "A.CLK");
register_subalias("4", "A.PREQ");
register_subalias("5", "A.Q");
register_subalias("6", "A.QQ");
register_subalias("7", "A.GND");
register_subalias("8", "B.QQ");
register_subalias("9", "B.Q");
register_subalias("10", "B.PREQ");
register_subalias("11", "B.CLK");
register_subalias("12", "B.D");
register_subalias("13", "B.CLRQ");
register_subalias("14", "A.VCC");
connect("A.GND", "B.GND");
connect("A.VCC", "B.VCC");
}
//NETLIB_UPDATEI();
//NETLIB_RESETI();
private:
NETLIB_SUB(7474) m_A;
NETLIB_SUB(7474) m_B;
};
NETLIB_DEVICE_IMPL(7474, "TTL_7474", "+CLK,+D,+CLRQ,+PREQ,@VCC,@GND")
NETLIB_DEVICE_IMPL(7474_dip, "TTL_7474_DIP", "")
} //namespace devices
} // namespace netlist

14
src/lib/netlist/devices/nld_7474.h
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@ -44,16 +44,8 @@
#include "netlist/nl_setup.h"
#define TTL_7474(name, cCLK, cD, cCLRQ, cPREQ) \
NET_REGISTER_DEV(TTL_7474, name) \
NET_CONNECT(name, GND, GND) \
NET_CONNECT(name, VCC, VCC) \
NET_CONNECT(name, CLK, cCLK) \
NET_CONNECT(name, D, cD) \
NET_CONNECT(name, CLRQ, cCLRQ) \
NET_CONNECT(name, PREQ, cPREQ)
#define TTL_7474_DIP(name) \
NET_REGISTER_DEV(TTL_7474_DIP, name)
// usage: TTL_7474(name, cCLK, cD, cCLRQ, cPREQ)
#define TTL_7474(...) \
NET_REGISTER_DEVEXT(TTL_7474, __VA_ARGS__)
#endif /* NLD_7474_H_ */

211
src/lib/netlist/devices/nld_7475.cpp
View File

@ -13,197 +13,62 @@ namespace netlist
{
namespace devices
{
NETLIB_OBJECT(7477)
template<bool _HasQQ>
NETLIB_OBJECT(7475_GATE_BASE)
{
NETLIB_CONSTRUCTOR(7477)
, m_C1C2(*this, "C1C2", NETLIB_DELEGATE(inputs))
, m_C3C4(*this, "C3C4", NETLIB_DELEGATE(inputs))
, m_last_Q(*this, "m_last_Q", 0)
, m_D(*this, {"D1", "D2", "D3", "D4"}, NETLIB_DELEGATE(inputs))
, m_Q(*this, {"Q1", "Q2", "Q3", "Q4"})
NETLIB_CONSTRUCTOR(7475_GATE_BASE)
, m_D(*this, "D", NETLIB_DELEGATE(inputs))
, m_CLK(*this, "CLK", NETLIB_DELEGATE(clk))
, m_Q(*this, "Q")
, m_QQ(*this, "QQ")
, m_nextD(*this, "m_nextD", 0)
, m_power_pins(*this)
{
register_subalias("Q1", m_Q[0]);
}
NETLIB_RESETI()
{
m_last_Q = 0;
m_CLK.set_state(logic_t::STATE_INP_LH);
m_nextD = 0;
}
NETLIB_HANDLERI(clk)
{
newstate(m_nextD, !m_nextD);
m_CLK.inactivate();
}
NETLIB_HANDLERI(inputs)
{
netlist_sig_t c1c2 = m_C1C2();
netlist_sig_t c3c4 = m_C3C4();
if (c1c2 && c3c4)
{
update_outputs(0, 4);
}
else if (c1c2)
{
update_outputs(0, 2);
}
else if (c3c4)
{
update_outputs(2, 4);
}
m_nextD = m_D();
m_CLK.activate_lh();
}
void update_outputs(std::size_t start, std::size_t end)
{
for (std::size_t i=start; i<end; i++)
{
netlist_sig_t d = m_D[i]();
if (d != ((m_last_Q >> i) & 1))
m_Q[i].push(d, d != 0 ? NLTIME_FROM_NS(30) : NLTIME_FROM_NS(25));
m_last_Q &= ~(1 << i);
m_last_Q |= d << i;
}
}
friend class NETLIB_NAME(7477_dip);
friend class NETLIB_NAME(7475_dip);
// FIXME: needs cleanup
friend class NETLIB_NAME(7475);
private:
logic_input_t m_C1C2;
logic_input_t m_C3C4;
state_var<unsigned> m_last_Q;
object_array_t<logic_input_t, 4> m_D;
object_array_t<logic_output_t, 4> m_Q;
logic_input_t m_D;
logic_input_t m_CLK;
logic_output_t m_Q;
logic_output_t m_QQ;
state_var<netlist_sig_t> m_nextD;
nld_power_pins m_power_pins;
void newstate(const netlist_sig_t stateQ, const netlist_sig_t stateQQ)
{
// 0: High-to-low 40 ns, 1: Low-to-high 25 ns
static constexpr const std::array<netlist_time, 2> delay = { NLTIME_FROM_NS(40), NLTIME_FROM_NS(25) };
m_Q.push(stateQ, delay[stateQ]);
if (_HasQQ)
m_QQ.push(stateQQ, delay[stateQQ]);
}
};
NETLIB_OBJECT(7475)
{
NETLIB_CONSTRUCTOR(7475)
, m_C1C2(*this, "C1C2", NETLIB_DELEGATE(inputs))
, m_C3C4(*this, "C3C4", NETLIB_DELEGATE(inputs))
, m_last_Q(*this, "m_last_Q", 0)
, m_D(*this, {"D1", "D2", "D3", "D4"}, NETLIB_DELEGATE(inputs))
, m_Q(*this, {"Q1", "Q2", "Q3", "Q4"})
, m_QQ(*this, {"QQ1", "QQ2", "QQ3", "QQ4"})
, m_power_pins(*this)
{
register_subalias("Q1", m_Q[0]);
}
using NETLIB_NAME(7475_GATE) = NETLIB_NAME(7475_GATE_BASE)<true>;
using NETLIB_NAME(7477_GATE) = NETLIB_NAME(7475_GATE_BASE)<false>;
NETLIB_RESETI()
{
m_last_Q = 0;
}
NETLIB_HANDLERI(inputs)
{
unsigned start_q = m_last_Q;
netlist_sig_t c1c2 = m_C1C2();
netlist_sig_t c3c4 = m_C3C4();
if (c1c2 && c3c4)
{
update_outputs(0, 4);
}
else if (c1c2)
{
update_outputs(0, 2);
}
else if (c3c4)
{
update_outputs(2, 4);
}
for (std::size_t i=0; i<4; i++)
{
unsigned last_bit = (m_last_Q >> i) & 1;
unsigned start_bit = (start_q >> i) & 1;
if (last_bit != start_bit)
m_QQ[i].push(last_bit ^ 1, last_bit != 0 ? NLTIME_FROM_NS(15) : NLTIME_FROM_NS(40));
}
}
void update_outputs(std::size_t start, std::size_t end)
{
for (std::size_t i=start; i<end; i++)
{
netlist_sig_t d = m_D[i]();
if (d != ((m_last_Q >> i) & 1))
m_Q[i].push(d, d != 0 ? NLTIME_FROM_NS(30) : NLTIME_FROM_NS(25));
m_last_Q &= ~(1 << i);
m_last_Q |= d << i;
}
}
friend class NETLIB_NAME(7477_dip);
friend class NETLIB_NAME(7475_dip);
private:
logic_input_t m_C1C2;
logic_input_t m_C3C4;
state_var<unsigned> m_last_Q;
object_array_t<logic_input_t, 4> m_D;
object_array_t<logic_output_t, 4> m_Q;
object_array_t<logic_output_t, 4> m_QQ;
nld_power_pins m_power_pins;
};
NETLIB_OBJECT(7475_dip)
{
NETLIB_CONSTRUCTOR(7475_dip)
, A(*this, "A")
{
register_subalias("1", A.m_QQ[0]);
register_subalias("2", A.m_D[0]);
register_subalias("3", A.m_D[1]);
register_subalias("4", A.m_C3C4);
register_subalias("5", "A.VCC");
register_subalias("6", A.m_D[2]);
register_subalias("7", A.m_D[3]);
register_subalias("8", A.m_QQ[3]);
register_subalias("9", A.m_Q[3]);
register_subalias("10", A.m_Q[2]);
register_subalias("11", A.m_QQ[2]);
register_subalias("12", "A.GND");
register_subalias("13", A.m_C1C2);
register_subalias("14", A.m_QQ[1]);
register_subalias("15", A.m_Q[1]);
register_subalias("16", A.m_Q[0]);
}
//NETLIB_RESETI() {}
private:
NETLIB_SUB(7475) A;
};
NETLIB_OBJECT(7477_dip)
{
NETLIB_CONSTRUCTOR(7477_dip)
, A(*this, "A")
{
register_subalias("1", A.m_D[0]);
register_subalias("2", A.m_D[1]);
register_subalias("3", A.m_C3C4);
register_subalias("4", "A.VCC");
register_subalias("5", A.m_D[2]);
register_subalias("6", A.m_D[3]);
//register_subalias("7", ); ==> NC
register_subalias("8", A.m_Q[3]);
register_subalias("9", A.m_Q[2]);
//register_subalias("10", ); ==> NC
register_subalias("11", "A.GND");
register_subalias("12", A.m_C1C2);
register_subalias("13", A.m_Q[1]);
register_subalias("14", A.m_Q[0]);
}
//NETLIB_RESETI() {}
private:
NETLIB_SUB(7477) A;
};
NETLIB_DEVICE_IMPL(7475, "TTL_7475", "")
NETLIB_DEVICE_IMPL(7475_dip, "TTL_7475_DIP", "")
NETLIB_DEVICE_IMPL(7477, "TTL_7477", "")
NETLIB_DEVICE_IMPL(7477_dip, "TTL_7477_DIP", "")
NETLIB_DEVICE_IMPL(7475_GATE, "TTL_7475_GATE", "")
NETLIB_DEVICE_IMPL(7477_GATE, "TTL_7477_GATE", "")
} //namespace devices
} // namespace netlist

26
src/lib/netlist/devices/nld_7475.h
View File

@ -37,28 +37,10 @@
#include "netlist/nl_setup.h"
#define PARAMS_7475_7477(name, cC1C2, cC3C4, cD1, cD2, cD3, cD4) \
NET_CONNECT(name, GND, GND) \
NET_CONNECT(name, VCC, VCC) \
NET_CONNECT(name, C1C2, cC1C2) \
NET_CONNECT(name, C3C4, cC3C4) \
NET_CONNECT(name, D1, cD1) \
NET_CONNECT(name, D2, cD2) \
NET_CONNECT(name, D3, cD3) \
NET_CONNECT(name, D4, cD4)
#define TTL_7475_GATE(...) \
NET_REGISTER_DEVEXT(TTL_7475_GATE, __VA_ARGS__)
#define TTL_7475(name, cC1C2, cC3C4, cD1, cD2, cD3, cD4) \
NET_REGISTER_DEV(TTL_7475, name) \
PARAMS_7475_7477(name, cC1C2, cC3C4, cD1, cD2, cD3, cD4)
#define TTL_7477(name, cC1C2, cC3C4, cD1, cD2, cD3, cD4) \
NET_REGISTER_DEV(TTL_7477, name) \
PARAMS_7475_7477(name, cC1C2, cC3C4, cD1, cD2, cD3, cD4)
#define TTL_7475_DIP(name) \
NET_REGISTER_DEV(TTL_7475_DIP, name)
#define TTL_7477_DIP(name) \
NET_REGISTER_DEV(TTL_7477_DIP, name)
#define TTL_7477_GATE(...) \
NET_REGISTER_DEVEXT(TTL_7477_GATE, __VA_ARGS__)
#endif /* NLD_7475_H_ */

194
src/lib/netlist/macro/nlm_ttl74xx.cpp
View File

@ -682,6 +682,194 @@ static NETLIST_START(TTL_7437_DIP)
)
NETLIST_END()
/*
* DM7450: DUAL 2-WIDE 2-INPUT AND-OR-INVERT GATES (ONE GATE EXPANDABLE)
*
* +--------------+
* 1A |1 ++ 14| VCC
* 2A |2 13| 1B
* 2B |3 12| 1XQ
* 2C |4 7450 11| 1X
* 2D |5 10| 1D
* 2Y |6 9| 1C
* GND |7 8| 1Y
* +--------------+
*/
static NETLIST_START(TTL_7450_DIP)
TTL_7450_ANDORINVERT(A)
TTL_7450_ANDORINVERT(B)
NET_C(A.VCC, B.VCC)
NET_C(A.GND, B.GND)
NC_PIN(NC)
DIPPINS( /* +--------------+ */
A.A, /* 1A |1 ++ 14| VCC */ A.VCC,
B.A, /* 2A |2 13| 1B */ A.B,
B.B, /* 2B |3 12| 1XQ */ NC.I,
B.C, /* 2C |4 7450 11| 1X */ NC.I,
B.D, /* 2D |5 10| 1D */ A.D,
B.Q, /* 2Y |6 9| 1C */ A.C,
A.GND,/* GND |7 8| 1Y */ A.Q
/* +--------------+ */
)
NETLIST_END()
/*
* 7473: Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
* 7473A: Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
*
* +----------+
* 1CLK |1 ++ 14| 1J
* 1CLRQ |2 13| 1QQ
* 1K |3 12| 1Q
* VCC |4 7473 11| GND
* 2CLK |5 10| 2K
* 2CLRQ |6 9| 2Q
* 2J |7 8| 2QQ
* +----------+
*/
static NETLIST_START(TTL_7473_DIP)
TTL_7473(A)
TTL_7473(B)
NET_C(A.VCC, B.VCC)
NET_C(A.GND, B.GND)
DIPPINS( /* +----------+ */
A.CLK, /* 1CLK |1 ++ 14| 1J */ A.J,
A.CLRQ, /* 1CLRQ |2 13| 1QQ */ A.QQ,
A.K, /* 1K |3 12| 1Q */ A.Q,
A.VCC, /* VCC |4 7473 11| GND */ A.GND,
B.CLK, /* 2CLK |5 10| 2K */ B.K,
B.CLRQ, /* 2CLRQ |6 9| 2Q */ B.Q,
B.J, /* 2J |7 8| 2QQ */ B.QQ
/* +----------+ */
)
NETLIST_END()
static NETLIST_START(TTL_7473A_DIP)
TTL_7473A(A)
TTL_7473A(B)
NET_C(A.VCC, B.VCC)
NET_C(A.GND, B.GND)
DIPPINS( /* +----------+ */
A.CLK, /* 1CLK |1 ++ 14| 1J */ A.J,
A.CLRQ, /* 1CLRQ |2 13| 1QQ */ A.QQ,
A.K, /* 1K |3 12| 1Q */ A.Q,
A.VCC, /* VCC |4 7473A 11| GND */ A.GND,
B.CLK, /* 2CLK |5 10| 2K */ B.K,
B.CLRQ, /* 2CLRQ |6 9| 2Q */ B.Q,
B.J, /* 2J |7 8| 2QQ */ B.QQ
/* +----------+ */
)
NETLIST_END()
/*
* DM7474: Dual Positive-Edge-Triggered D Flip-Flops
* with Preset, Clear and Complementary Outputs
*
* +--------------+
* CLR1 |1 ++ 14| VCC
* D1 |2 13| CLR2
* CLK1 |3 12| D2
* PR1 |4 7474 11| CLK2
* Q1 |5 10| PR2
* Q1Q |6 9| Q2
* GND |7 8| Q2Q
* +--------------+
*/
static NETLIST_START(TTL_7474_DIP)
TTL_7474(A)
TTL_7474(B)
NET_C(A.VCC, B.VCC)
NET_C(A.GND, B.GND)
DIPPINS( /* +--------------+ */
A.CLRQ, /* CLR1 |1 ++ 14| VCC */ A.VCC,
A.D, /* D1 |2 13| CLR2 */ B.CLRQ,
A.CLK, /* CLK1 |3 12| D2 */ B.D,
A.PREQ, /* PR1 |4 7474 11| CLK2 */ B.CLK,
A.Q, /* Q1 |5 10| PR2 */ B.PREQ,
A.QQ, /* Q1Q |6 9| Q2 */ B.Q,
A.GND, /* GND |7 8| Q2Q */ B.QQ
/* +-------------+ */
)
NETLIST_END()
/*
* 7475: 4-Bit Bistable Latches with Complementary Outputs
* 7477: 4-Bit Bistable Latches
*
* +----------+ +----------+
* 1QQ |1 ++ 16| 1Q 1D |1 ++ 14| 1Q
* 1D |2 15| 2Q 2D |2 13| 2Q
* 2D |3 14| 2QQ 3C4C |3 12| 1C2C
* 3C4C |4 7475 13| 1C2C VCC |4 7477 11| GND
* VCC |5 12| GND 3D |5 10| NC
* 3D |6 11| 3QQ 4D |6 9| 3Q
* 4D |7 10| 3Q NC |7 8| 4Q
* 4QQ |8 9| 4Q +----------+
* +----------+
*/
static NETLIST_START(TTL_7475_DIP)
TTL_7475_GATE(A)
TTL_7475_GATE(B)
TTL_7475_GATE(C)
TTL_7475_GATE(D)
NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
NET_C(A.GND, B.GND, C.GND, D.GND)
NET_C(A.CLK, B.CLK)
NET_C(C.CLK, D.CLK)
DIPPINS( /* +----------+ */
A.QQ, /* 1QQ |1 ++ 16| 1Q */ A.Q,
A.D, /* 1D |2 15| 2Q */ B.Q,
B.D, /* 2D |3 14| 2QQ */ B.QQ,
C.CLK, /* 3C4C |4 7475 13| 1C2C */ A.CLK,
A.VCC, /* VCC |5 12| GND */ A.GND,
C.D, /* 3D |6 11| 3QQ */ C.QQ,
D.D, /* 4D |7 10| 3Q */ C.Q,
D.QQ, /* 4QQ |8 9| 4Q */ D.Q
/* +----------+ */
)
NETLIST_END()
static NETLIST_START(TTL_7477_DIP)
TTL_7477_GATE(A)
TTL_7477_GATE(B)
TTL_7477_GATE(C)
TTL_7477_GATE(D)
NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
NET_C(A.GND, B.GND, C.GND, D.GND)
NET_C(A.CLK, B.CLK)
NET_C(C.CLK, D.CLK)
NC_PIN(NC)
DIPPINS( /* +----------+ */
A.D, /* 1D |1 ++ 14| 1Q */ A.Q,
B.D, /* 2D |2 13| 2Q */ B.Q,
C.CLK, /* 3C4C |3 12| 1C2C */ A.CLK,
A.VCC, /* VCC |4 7477 11| GND */ A.GND,
C.D, /* 3D |5 10| NC */ NC.I,
D.D, /* 4D |6 9| 3Q */ C.Q,
NC.I, /* NC |7 8| 4Q */ D.Q
/* +----------+ */
)
NETLIST_END()
/*
* DM7486: Quad 2-Input Exclusive-OR Gates
*
@ -2025,6 +2213,12 @@ NETLIST_START(TTL74XX_lib)
LOCAL_LIB_ENTRY(TTL_7437_DIP)
LOCAL_LIB_ENTRY(TTL_7442_DIP)
LOCAL_LIB_ENTRY(TTL_7448_DIP)
LOCAL_LIB_ENTRY(TTL_7450_DIP)
LOCAL_LIB_ENTRY(TTL_7473_DIP)
LOCAL_LIB_ENTRY(TTL_7473A_DIP)
LOCAL_LIB_ENTRY(TTL_7474_DIP)
LOCAL_LIB_ENTRY(TTL_7475_DIP)
LOCAL_LIB_ENTRY(TTL_7477_DIP)
LOCAL_LIB_ENTRY(TTL_7486_DIP)
LOCAL_LIB_ENTRY(TTL_74121_DIP)
LOCAL_LIB_ENTRY(TTL_74123_DIP)

18
src/lib/netlist/macro/nlm_ttl74xx.h
View File

@ -266,6 +266,24 @@
#define TTL_7448_DIP(name) \
NET_REGISTER_DEV(TTL_7448_DIP, name)
#define TTL_7450_DIP(name) \
NET_REGISTER_DEV(TTL_7450_DIP, name)
#define TTL_7473_DIP(name) \
NET_REGISTER_DEV(TTL_7473_DIP, name)
#define TTL_7473A_DIP(name) \
NET_REGISTER_DEV(TTL_7473A_DIP, name)
#define TTL_7474_DIP(name) \
NET_REGISTER_DEV(TTL_7474_DIP, name)
#define TTL_7475_DIP(name) \
NET_REGISTER_DEV(TTL_7475_DIP, name)
#define TTL_7477_DIP(name) \
NET_REGISTER_DEV(TTL_7477_DIP, name)
#define TTL_7486_GATE(name) \
NET_REGISTER_DEV(TTL_7486_GATE, name)