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---------------------------------- Telex 274-61C Sixteen Station Control Unit [Al Kossow, Bitsavers]
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@ -3999,6 +3999,7 @@ files {
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MAME_DIR .. "src/mame/drivers/talkingfb.cpp",
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MAME_DIR .. "src/mame/drivers/tavernie.cpp",
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MAME_DIR .. "src/mame/drivers/tecnbras.cpp",
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MAME_DIR .. "src/mame/drivers/telex274.cpp",
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MAME_DIR .. "src/mame/drivers/terak.cpp",
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MAME_DIR .. "src/mame/drivers/terco.cpp",
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MAME_DIR .. "src/mame/drivers/terminal.cpp",
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179
src/mame/drivers/telex274.cpp
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179
src/mame/drivers/telex274.cpp
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// license:BSD-3-Clause
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// copyright-holders:AJR
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/************************************************************************************************************
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Skeleton driver for Telex 274 IBM 3274-compatible coaxial controllers.
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The three main boards have the following components identified by PCB silkscreening and/or serial
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numbers:
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COMM IIS
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U1 Am27128A(?)-2DC ODD (203981-053)
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U2 Am27128A(?)-2DC EVEN (203982-053)
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U3 NEC D4361C-70 ODD PARITY
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U9 HM62256LP-12 ODD
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U10 HM62256LP-12 EVEN
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U11 NEC D4361C-70 EVEN PARITY
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U13 unknown 64-pin SDIP DMA
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U45 PAL20L8ANC ADD DECODE PAL (205264-002)
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U56 SCN68000CAN64 CPU
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U81 10.000000MHz 10 MHZ CLK
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U84 4.0000MHz 4 MHZ CLK
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U98 P8274 COMM CHIP
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U99 Am9513APC TIMER
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16 PORT COAX CONTROLLER
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U1 M5M4464P-12 BANK 0 D8:11
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U2 M5M4464P-12 BANK 1 D8:11
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U3 M5M4464P-12 BANK 0 D12:15
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U4 M5M4464P-12 BANK 1 D12:15
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U6 S 74F245N BUF D8:15
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U7 S 74F245N BUF D0:7
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U12 M5M4464P-12 BANK 0 D0:3
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U13 M5M4464P-12 BANK 1 D0:3
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U14 M5M4464P-12 BANK 0 D4:7
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U15 M5M4464P-12 BANK 1 D4:7
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U25 KM4164B-12 BANK 0 LOW
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U26 KM4164B-12 BANK 1 LOW
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U27 KM4164B-12 BANK 0 HIGH
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U28 KM4164B-12 BANK 1 HIGH
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U30 SN74LS195AN WATCHDOG TIMER
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U38 AMPAL16R8PC (205263-002)
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U41 PAL16R4ACN (204143-02)
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U44 S 74LS138N STATE DECODER
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U48 PAL20L8ANC MEMORY DECODER (205264-002)
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U64/89 PAL16R4ACN (204140-003)
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U65/90 PAL16R4ACN (204141-003)
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U66 TC17G022AP-0091 DEV 0-7 COAX
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U67/102 PAL16L8ANC (204142-001)
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U68 N82S129N (204570-002)
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U69 SN74LS273N MISC PORT OUT
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U83 S 74LS541N MISC PORT IN
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U84/107 S 74LS541N EXEC FIFO DRIVERS
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U101 TC17G022AP-0091 DEV 8-15 COAX
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EXAM BD SS-B
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U1/16 TMS 4464-15NL D12:D15
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U2/17 TMS 4464-15NL D8:D11
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U3/18 TMS 4464-15NL D4:D7
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U4/19 TMS 4464-15NL D0:D3
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U41 AMPAL16R8PC MEM CONTROL (205261-002)
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U62 PAL20L8ANC MEM DECODE (205264-002)
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U85 AMPAL16R8PC MEM CONTROL (205263-002)
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U92 PAL16R8BNC BUS ARB (205266-002)
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U105 HYB 41256-15 D15
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U106 HYB 41256-15 D14
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U107 HYB 41256-15 D13
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U108 HYB 41256-15 D12
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U109 HYB 41256-15 D11
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U110 HYB 41256-15 D10
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U113 MK48Z02BU-25 (0678A)
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U120 HYB 41256-15 D9
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U121 HYB 41256-15 D8
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U122 HYB 41256-15 D7
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U123 HYB 41256-15 D6
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U124 HYB 41256-15 D5
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U125 HYB 41256-15 D4
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U134 HYB 41256-15 D3
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U135 HYB 41256-15 D2
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U136 HYB 41256-15 D1
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U137 HYB 41256-15 D0
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U138 HYB 41256-15 HI PAR
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U139 HYB 41256-15 LO PAR
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While each of these boards has a CPU, program ROMs are present only on the "COMM" board. Programs for
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the other two boards should be loaded off floppy disk through the WD2797A-PL FDC which resides on the
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front panel. There are also no visible oscillators on this front panel or the "EXAM BD" and only one
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on the "COAX" board (18.8696MHz, likely used to generate data clocks for the protocol gate arrays).
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************************************************************************************************************/
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#include "emu.h"
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#include "cpu/m68000/m68000.h"
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#include "machine/am9513.h"
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#include "machine/z80sio.h"
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//#include "machine/wd_fdc.h"
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class telex274_state : public driver_device
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{
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public:
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telex274_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag)
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, m_maincpu(*this, "maincpu")
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, m_coaxcpu(*this, "coaxcpu")
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, m_examcpu(*this, "examcpu")
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{
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}
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void telex274(machine_config &config);
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private:
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void main_mem(address_map &map);
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void coax_mem(address_map &map);
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void exam_mem(address_map &map);
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required_device<cpu_device> m_maincpu;
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required_device<cpu_device> m_coaxcpu;
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required_device<cpu_device> m_examcpu;
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};
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void telex274_state::main_mem(address_map &map)
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{
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map(0x000000, 0x007fff).rom().region("program", 0);
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map(0x008000, 0x01ffff).ram();
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map(0x080000, 0x09ffff).ram();
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map(0xff811e, 0xff811f).nopr();
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map(0xff8810, 0xff8817).rw("mpsc", FUNC(i8274_new_device::cd_ba_r), FUNC(i8274_new_device::cd_ba_w)).umask16(0x00ff);
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map(0xff8818, 0xff881b).rw("maintimer", FUNC(am9513a_device::read8), FUNC(am9513a_device::write8)).umask16(0x00ff);
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}
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void telex274_state::coax_mem(address_map &map)
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{
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}
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void telex274_state::exam_mem(address_map &map)
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{
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}
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static INPUT_PORTS_START(telex274)
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INPUT_PORTS_END
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void telex274_state::telex274(machine_config &config)
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{
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M68000(config, m_maincpu, 10_MHz_XTAL);
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m_maincpu->set_addrmap(AS_PROGRAM, &telex274_state::main_mem);
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am9513a_device &maintimer(AM9513A(config, "maintimer", 4_MHz_XTAL));
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maintimer.out4_cb().set("mpsc", FUNC(i8274_new_device::rxca_w)); // ?
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maintimer.out4_cb().append("mpsc", FUNC(i8274_new_device::txca_w)); // ?
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maintimer.out5_cb().set("mpsc", FUNC(i8274_new_device::rxtxcb_w)); // ?
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I8274_NEW(config, "mpsc", 4'000'000);
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M68000(config, m_coaxcpu, 10'000'000);
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m_coaxcpu->set_addrmap(AS_PROGRAM, &telex274_state::coax_mem);
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m_coaxcpu->set_disable();
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M68000(config, m_examcpu, 10'000'000);
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m_examcpu->set_addrmap(AS_PROGRAM, &telex274_state::exam_mem);
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m_examcpu->set_disable();
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//AM9513A(config, "examtimer", 4'000'000);
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//WD2797(config, "fdc", 1'000'000);
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}
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ROM_START(telex274)
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ROM_REGION16_BE(0x8000, "program", 0)
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ROM_LOAD16_BYTE("203982-053_even.u2", 0x0000, 0x4000, CRC(56914ba9) SHA1(7a2a9e16491a024b4109c8589a2277d65536e629))
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ROM_LOAD16_BYTE("203981-053_odd.u1", 0x0001, 0x4000, CRC(04a9e2cf) SHA1(58255d6275b76aecd8b81d2ea23ca69167caf232))
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ROM_END
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COMP(1986, telex274, 0, 0, telex274, telex274, telex274_state, empty_init, "Telex Computer Products", "Telex 274-61C Sixteen Station Control Unit", MACHINE_IS_SKELETON)
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@ -37498,6 +37498,9 @@ tek4404 // (c) 1984 Tektronix
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@source:tekxp33x.cpp
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tekxp330 //
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@source:telex274.cpp
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telex274 //
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@source:tempest.cpp
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tempest // 136002 (c) 1980
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tempest1 // 136002 (c) 1980
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@ -773,6 +773,7 @@ tek405x.cpp
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tek410x.cpp
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tek440x.cpp
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tekxp33x.cpp
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telex274.cpp
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terak.cpp
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terco.cpp
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terminal.cpp
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