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video/pc_vga_paradise.cpp: fix boot regression with PVGA1A
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@ -77,9 +77,10 @@ void pvga1a_vga_device::device_reset()
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m_memory_size = 0;
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m_video_control = 0; // Really &= 0x8; at POR according to docs
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m_video_select = 0;
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m_ega_compatible = false;
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m_crtc_lock = 0;
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m_ext_gc_unlock = false;
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m_ext_gc_view.select(0);
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m_ext_gc_view.select(1);
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}
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uint8_t pvga1a_vga_device::mem_r(offs_t offset)
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@ -110,12 +111,28 @@ void pvga1a_vga_device::gc_map(address_map &map)
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LOGLOCKED("Attempt to R ext. GC register offset %02x while locked\n", offset + 9);
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return 0xff;
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})
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).unmapw();
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m_ext_gc_view[1](0x09, 0x0a).r(FUNC(pvga1a_vga_device::address_offset_r)).unmapw();
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m_ext_gc_view[1](0x0b, 0x0b).r(FUNC(pvga1a_vga_device::memory_size_r)).unmapw();
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m_ext_gc_view[1](0x0c, 0x0c).r(FUNC(pvga1a_vga_device::video_select_r)).unmapw();
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m_ext_gc_view[1](0x0d, 0x0d).r(FUNC(pvga1a_vga_device::crtc_lock_r)).unmapw();
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m_ext_gc_view[1](0x0e, 0x0e).r(FUNC(pvga1a_vga_device::video_control_r)).unmapw();
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m_ext_gc_view[2](0x09, 0x0e).lr8(
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NAME([this] (offs_t offset) {
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LOGLOCKED("Attempt to R ext. GC register offset %02x while locked\n", offset + 9);
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return 0xff;
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})
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);
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m_ext_gc_view[1](0x09, 0x0a).rw(FUNC(pvga1a_vga_device::address_offset_r), FUNC(pvga1a_vga_device::address_offset_w));
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m_ext_gc_view[1](0x0b, 0x0b).rw(FUNC(pvga1a_vga_device::memory_size_r), FUNC(pvga1a_vga_device::memory_size_w));
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m_ext_gc_view[1](0x0c, 0x0c).rw(FUNC(pvga1a_vga_device::video_select_r), FUNC(pvga1a_vga_device::video_select_w));
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m_ext_gc_view[1](0x0d, 0x0d).rw(FUNC(pvga1a_vga_device::crtc_lock_r), FUNC(pvga1a_vga_device::crtc_lock_w));
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m_ext_gc_view[1](0x0e, 0x0e).rw(FUNC(pvga1a_vga_device::video_control_r), FUNC(pvga1a_vga_device::video_control_w));
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m_ext_gc_view[2](0x09, 0x0a).w(FUNC(pvga1a_vga_device::address_offset_w));
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m_ext_gc_view[2](0x0b, 0x0b).w(FUNC(pvga1a_vga_device::memory_size_w));
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m_ext_gc_view[2](0x0c, 0x0c).w(FUNC(pvga1a_vga_device::video_select_w));
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m_ext_gc_view[2](0x0d, 0x0d).w(FUNC(pvga1a_vga_device::crtc_lock_w));
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m_ext_gc_view[2](0x0e, 0x0e).w(FUNC(pvga1a_vga_device::video_control_w));
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m_ext_gc_view[3](0x09, 0x0a).rw(FUNC(pvga1a_vga_device::address_offset_r), FUNC(pvga1a_vga_device::address_offset_w));
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m_ext_gc_view[3](0x0b, 0x0b).rw(FUNC(pvga1a_vga_device::memory_size_r), FUNC(pvga1a_vga_device::memory_size_w));
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m_ext_gc_view[3](0x0c, 0x0c).rw(FUNC(pvga1a_vga_device::video_select_r), FUNC(pvga1a_vga_device::video_select_w));
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m_ext_gc_view[3](0x0d, 0x0d).rw(FUNC(pvga1a_vga_device::crtc_lock_r), FUNC(pvga1a_vga_device::crtc_lock_w));
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m_ext_gc_view[3](0x0e, 0x0e).rw(FUNC(pvga1a_vga_device::video_control_r), FUNC(pvga1a_vga_device::video_control_w));
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map(0x0f, 0x0f).rw(FUNC(pvga1a_vga_device::ext_gc_status_r), FUNC(pvga1a_vga_device::ext_gc_unlock_w));
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}
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@ -225,7 +242,7 @@ u8 pvga1a_vga_device::crtc_lock_r(offs_t offset)
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void pvga1a_vga_device::crtc_lock_w(offs_t offset, u8 data)
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{
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LOG("PR3 CRTC lock W\n", data);
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LOG("PR3 CRTC lock W %02x\n", data);
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m_crtc_lock = data;
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}
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@ -252,6 +269,9 @@ void pvga1a_vga_device::video_control_w(offs_t offset, u8 data)
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LOG("PR4 Video Control W %02x\n", data);
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m_video_control = data;
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svga.rgb8_en = BIT(data, 0);
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m_ega_compatible = bool(BIT(data, 1));
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m_ext_gc_view.select(m_ext_gc_unlock << 1 | !m_ega_compatible);
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}
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/*
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@ -271,7 +291,7 @@ void pvga1a_vga_device::ext_gc_unlock_w(offs_t offset, u8 data)
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{
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m_ext_gc_unlock = (data & 0x7) == 5;
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LOGLOCKED("PR5 %s state (%02x)\n", m_ext_gc_unlock ? "unlock" : "lock", data);
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m_ext_gc_view.select(m_ext_gc_unlock);
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m_ext_gc_view.select(m_ext_gc_unlock << 1 | !m_ega_compatible);
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}
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/**************************************
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@ -45,6 +45,7 @@ private:
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u8 m_memory_size = 0;
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u8 m_video_control = 0;
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bool m_ext_gc_unlock = false;
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bool m_ega_compatible = false;
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};
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class wd90c00_vga_device : public pvga1a_vga_device
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