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https://github.com/holub/mame
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cps3.cpp: delay Palette/Character DMAs interrupt, get rid of periodic irq, more register docs
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MetalliC
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@ -17,18 +17,15 @@ To-Do/Issues:
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Street Fighter 3 2nd Impact uses flipped tilemaps during flashing, emulate this.
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Figure out proper IRQ10 generation:
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If we generate on DMA operations only then Warzard is OK, otherwise it hangs during attract
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HOWEVER, SFIII2 sometimes has messed up character profiles unless we also generate it periodically.
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I think the corrupt background on some of the lighting effects may be related to this + the DMA
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status flags.
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DMA ack IRQ10 generation:
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Character and Palette DMAs speed is unknown, needs to be measured.
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Alpha Blending Effects
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These are actually palette manipulation effects, not true blending. How the values are used is
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not currently 100% understood. They are incorrect if you use player 2 in Warzard
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Linezoom
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Is it used anywhere??
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Is it used in games? May be enabled in jojo/jojoba dev.menu BG test (P2 btn4)
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Palette DMA effects
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Verify them, they might not be 100% accurate at the moment
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@ -455,44 +452,91 @@ hardware modification to the security cart.....
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4. That is all. Enjoy your working PCB.
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Hardware register info
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Hardware registers info
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----------------------
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PPU CRTC registers (write only)
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0x040C0060 - 0x040C0081
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PPU registers (read only)
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0x040C0000 - 0x040C000D
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Offset: Bits: Desc: Values: 384 495 "wide"
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60 xxxx xxxx xxxx xxxx H Sync 42 35
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62 xxxx xxxx xxxx xxxx H Start 111 118
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64 xxxx xxxx xxxx xxxx H Blank 495 613
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66 xxxx xxxx xxxx xxxx H Total* 454 454
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68 ---- --xx xxxx xxxx H Zoom Master? 0 0 +128 if flip screen, might be not zoom-related but global H scroll
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6A xxxx xxxx xxxx xxxx H Zoom Offset? 0 0
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6C ---- --xx xxxx xxxx H Zoom Size? 1023 1023
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Offset: Bits: Desc:
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0C ---- ---- ---- -2-- Palette DMA active |
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---- ---- ---- --1- Character DMA active | several parts of game code assume only 1 of these might be active at the same time
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---- ---- ---- ---0 Sprite list DMA/copy active, see register 82 description
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PPU registers (write only)
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0x040C0000 - 0x040C00AF
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Offset: Bits: Desc:
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00 ---- --xx xxxx xxxx Global Scroll 0 X
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02 ---- --xx xxxx xxxx Global Scroll 0 Y
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04-1F Global Scrolls 1-7
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20 xxxx xxxx xxxx xxxx Tilemap 0 Scroll X
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22 xxxx xxxx xxxx xxxx Tilemap 0 Scroll Y
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24 xxxx xxxx xxxx xxxx Tilemap 0 ??
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26 f--- ---- ---- ---- Tilemap 0 Enable
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-e-- ---- ---- ---- Tilemap 0 Line Scroll Enable
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--dc ---- ---- ---- Tilemap 0 Line Zoom Enable? (seems unused in games, but might be enabled in jojo dev.menu BG test)
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---- b--- ---- ---- Tilemap 0 ? Flip X (Warzard demo fights during special moves)
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---- -a-- ---- ---- Tilemap 0 Flip Y (not implemented, Capcom logos background during sfiii2 flashing)
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28 -edc ba98 ---- ---- Tilemap 0 Line Scroll and Zoom Base address (1st word is scroll, 2nd word is zoom)
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---- ---- -654 3210 Tilemap 0 Tiles Base address
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2A unused ? always 0
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2C unused ? always 0
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2E unused ? always 0
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30-5F Tilemaps 1-3
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Values: 384 495 "wide"
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60 xxxx xxxx xxxx xxxx H Sync end* 42 35
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62 xxxx xxxx xxxx xxxx H Blank end 111 118
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64 xxxx xxxx xxxx xxxx H Screen end 495 613
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66 xxxx xxxx xxxx xxxx H Total end* 454 454
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68 ---- --xx xxxx xxxx H ?? Zoom Master? 0 0 +128 if flip screen, might be not zoom-related but global H scroll
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6A xxxx xxxx xxxx xxxx H ?? Zoom Offset? 0 0
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6C xxxx xxxx xxxx xxxx H ?? Zoom Size? 1023 1023 (511 at BIOS init)
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6E xxxx xxxx xxxx xxxx H Zoom Scale 64 64
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70 xxxx xxxx xxxx xxxx V Sync 3 3
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72 xxxx xxxx xxxx xxxx V Start 21 21
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74 xxxx xxxx xxxx xxxx V Blank 245 245
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76 xxxx xxxx xxxx xxxx V Total 262 262
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78 ---- --xx xxxx xxxx V Zoom Master? 0 0 might be not zoom-related but global V scroll
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7A xxxx xxxx xxxx xxxx V Zoom Offset? 0 0
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7C ---- --xx xxxx xxxx V Zoom Size? 1023 1023
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70 xxxx xxxx xxxx xxxx V Sync end 3 3
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72 xxxx xxxx xxxx xxxx V Blank end 21 21
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74 xxxx xxxx xxxx xxxx V Screen end 245 245
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76 xxxx xxxx xxxx xxxx V Total end 262 262
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78 ---- --xx xxxx xxxx V ?? Zoom Master? 0 0 might be not zoom-related but global V scroll
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7A xxxx xxxx xxxx xxxx V ?? Zoom Offset? 0 0
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7C xxxx xxxx xxxx xxxx V ?? Zoom Size? 1023 1023 (261 at BIOS init)
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7E xxxx xxxx xxxx xxxx V Zoom Scale 64 64
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80 ---- ---- ---- -210 Pixel clock 3 5 not clear how it works, which OSC is base clock, etc.
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---- ---- ---4 3--- Flip screen X/Y (or Y/X)
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---- ---- -65- ---- ?? always 11, 00 in unused 24KHz mode (pixel clock divider?)
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f--- ---- ---- ---- ?? always 0, but there is code which may set it (display disable?)
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---- ---- --5- ---- ?? always set to 1, 0 in unused 24KHz mode (pixel clock divider?)
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---- ---- -6-- ---- ?? set to 0 by BIOS init, then set to 1 after video mode selection, 0 in unused 24KHz mode (pixel clock divider?)
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f--- ---- ---- ---- ?? always 0, but there is code which may set it
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82 ---- ---- ---- 3--0 Sprite list DMA/copy to onchip RAM ? after new list upload to sprite RAM games write here 8/9/8/9 pattern, then wait until register 0C bit 0 became 0, then write 0.
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84 ---- b--- ---- ---- ?? always set to 0x0800
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86 ---- ---- ---- 3210 Character RAM bank
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88 ---- ---- --54 3210 Gfx flash ROM bank
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8A ---- ---- ---- ---- ?? set to 0 by BIOS init, never writen later
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8E ---- ---- 7-5- ---- ?? set to 0x00A0 by BIOS init after Pal/Char DMA registers, never writen later (Char/Pal DMA IRQ enable ?)
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96 xxxx xxxx xxxx xxxx Character DMA Source low bits
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98 ---- ---- --54 3210 Character DMA Source high bits
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---- ---- -6-- ---- Character DMA Start
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A0 ---- -a98 7654 3210 Palette DMA Source high bits
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A2 xxxx xxxx xxxx xxxx Palette DMA Source low bits
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A4 ---- ---- ---- ---0 Palette DMA Destination high bit
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A6 xxxx xxxx xxxx xxxx Palette DMA Destination low bits
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A8 -edc ba98 -654 3210 Palette DMA Fade low bits
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AA ---- ---- -654 3210 Palette DMA Fade high bits
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AC xxxx xxxx xxxx xxxx Palette DMA Lenght low bits
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AE ---- ---- ---- ---0 Palette DMA Lenght high bit
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---- ---- ---- --1- Palette DMA Start
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(*) H Total value is same for all 15KHz modes, probably uses fixed clock (not affected by pixel clock modifier),
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perhaps 42.9545MHz/6 ? (/454 = 15768.9Hz /262 = 60.186Hz ?)
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unused 24KHz 512x384 mode uses H Total 293 V Total 424 (42.9545MHz/6 /293 = 24433.7Hz /424 = 57.63Hz ?)
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All CRTC-related values is last clock/line of given area, i.e. actual sizes is +1 to value.
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(*) H Total value is same for all 15KHz modes, uses fixed clock (not affected by pixel clock modifier),
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probably 42.954545MHz/6 (similar to SSV) /(454+1) = 15734.25Hz /(262+1) = 59.826Hz
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unused 24KHz 512x384 mode uses H Total 293 V Total 424 (42.954545MHz/6 /(293+1) = 24350.62Hz /(424+1) = 57.29Hz)
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'SS' foreground tilemap layer generator (presumable located in 'SSU' chip) registers (write only?)
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0x05050000 - 0x05050029 area, even bytes only.
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Offset: Bits: Desc: Values: 384 495 "wide"
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00 xxxx xxxx H Sync 42 35 same as PPU
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00 xxxx xxxx H Sync* 42 35 same as PPU
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01 xxxx xxxx H Start L
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02 xxxx xxxx H Start H 62 64
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03 xxxx xxxx H Blank L
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@ -1656,14 +1700,9 @@ WRITE32_MEMBER(cps3_state::cram_gfxflash_bank_w)
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}
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}
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READ16_MEMBER(cps3_state::gpu_status_r)
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READ16_MEMBER(cps3_state::dma_status_r)
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{
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// 40c000c GPU DMA? status register
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// -------- -----2-- Palette DMA? active |
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// -------- ------1- Character DMA? active | it seems only 1 of these might be active at the same time
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// -------- -------0 Sprite DMA active ? games wait it to be 0 after 8/9/8/9/8/9 sequence write to 40C0082 register
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// it is also possible these bits is not DMA-related but HBLANK/VBLANK/etc statuses.
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return 0x0000;
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return m_dma_status;
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}
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READ16_MEMBER(cps3_state::dev_dipsw_r)
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@ -1807,7 +1846,8 @@ WRITE32_MEMBER(cps3_state::palettedma_w)
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set_mame_colours((m_paldma_dest+i)^1, coldata, m_paldma_fade);
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}
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m_maincpu->set_input_line(10, ASSERT_LINE);
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m_dma_status |= 4;
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m_dma_timer->adjust(attotime::from_usec(100)); // delay time is a hack, what is actual DMA speed?
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}
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}
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}
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@ -2023,7 +2063,8 @@ void cps3_state::process_character_dma(u32 address)
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break;
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}
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}
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m_maincpu->set_input_line(10, ASSERT_LINE);
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m_dma_status |= 2;
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m_dma_timer->adjust(attotime::from_usec(100)); // delay time is a hack, what is actual DMA speed?
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}
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WRITE32_MEMBER(cps3_state::characterdma_w)
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@ -2094,13 +2135,13 @@ void cps3_state::cps3_map(address_map &map)
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{
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map(0x00000000, 0x0007ffff).rom().region("bios", 0); // Bios ROM
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map(0x02000000, 0x0207ffff).ram().share("mainram"); // Main RAM
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map(0x03000000, 0x030003ff).ram(); // 'FRAM' (SFIII memory test mode ONLY, and only odd bytes)
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map(0x03000000, 0x030003ff).ram(); // 'FRAM' (sfiii and warzard memory test mode ONLY, and only odd bytes)
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map(0x04000000, 0x0407ffff).ram().share("spriteram"); // Sprite RAM
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map(0x04080000, 0x040bffff).rw(FUNC(cps3_state::colourram_r), FUNC(cps3_state::colourram_w)).share("colourram"); // Colour RAM 0x20000 colours
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// PPU registers
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map(0x040c0000, 0x040c0007).nopr(); // ?? warzard reads this but not use values, dev/debug leftovers ?
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map(0x040c000c, 0x040c000d).r(FUNC(cps3_state::gpu_status_r));
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map(0x040c000c, 0x040c000d).r(FUNC(cps3_state::dma_status_r));
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map(0x040c0000, 0x040c001f).w(FUNC(cps3_state::ppu_gscroll_w));
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map(0x040c0020, 0x040c002b).writeonly().share("tmap20_regs");
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@ -2225,11 +2266,10 @@ WRITE_LINE_MEMBER(cps3_state::vbl_interrupt)
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m_maincpu->set_input_line(12, ASSERT_LINE);
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}
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// this seems to need to be periodic (see the life bar portraits in sfiii2
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// but also triggered on certain dma events (or warzard locks up in attract)
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// what is the REAL source of IRQ10??
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INTERRUPT_GEN_MEMBER(cps3_state::irq10_periodic)
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// Test cases: character portraits screen after character select in sfiii2, warzard attract title.
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TIMER_DEVICE_CALLBACK_MEMBER(cps3_state::dma_interrupt)
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{
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m_dma_status &= ~6;
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m_maincpu->set_input_line(10, ASSERT_LINE);
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}
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@ -2454,7 +2494,6 @@ void cps3_state::cps3(machine_config &config)
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SH2(config, m_maincpu, 6250000*4); // external clock is 6.25 Mhz, it sets the internal multiplier to 4x (this should probably be handled in the core..)
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m_maincpu->set_addrmap(AS_PROGRAM, &cps3_state::cps3_map);
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m_maincpu->set_addrmap(AS_OPCODES, &cps3_state::decrypted_opcodes_map);
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m_maincpu->set_periodic_int(FUNC(cps3_state::irq10_periodic), attotime::from_hz(80)); /* ?source? */
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m_maincpu->set_dma_kludge_callback(FUNC(cps3_state::dma_callback));
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NSCSI_BUS(config, "scsi");
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@ -2466,7 +2505,7 @@ void cps3_state::cps3(machine_config &config)
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screen.set_raw(XTAL(60'000'000)/8, 486, 0, 384, 259, 0, 224);
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screen.set_screen_update(FUNC(cps3_state::screen_update));
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screen.screen_vblank().set(FUNC(cps3_state::vbl_interrupt));
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/*
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/*
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Measured clocks:
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V = 59.5992Hz
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H = 15.4335kHz
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@ -2477,6 +2516,8 @@ void cps3_state::cps3(machine_config &config)
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42.9545MHz / 15.4445kHz = 2781.217 / 6 = 463.536 -> unlikely
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*/
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TIMER(config, m_dma_timer).configure_generic(FUNC(cps3_state::dma_interrupt));
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NVRAM(config, "eeprom", nvram_device::DEFAULT_ALL_0);
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PALETTE(config, m_palette).set_entries(0x10000); // actually 0x20000 ...
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@ -14,6 +14,7 @@
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#include "machine/intelfsh.h"
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#include "cpu/sh/sh2.h"
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#include "audio/cps3.h"
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#include "machine/timer.h"
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#include "emupal.h"
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@ -26,6 +27,7 @@ public:
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, m_gfxdecode(*this, "gfxdecode")
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, m_palette(*this, "palette")
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, m_cps3sound(*this, "cps3sound")
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, m_dma_timer(*this, "dma_timer")
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, m_simm{{*this, "simm1.%u", 0U},
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{*this, "simm2.%u", 0U},
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{*this, "simm3.%u", 0U},
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@ -85,6 +87,7 @@ protected:
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required_device<gfxdecode_device> m_gfxdecode;
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required_device<palette_device> m_palette;
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required_device<cps3_sound_device> m_cps3sound;
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required_device<timer_device> m_dma_timer;
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optional_device_array<fujitsu_29f016a_device, 8> m_simm[7];
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required_shared_ptr<u32> m_mainram;
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@ -119,6 +122,7 @@ private:
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u32 m_key1;
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u32 m_key2;
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int m_altEncryption;
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u16 m_dma_status;
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u32 m_cram_bank;
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u16 m_current_eeprom_read;
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u32 m_paldma_source;
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@ -149,7 +153,7 @@ private:
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DECLARE_WRITE32_MEMBER(flash1_w);
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DECLARE_WRITE32_MEMBER(flash2_w);
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DECLARE_WRITE32_MEMBER(cram_gfxflash_bank_w);
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DECLARE_READ16_MEMBER(gpu_status_r);
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DECLARE_READ16_MEMBER(dma_status_r);
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DECLARE_READ16_MEMBER(dev_dipsw_r);
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DECLARE_READ32_MEMBER(eeprom_r);
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DECLARE_WRITE32_MEMBER(eeprom_w);
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@ -163,7 +167,7 @@ private:
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void draw_fg_layer(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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u32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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WRITE_LINE_MEMBER(vbl_interrupt);
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INTERRUPT_GEN_MEMBER(irq10_periodic);
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TIMER_DEVICE_CALLBACK_MEMBER(dma_interrupt);
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u16 rotate_left(u16 value, int n);
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u16 rotxor(u16 val, u16 xorval);
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u32 cps3_mask(u32 address, u32 key1, u32 key2);
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