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https://github.com/holub/mame
synced 2025-04-24 01:11:11 +03:00
ngen: mapped DMA controller, no idea what DMA channels map to what devices, yet.
This commit is contained in:
mahlemiut
parent
056dced923
commit
04caecd693
@ -41,6 +41,13 @@ public:
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DECLARE_READ16_MEMBER(peripheral_r);
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DECLARE_WRITE16_MEMBER(port00_w);
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DECLARE_READ16_MEMBER(port00_r);
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DECLARE_WRITE_LINE_MEMBER(dma_hrq_changed);
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DECLARE_WRITE_LINE_MEMBER(dack0_w);
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DECLARE_WRITE_LINE_MEMBER(dack1_w);
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DECLARE_WRITE_LINE_MEMBER(dack2_w);
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DECLARE_WRITE_LINE_MEMBER(dack3_w);
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DECLARE_READ8_MEMBER(dma_read_byte);
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DECLARE_WRITE8_MEMBER(dma_write_byte);
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MC6845_UPDATE_ROW(crtc_update_row);
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protected:
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@ -55,11 +62,15 @@ private:
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optional_shared_ptr<UINT16> m_vram;
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optional_shared_ptr<UINT16> m_fontram;
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void set_dma_channel(int channel, int state);
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UINT16 m_peripheral;
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UINT16 m_upper;
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UINT16 m_middle;
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UINT16 m_port00;
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UINT16 m_periph141;
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UINT8 m_dma_offset[4];
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INT8 m_dma_channel;
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};
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WRITE_LINE_MEMBER(ngen_state::pit_out0_w)
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@ -117,6 +128,33 @@ WRITE16_MEMBER(ngen_state::peripheral_w)
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{
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switch(offset)
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{
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case 0x00:
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case 0x01:
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case 0x02:
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case 0x03:
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case 0x04:
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case 0x05:
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case 0x06:
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case 0x07:
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case 0x08:
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case 0x09:
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case 0x0a:
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case 0x0b:
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case 0x0c:
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case 0x0d:
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case 0x0e:
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case 0x0f:
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if(mem_mask & 0x00ff)
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m_dmac->write(space,offset,data & 0xff);
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//logerror("(PC=%06x) DMA write offset %04x data %04x mask %04x\n",m_maincpu->device_t::safe_pc(),offset,data,mem_mask);
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break;
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case 0x80: // DMA page offset?
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case 0x81:
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case 0x82:
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case 0x83:
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if(mem_mask & 0x00ff)
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m_dma_offset[offset-0x80] = data & 0xff;
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break;
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case 0x110:
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if(mem_mask & 0x00ff)
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m_pit->write(space,0,data & 0x0ff);
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@ -151,6 +189,9 @@ WRITE16_MEMBER(ngen_state::peripheral_w)
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case 0x147:
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//logerror("Video write offset 0x147 data %04x mask %04x\n",data,mem_mask);
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break;
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case 0x1a0: // serial?
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logerror("(PC=%06x) Serial(?) 0x1a0 write offset %04x data %04x mask %04x\n",m_maincpu->device_t::safe_pc(),offset,data,mem_mask);
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break;
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default:
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logerror("(PC=%06x) Unknown 80186 peripheral write offset %04x data %04x mask %04x\n",m_maincpu->device_t::safe_pc(),offset,data,mem_mask);
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}
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@ -161,6 +202,33 @@ READ16_MEMBER(ngen_state::peripheral_r)
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UINT16 ret = 0xffff;
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switch(offset)
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{
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case 0x00:
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case 0x01:
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case 0x02:
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case 0x03:
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case 0x04:
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case 0x05:
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case 0x06:
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case 0x07:
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case 0x08:
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case 0x09:
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case 0x0a:
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case 0x0b:
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case 0x0c:
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case 0x0d:
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case 0x0e:
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case 0x0f:
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if(mem_mask & 0x00ff)
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ret = m_dmac->read(space,offset);
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logerror("(PC=%06x) DMA read offset %04x mask %04x returning %04x\n",m_maincpu->device_t::safe_pc(),offset,mem_mask,ret);
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break;
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case 0x80: // DMA page offset?
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case 0x81:
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case 0x82:
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case 0x83:
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if(mem_mask & 0x00ff)
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ret = m_dma_offset[offset-0x80] & 0xff;
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break;
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case 0x110:
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if(mem_mask & 0x00ff)
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ret = m_pit->read(space,0);
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@ -189,15 +257,20 @@ READ16_MEMBER(ngen_state::peripheral_r)
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ret = m_crtc->register_r(space,0);
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break;
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case 0x146:
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if(mem_mask & 0x00ff)
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ret = m_iouart->ba_cd_r(space,0);
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break;
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case 0x147: // definitely video related, likely UART sending data to the video board
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if(mem_mask & 0x00ff)
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ret = m_iouart->ba_cd_r(space,1);
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case 0x147: // definitely video related, maybe UART sending data to the monitor?
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// expects bit 0 to be set (Video ready signal?)
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ret = 0;
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ret |= 1;
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break;
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case 0x1a0: // status?
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ret = 0;
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ret |= 0x02; // end of DMA transfer?
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break;
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case 0x1b1:
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ret = 0;
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ret |= 0x02; // also checked after DMA transfer ends
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break;
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default:
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logerror("(PC=%06x) Unknown 80186 peripheral read offset %04x mask %04x returning %04x\n",m_maincpu->device_t::safe_pc(),offset,mem_mask,ret);
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}
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@ -220,6 +293,51 @@ READ16_MEMBER(ngen_state::port00_r)
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return m_port00;
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}
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WRITE_LINE_MEMBER( ngen_state::dma_hrq_changed )
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{
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m_maincpu->set_input_line(INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
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}
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void ngen_state::set_dma_channel(int channel, int state)
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{
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if(!state)
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m_dma_channel = channel;
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else if(m_dma_channel == channel)
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m_dma_channel = -1;
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}
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WRITE_LINE_MEMBER( ngen_state::dack0_w ) { set_dma_channel(0, state); }
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WRITE_LINE_MEMBER( ngen_state::dack1_w ) { set_dma_channel(1, state); }
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WRITE_LINE_MEMBER( ngen_state::dack2_w ) { set_dma_channel(2, state); }
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WRITE_LINE_MEMBER( ngen_state::dack3_w ) { set_dma_channel(3, state); }
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READ8_MEMBER(ngen_state::dma_read_byte)
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{
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address_space& prog_space = m_maincpu->space(AS_PROGRAM); // get the right address space
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UINT8 result;
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if(m_dma_channel == -1)
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return 0xff;
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offs_t page_offset = (((offs_t) m_dma_offset[m_dma_channel]) << 16) & 0xFF0000;
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result = prog_space.read_byte(page_offset + offset);
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popmessage("DMA byte address %06x read %02x\n",page_offset+offset,result);
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return result;
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}
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WRITE8_MEMBER(ngen_state::dma_write_byte)
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{
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address_space& prog_space = m_maincpu->space(AS_PROGRAM); // get the right address space
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if(m_dma_channel == -1)
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return;
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offs_t page_offset = (((offs_t) m_dma_offset[m_dma_channel]) << 16) & 0xFF0000;
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prog_space.write_byte(page_offset + offset, data);
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popmessage("DMA byte address %06x write %02x\n",page_offset+offset,data);
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}
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MC6845_UPDATE_ROW( ngen_state::crtc_update_row )
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{
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UINT16 addr = ma;
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@ -286,9 +404,16 @@ static MACHINE_CONFIG_START( ngen, ngen_state )
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MCFG_PIT8253_OUT2_HANDLER(WRITELINE(ngen_state, pit_out2_w))
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MCFG_DEVICE_ADD("dmac", AM9517A, XTAL_14_7456MHz / 3) // NEC D8237A, divisor unknown
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MCFG_I8237_OUT_HREQ_CB(WRITELINE(ngen_state, dma_hrq_changed))
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MCFG_I8237_IN_MEMR_CB(READ8(ngen_state, dma_read_byte))
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MCFG_I8237_OUT_MEMW_CB(WRITE8(ngen_state, dma_write_byte))
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MCFG_I8237_OUT_DACK_0_CB(WRITELINE(ngen_state, dack0_w))
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MCFG_I8237_OUT_DACK_1_CB(WRITELINE(ngen_state, dack1_w))
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MCFG_I8237_OUT_DACK_2_CB(WRITELINE(ngen_state, dack2_w))
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MCFG_I8237_OUT_DACK_3_CB(WRITELINE(ngen_state, dack3_w))
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// I/O board
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MCFG_UPD7201_ADD("iouart",0, 0,0,0,0) // clocked by PIT channel 2?
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MCFG_UPD7201_ADD("iouart",0,0,0,0,0) // clocked by PIT channel 2?
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MCFG_Z80DART_OUT_TXDA_CB(DEVWRITELINE("rs232_a", rs232_port_device, write_txd))
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MCFG_Z80DART_OUT_TXDB_CB(DEVWRITELINE("rs232_b", rs232_port_device, write_txd))
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MCFG_Z80DART_OUT_DTRA_CB(DEVWRITELINE("rs232_a", rs232_port_device, write_dtr))
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