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(MESS) tandy2k: WIP. (nw)
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Curt Coder
parent
a71569d7df
commit
054e578985
@ -398,16 +398,15 @@ inline void crt9007_t::update_dma_timer()
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inline void crt9007_t::recompute_parameters()
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{
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#ifdef UNUSED_FOR_NOW
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// check that necessary registers have been loaded
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if (!HAS_VALID_PARAMETERS) return;
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// screen dimensions
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int horiz_pix_total = CHARACTERS_PER_HORIZONTAL_PERIOD * m_hpixels_per_column;
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int vert_pix_total = SCAN_LINES_PER_FRAME;
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//int horiz_pix_total = CHARACTERS_PER_HORIZONTAL_PERIOD * m_hpixels_per_column;
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//int vert_pix_total = SCAN_LINES_PER_FRAME;
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// refresh rate
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attoseconds_t refresh = HZ_TO_ATTOSECONDS(clock()) * horiz_pix_total * vert_pix_total;
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//attoseconds_t refresh = HZ_TO_ATTOSECONDS(clock()) * horiz_pix_total * vert_pix_total;
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// horizontal sync
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m_hsync_start = 0;
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@ -426,23 +425,22 @@ inline void crt9007_t::recompute_parameters()
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m_vsync_end = VERTICAL_SYNC_WIDTH;
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// visible area
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rectangle visarea;
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//rectangle visarea;
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visarea.set(m_hsync_end, horiz_pix_total - 1, m_vsync_end, vert_pix_total - 1);
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//visarea.set(m_hsync_end, horiz_pix_total - 1, m_vsync_end, vert_pix_total - 1);
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if (LOG)
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{
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logerror("CRT9007 '%s' Screen: %u x %u @ %f Hz\n", tag(), horiz_pix_total, vert_pix_total, 1 / ATTOSECONDS_TO_DOUBLE(refresh));
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logerror("CRT9007 '%s' Visible Area: (%u, %u) - (%u, %u)\n", tag(), visarea.min_x, visarea.min_y, visarea.max_x, visarea.max_y);
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}
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//if (LOG)
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//{
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// logerror("CRT9007 '%s' Screen: %u x %u @ %f Hz\n", tag(), horiz_pix_total, vert_pix_total, 1 / ATTOSECONDS_TO_DOUBLE(refresh));
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// logerror("CRT9007 '%s' Visible Area: (%u, %u) - (%u, %u)\n", tag(), visarea.min_x, visarea.min_y, visarea.max_x, visarea.max_y);
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//}
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m_screen->configure(horiz_pix_total, vert_pix_total, visarea, refresh);
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//m_screen->configure(horiz_pix_total, vert_pix_total, visarea, refresh);
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m_hsync_timer->adjust(m_screen->time_until_pos(0, 0));
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m_vsync_timer->adjust(m_screen->time_until_pos(0, 0));
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m_vlt_timer->adjust(m_screen->time_until_pos(0, m_vlt_start), 1);
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m_drb_timer->adjust(m_screen->time_until_pos(0, 0));
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#endif
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}
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@ -13,7 +13,6 @@
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- floppy
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- HDL is also connected to WP/TS input where TS is used to detect motor status
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- 3 second motor off delay timer
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- DMA
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- video (video RAM is at memory top - 0x1400, i.e. 0x1ec00)
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- keyboard ROM
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- hires graphics board
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@ -25,6 +24,8 @@
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#include "includes/tandy2k.h"
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#define LOG 1
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// Read/Write Handlers
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void tandy2k_state::update_drq()
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@ -50,6 +51,7 @@ void tandy2k_state::update_drq()
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void tandy2k_state::dma_request(int line, int state)
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{
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m_busdmarq[line] = state;
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update_drq();
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}
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@ -119,8 +121,8 @@ WRITE8_MEMBER( tandy2k_state::enable_w )
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0 KBEN keyboard enable
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1 EXTCLK external baud rate clock
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2 SPKRGATE enable periodic m_speaker output
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3 SPKRDATA direct output to m_speaker
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2 SPKRGATE enable periodic speaker output
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3 SPKRDATA direct output to speaker
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4 RFRQGATE enable refresh and baud rate clocks
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5 FDCRESET* reset 8272
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6 TMRIN0 enable 80186 timer 0
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@ -128,16 +130,18 @@ WRITE8_MEMBER( tandy2k_state::enable_w )
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*/
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if (LOG) logerror("ENABLE %02x\n", data);
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// keyboard enable
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m_kb->power_w(BIT(data, 0));
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// external baud rate clock
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m_extclk = BIT(data, 1);
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// m_speaker gate
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// speaker gate
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m_pit->write_gate0(BIT(data, 2));
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// m_speaker data
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// speaker data
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m_spkrdata = BIT(data, 3);
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speaker_update();
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@ -146,8 +150,10 @@ WRITE8_MEMBER( tandy2k_state::enable_w )
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m_pit->write_gate2(BIT(data, 4));
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// FDC reset
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if(!BIT(data, 5))
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if (!BIT(data, 5))
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{
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m_fdc->reset();
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}
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// timer 0 enable
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m_maincpu->tmrin0_w(BIT(data, 6));
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@ -173,6 +179,8 @@ WRITE8_MEMBER( tandy2k_state::dma_mux_w )
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*/
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if (LOG) logerror("DMA MUX %02x\n", data);
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m_dma_mux = data;
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// check for DMA error
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@ -228,6 +236,8 @@ WRITE16_MEMBER( tandy2k_state::vpac_w )
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READ8_MEMBER( tandy2k_state::fldtc_r )
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{
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if (LOG) logerror("FLDTC\n");
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fldtc_w(space, 0, 0);
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return 0;
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@ -256,6 +266,8 @@ WRITE8_MEMBER( tandy2k_state::addr_ctrl_w )
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*/
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if (LOG) logerror("Address Control %02x\n", data);
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// video access
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m_vram_base = data & 0x1f;
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@ -281,8 +293,6 @@ WRITE8_MEMBER( tandy2k_state::addr_ctrl_w )
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// video source select
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m_vidouts = BIT(data, 7);
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logerror("Address Control %02x\n", data);
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}
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// Memory Maps
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@ -297,17 +307,17 @@ ADDRESS_MAP_END
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static ADDRESS_MAP_START( tandy2k_io, AS_IO, 16, tandy2k_state )
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ADDRESS_MAP_UNMAP_HIGH
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AM_RANGE(0x00000, 0x00001) AM_READWRITE8(enable_r, enable_w, 0x00ff)
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AM_RANGE(0x00002, 0x00003) AM_WRITE8(dma_mux_w, 0x00ff)
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AM_RANGE(0x00004, 0x00005) AM_READWRITE8(fldtc_r, fldtc_w, 0x00ff)
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AM_RANGE(0x00010, 0x00013) AM_DEVREADWRITE8(I8251A_TAG, i8251_device, data_r, data_w, 0x00ff)
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AM_RANGE(0x00030, 0x00033) AM_DEVICE8(I8272A_TAG, i8272a_device, map, 0x00ff)
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AM_RANGE(0x00040, 0x00047) AM_DEVREADWRITE8(I8253_TAG, pit8253_device, read, write, 0x00ff)
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AM_RANGE(0x00052, 0x00053) AM_READ8(kbint_clr_r, 0x00ff)
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AM_RANGE(0x00050, 0x00057) AM_DEVREADWRITE8(I8255A_TAG, i8255_device, read, write, 0x00ff)
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AM_RANGE(0x00060, 0x00063) AM_DEVREADWRITE8(I8259A_0_TAG, pic8259_device, read, write, 0x00ff)
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AM_RANGE(0x00070, 0x00073) AM_DEVREADWRITE8(I8259A_1_TAG, pic8259_device, read, write, 0x00ff)
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AM_RANGE(0x00080, 0x00081) AM_DEVREADWRITE8(I8272A_TAG, i8272a_device, mdma_r, mdma_w, 0x00ff)
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AM_RANGE(0x00000, 0x00001) AM_MIRROR(0x8) AM_READWRITE8(enable_r, enable_w, 0x00ff)
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AM_RANGE(0x00002, 0x00003) AM_MIRROR(0x8) AM_WRITE8(dma_mux_w, 0x00ff)
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AM_RANGE(0x00004, 0x00005) AM_MIRROR(0x8) AM_READWRITE8(fldtc_r, fldtc_w, 0x00ff)
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AM_RANGE(0x00010, 0x00013) AM_MIRROR(0xc) AM_DEVREADWRITE8(I8251A_TAG, i8251_device, data_r, data_w, 0x00ff)
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AM_RANGE(0x00030, 0x00033) AM_MIRROR(0xc) AM_DEVICE8(I8272A_TAG, i8272a_device, map, 0x00ff)
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AM_RANGE(0x00040, 0x00047) AM_MIRROR(0x8) AM_DEVREADWRITE8(I8253_TAG, pit8253_device, read, write, 0x00ff)
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AM_RANGE(0x00052, 0x00053) AM_MIRROR(0x8) AM_READ8(kbint_clr_r, 0x00ff)
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AM_RANGE(0x00050, 0x00057) AM_MIRROR(0x8) AM_DEVREADWRITE8(I8255A_TAG, i8255_device, read, write, 0x00ff)
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AM_RANGE(0x00060, 0x00063) AM_MIRROR(0xc) AM_DEVREADWRITE8(I8259A_0_TAG, pic8259_device, read, write, 0x00ff)
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AM_RANGE(0x00070, 0x00073) AM_MIRROR(0xc) AM_DEVREADWRITE8(I8259A_1_TAG, pic8259_device, read, write, 0x00ff)
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AM_RANGE(0x00080, 0x00081) AM_MIRROR(0xe) AM_DEVREADWRITE8(I8272A_TAG, i8272a_device, mdma_r, mdma_w, 0x00ff)
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// AM_RANGE(0x00100, 0x0017f) AM_DEVREADWRITE8(CRT9007_TAG, crt9007_t, read, write, 0x00ff) AM_WRITE8(addr_ctrl_w, 0xff00)
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AM_RANGE(0x00100, 0x0017f) AM_READWRITE(vpac_r, vpac_w)
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// AM_RANGE(0x00180, 0x00180) AM_READ8(hires_status_r, 0x00ff)
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@ -516,6 +526,7 @@ WRITE_LINE_MEMBER( tandy2k_state::intbrclk_w )
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WRITE_LINE_MEMBER( tandy2k_state::rfrqpulse_w )
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{
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// memory refresh counter up
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}
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// Intel 8255A Interface
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@ -786,7 +797,7 @@ static MACHINE_CONFIG_START( tandy2k, tandy2k_state )
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MCFG_DEVICE_ADD(CRT9021B_TAG, CRT9021, XTAL_16MHz*28/20)
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MCFG_VIDEO_SET_SCREEN(SCREEN_TAG)
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MCFG_TIMER_DRIVER_ADD_PERIODIC("vidldsh", tandy2k_state, vidldsh_tick, attotime::from_hz(XTAL_16MHz*28/20/8))
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MCFG_TIMER_DRIVER_ADD("vidldsh", tandy2k_state, vidldsh_tick)
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// sound hardware
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MCFG_SPEAKER_STANDARD_MONO("mono")
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@ -806,14 +817,16 @@ static MACHINE_CONFIG_START( tandy2k, tandy2k_state )
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MCFG_RS232_PORT_ADD(RS232_TAG, default_rs232_devices, NULL)
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MCFG_RS232_RXD_HANDLER(DEVWRITELINE(I8251A_TAG, i8251_device, write_rxd))
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MCFG_RS232_DSR_HANDLER(DEVWRITELINE(I8251A_TAG, i8251_device, write_dsr))
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// TODO pin 15 external transmit clock
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// TODO pin 17 external receiver clock
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MCFG_DEVICE_ADD(I8253_TAG, PIT8253, 0)
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MCFG_PIT8253_CLK0(XTAL_16MHz/16)
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MCFG_PIT8253_OUT0_HANDLER(WRITELINE(tandy2k_state, outspkr_w))
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MCFG_PIT8253_CLK1(XTAL_16MHz/8)
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MCFG_PIT8253_OUT1_HANDLER(WRITELINE(tandy2k_state, intbrclk_w))
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MCFG_PIT8253_CLK2(XTAL_16MHz/8)
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MCFG_PIT8253_OUT2_HANDLER(WRITELINE(tandy2k_state, rfrqpulse_w))
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//MCFG_PIT8253_CLK2(XTAL_16MHz/8)
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//MCFG_PIT8253_OUT2_HANDLER(WRITELINE(tandy2k_state, rfrqpulse_w))
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MCFG_PIC8259_ADD(I8259A_0_TAG, DEVWRITELINE(I80186_TAG, i80186_cpu_device, int0_w), VCC, NULL)
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@ -76,8 +76,8 @@ public:
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m_pb_sel(0),
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m_vram_base(0),
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m_vidouts(0),
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m_clkspd(0),
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m_clkcnt(0),
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m_clkspd(-1),
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m_clkcnt(-1),
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m_blc(0),
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m_bkc(0),
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m_cblank(0),
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