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z80dart: Merged in uPD7201 and modernized the interface. [Curt Coder]

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This commit is contained in:
Curt Coder 2013-05-27 14:02:08 +00:00
parent f79944e6c6
commit 0584bb9d5a
36 changed files with 399 additions and 805 deletions
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2
.gitattributes vendored
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@ -1430,8 +1430,6 @@ src/emu/machine/upd4701.c svneol=native#text/plain
src/emu/machine/upd4701.h svneol=native#text/plain
src/emu/machine/upd7002.c svneol=native#text/plain
src/emu/machine/upd7002.h svneol=native#text/plain
src/emu/machine/upd7201.c svneol=native#text/plain
src/emu/machine/upd7201.h svneol=native#text/plain
src/emu/machine/upd765.c svneol=native#text/plain
src/emu/machine/upd765.h svneol=native#text/plain
src/emu/machine/v3021.c svneol=native#text/plain

1
src/emu/emu.mak
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@ -292,7 +292,6 @@ EMUMACHINEOBJS = \
$(EMUMACHINE)/upd1990a.o \
$(EMUMACHINE)/upd4701.o \
$(EMUMACHINE)/upd7002.o \
$(EMUMACHINE)/upd7201.o \
$(EMUMACHINE)/upd765.o \
$(EMUMACHINE)/v3021.o \
$(EMUMACHINE)/wd_fdc.o \

331
src/emu/machine/upd7201.c
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@ -1,331 +0,0 @@
/**********************************************************************
NEC uPD7201 Multiprotocol Serial Communications Controller
Copyright MESS Team.
Visit http://mamedev.org for licensing and usage restrictions.
**********************************************************************/
/*
TODO:
- this is a clone of Intel 8274?
- everything
*/
#include "emu.h"
#include "upd7201.h"
// device type definition
const device_type UPD7201 = &device_creator<upd7201_device>;
//**************************************************************************
// MACROS / CONSTANTS
//**************************************************************************
#define LOG 0
enum
{
CHANNEL_A = 0,
CHANNEL_B
};
//**************************************************************************
// INLINE HELPERS
//**************************************************************************
//-------------------------------------------------
// receive -
//-------------------------------------------------
inline void upd7201_device::receive(int channel)
{
}
//-------------------------------------------------
// transmit -
//-------------------------------------------------
inline void upd7201_device::transmit(int channel)
{
}
//**************************************************************************
// LIVE DEVICE
//**************************************************************************
//-------------------------------------------------
// upd7201_device - constructor
//-------------------------------------------------
upd7201_device::upd7201_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: device_t(mconfig, UPD7201, "UPD7201", tag, owner, clock)
{
}
//-------------------------------------------------
// device_config_complete - perform any
// operations now that the configuration is
// complete
//-------------------------------------------------
void upd7201_device::device_config_complete()
{
// inherit a copy of the static data
const upd7201_interface *intf = reinterpret_cast<const upd7201_interface *>(static_config());
if (intf != NULL)
*static_cast<upd7201_interface *>(this) = *intf;
// or initialize to defaults if none provided
else
{
memset(&m_out_int_cb, 0, sizeof(m_out_int_cb));
}
}
//-------------------------------------------------
// device_start - device-specific startup
//-------------------------------------------------
void upd7201_device::device_start()
{
// resolve callbacks
m_out_int_func.resolve(m_out_int_cb, *this);
}
//-------------------------------------------------
// device_reset - device-specific reset
//-------------------------------------------------
void upd7201_device::device_reset()
{
}
//-------------------------------------------------
// device_timer - handler timer events
//-------------------------------------------------
void upd7201_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
{
switch (id)
{
case TIMER_RX_A:
receive(CHANNEL_A);
break;
case TIMER_TX_A:
transmit(CHANNEL_A);
break;
case TIMER_RX_B:
receive(CHANNEL_B);
break;
case TIMER_TX_B:
transmit(CHANNEL_B);
break;
}
}
//-------------------------------------------------
// cd_ba_r -
//-------------------------------------------------
READ8_MEMBER( upd7201_device::cd_ba_r )
{
return 0;
}
//-------------------------------------------------
// cd_ba_w -
//-------------------------------------------------
WRITE8_MEMBER( upd7201_device::cd_ba_w )
{
}
//-------------------------------------------------
// ba_cd_r -
//-------------------------------------------------
READ8_MEMBER( upd7201_device::ba_cd_r )
{
return 0;
}
//-------------------------------------------------
// ba_cd_w -
//-------------------------------------------------
WRITE8_MEMBER( upd7201_device::ba_cd_w )
{
}
//-------------------------------------------------
// intak_r -
//-------------------------------------------------
READ8_MEMBER( upd7201_device::intak_r )
{
return 0;
}
//-------------------------------------------------
// synca_w -
//-------------------------------------------------
WRITE_LINE_MEMBER( upd7201_device::synca_w )
{
}
//-------------------------------------------------
// syncb_w -
//-------------------------------------------------
WRITE_LINE_MEMBER( upd7201_device::syncb_w )
{
}
//-------------------------------------------------
// ctsa_w -
//-------------------------------------------------
WRITE_LINE_MEMBER( upd7201_device::ctsa_w )
{
}
//-------------------------------------------------
// ctsb_w -
//-------------------------------------------------
WRITE_LINE_MEMBER( upd7201_device::ctsb_w )
{
}
//-------------------------------------------------
// dtra_r -
//-------------------------------------------------
READ_LINE_MEMBER( upd7201_device::dtra_r )
{
return 0;
}
//-------------------------------------------------
// dtrb_r -
//-------------------------------------------------
READ_LINE_MEMBER( upd7201_device::dtrb_r )
{
return 0;
}
//-------------------------------------------------
// hai_w -
//-------------------------------------------------
WRITE_LINE_MEMBER( upd7201_device::hai_w )
{
}
//-------------------------------------------------
// rxda_w -
//-------------------------------------------------
WRITE_LINE_MEMBER( upd7201_device::rxda_w )
{
}
//-------------------------------------------------
// txda_r -
//-------------------------------------------------
READ_LINE_MEMBER( upd7201_device::txda_r )
{
return 0;
}
//-------------------------------------------------
// rxdb_w -
//-------------------------------------------------
WRITE_LINE_MEMBER( upd7201_device::rxdb_w )
{
}
//-------------------------------------------------
// txdb_r -
//-------------------------------------------------
READ_LINE_MEMBER( upd7201_device::txdb_r )
{
return 0;
}
//-------------------------------------------------
// rxca_w -
//-------------------------------------------------
WRITE_LINE_MEMBER( upd7201_device::rxca_w )
{
}
//-------------------------------------------------
// rxcb_w -
//-------------------------------------------------
WRITE_LINE_MEMBER( upd7201_device::rxcb_w )
{
}
//-------------------------------------------------
// txca_w -
//-------------------------------------------------
WRITE_LINE_MEMBER( upd7201_device::txca_w )
{
}
//-------------------------------------------------
// txcb_w -
//-------------------------------------------------
WRITE_LINE_MEMBER( upd7201_device::txcb_w )
{
}

151
src/emu/machine/upd7201.h
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@ -1,151 +0,0 @@
/**********************************************************************
NEC uPD7201 Multiprotocol Serial Communications Controller
Copyright MESS Team.
Visit http://mamedev.org for licensing and usage restrictions.
**********************************************************************
_____ _____
CLK 1 |* \_/ | 40 Vcc
_RESET 2 | | 39 _CTSA
_DCDA 3 | | 38 _RTSA
_RxCB 4 | | 37 TxDA
_DCDB 5 | | 36 _TxCA
_CTSB 6 | | 35 _RxCA
_TxCB 7 | | 34 RxDA
TxDB 8 | | 33 _SYNCA
RxDB 9 | | 32 _WAITA/DRQRxA
_RTSB/_SYNCB 10 | UPD7201 | 31 _DTRA/_HAO
_WAITB/_DRQTxA 11 | | 30 _PRO/DRQTxB
D7 12 | | 29 _PRI/DRQRxB
D6 13 | | 28 _INT
D5 14 | | 27 _INTAK
D4 15 | | 26 _DTRB/_HAI
D3 16 | | 25 B/_A
D2 17 | | 24 C/_D
D1 18 | | 23 _CS
D0 19 | | 22 _RD
Vss 20 |_____________| 21 _WR
**********************************************************************/
#pragma once
#ifndef __UPD7201__
#define __UPD7201__
#include "emu.h"
//**************************************************************************
// INTERFACE CONFIGURATION MACROS
//**************************************************************************
#define MCFG_UPD7201_ADD(_tag, _clock, _config) \
MCFG_DEVICE_ADD((_tag), UPD7201, _clock) \
MCFG_DEVICE_CONFIG(_config)
#define UPD7201_INTERFACE(name) \
const upd7201_interface (name) =
//**************************************************************************
// TYPE DEFINITIONS
//**************************************************************************
// ======================> upd7201_interface
struct upd7201_interface
{
devcb_write_line m_out_int_cb;
struct
{
int m_rx_clock;
int m_tx_clock;
devcb_write_line m_out_drqrx_cb;
devcb_write_line m_out_drqtx_cb;
devcb_read_line m_in_rxd_cb;
devcb_write_line m_out_txd_cb;
devcb_read_line m_in_cts_cb;
devcb_read_line m_in_dcd_cb;
devcb_write_line m_out_rts_cb;
devcb_write_line m_out_dtr_cb;
devcb_write_line m_out_wait_cb;
devcb_write_line m_out_sync_cb;
} m_channel[2];
};
// ======================> upd7201_device
class upd7201_device : public device_t,
public upd7201_interface
{
public:
// construction/destruction
upd7201_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
DECLARE_READ8_MEMBER( cd_ba_r );
DECLARE_WRITE8_MEMBER( cd_ba_w );
DECLARE_READ8_MEMBER( ba_cd_r );
DECLARE_WRITE8_MEMBER( ba_cd_w );
DECLARE_READ8_MEMBER( intak_r );
DECLARE_WRITE_LINE_MEMBER( synca_w );
DECLARE_WRITE_LINE_MEMBER( syncb_w );
DECLARE_WRITE_LINE_MEMBER( ctsa_w );
DECLARE_WRITE_LINE_MEMBER( ctsb_w );
DECLARE_READ_LINE_MEMBER( dtra_r );
DECLARE_READ_LINE_MEMBER( dtrb_r );
DECLARE_WRITE_LINE_MEMBER( hai_w );
DECLARE_WRITE_LINE_MEMBER( rxda_w );
DECLARE_READ_LINE_MEMBER( txda_r );
DECLARE_WRITE_LINE_MEMBER( rxdb_w );
DECLARE_READ_LINE_MEMBER( txdb_r );
DECLARE_WRITE_LINE_MEMBER( rxca_w );
DECLARE_WRITE_LINE_MEMBER( rxcb_w );
DECLARE_WRITE_LINE_MEMBER( txca_w );
DECLARE_WRITE_LINE_MEMBER( txcb_w );
protected:
// device-level overrides
virtual void device_config_complete();
virtual void device_start();
virtual void device_reset();
virtual void device_timer(emu_timer &timer, device_timer_id id, int m_param, void *ptr);
private:
static const device_timer_id TIMER_RX_A = 0;
static const device_timer_id TIMER_TX_A = 1;
static const device_timer_id TIMER_RX_B = 2;
static const device_timer_id TIMER_TX_B = 3;
inline void receive(int channel);
inline void transmit(int channel);
devcb_resolved_write_line m_out_int_func;
// timers
//emu_timer *m_rx_a_timer;
//emu_timer *m_tx_a_timer;
//emu_timer *m_rx_b_timer;
//emu_timer *m_tx_b_timer;
};
// device type definition
extern const device_type UPD7201;
#endif

128
src/emu/machine/z80dart.c
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@ -182,24 +182,72 @@ const int WR5_DTR = 0x80;
// device type definition
const device_type Z80DART = &device_creator<z80dart_device>;
const device_type Z80SIO0 = &device_creator<z80dart_device>;
const device_type Z80SIO1 = &device_creator<z80dart_device>;
const device_type Z80SIO2 = &device_creator<z80dart_device>;
const device_type Z80SIO3 = &device_creator<z80dart_device>;
const device_type Z80SIO4 = &device_creator<z80dart_device>;
const device_type Z80SIO0 = &device_creator<z80sio0_device>;
const device_type Z80SIO1 = &device_creator<z80sio1_device>;
const device_type Z80SIO2 = &device_creator<z80sio2_device>;
const device_type Z80SIO3 = &device_creator<z80sio3_device>;
const device_type Z80SIO4 = &device_creator<z80sio4_device>;
const device_type I8274 = &device_creator<i8274_device>;
const device_type UPD7201 = &device_creator<upd7201_device>;
//-------------------------------------------------
// z80dart_device - constructor
//-------------------------------------------------
z80dart_device::z80dart_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: device_t(mconfig, Z80DART, "Zilog Z80 DART", tag, owner, clock),
device_z80daisy_interface(mconfig, *this)
z80dart_device::z80dart_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source)
: device_t(mconfig, type, name, tag, owner, clock, shortname, source),
device_z80daisy_interface(mconfig, *this),
m_variant(variant)
{
for (int i = 0; i < 8; i++)
m_int_state[i] = 0;
}
z80dart_device::z80dart_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: device_t(mconfig, Z80DART, "Z80-DART", tag, owner, clock, "z80dart", __FILE__),
device_z80daisy_interface(mconfig, *this),
m_variant(TYPE_DART)
{
for (int i = 0; i < 8; i++)
m_int_state[i] = 0;
}
z80sio0_device::z80sio0_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: z80dart_device(mconfig, Z80SIO0, "Z80-SIO/0", tag, owner, clock, TYPE_SIO0, "z80sio0", __FILE__)
{
}
z80sio1_device::z80sio1_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: z80dart_device(mconfig, Z80SIO1, "Z80-SIO/1", tag, owner, clock, TYPE_SIO1, "z80sio1", __FILE__)
{
}
z80sio2_device::z80sio2_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: z80dart_device(mconfig, Z80SIO2, "Z80-SIO/2", tag, owner, clock, TYPE_SIO2, "z80sio2", __FILE__)
{
}
z80sio3_device::z80sio3_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: z80dart_device(mconfig, Z80SIO3, "Z80-SIO/3", tag, owner, clock, TYPE_SIO3, "z80sio3", __FILE__)
{
}
z80sio4_device::z80sio4_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: z80dart_device(mconfig, Z80SIO4, "Z80-SIO/4", tag, owner, clock, TYPE_SIO4, "z80sio4", __FILE__)
{
}
i8274_device::i8274_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: z80dart_device(mconfig, I8274, "I8274", tag, owner, clock, TYPE_I8274, "i8274", __FILE__)
{
}
upd7201_device::upd7201_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: z80dart_device(mconfig, UPD7201, "uPD7201", tag, owner, clock, TYPE_UPD7201, "upd7201", __FILE__)
{
}
//-------------------------------------------------
// device_config_complete - perform any
@ -218,6 +266,7 @@ void z80dart_device::device_config_complete()
else
{
m_rx_clock_a = m_tx_clock_a = m_rx_clock_b = m_tx_clock_b = 0;
memset(&m_in_rxda_cb, 0, sizeof(m_in_rxda_cb));
memset(&m_out_txda_cb, 0, sizeof(m_out_txda_cb));
memset(&m_out_dtra_cb, 0, sizeof(m_out_dtra_cb));
@ -231,6 +280,10 @@ void z80dart_device::device_config_complete()
memset(&m_out_wrdyb_cb, 0, sizeof(m_out_wrdyb_cb));
memset(&m_out_syncb_cb, 0, sizeof(m_out_syncb_cb));
memset(&m_out_int_cb, 0, sizeof(m_out_int_cb));
memset(&m_out_rxdrqa_cb, 0, sizeof(m_out_rxdrqa_cb));
memset(&m_out_txdrqa_cb, 0, sizeof(m_out_txdrqa_cb));
memset(&m_out_rxdrqb_cb, 0, sizeof(m_out_rxdrqb_cb));
memset(&m_out_txdrqb_cb, 0, sizeof(m_out_txdrqb_cb));
}
}
@ -244,8 +297,8 @@ void z80dart_device::device_start()
// resolve callbacks
m_out_int_func.resolve(m_out_int_cb, *this);
m_channel[CHANNEL_A].start(this, CHANNEL_A, m_in_rxda_cb, m_out_txda_cb, m_out_dtra_cb, m_out_rtsa_cb, m_out_wrdya_cb, m_out_synca_cb);
m_channel[CHANNEL_B].start(this, CHANNEL_B, m_in_rxdb_cb, m_out_txdb_cb, m_out_dtrb_cb, m_out_rtsb_cb, m_out_wrdyb_cb, m_out_syncb_cb);
m_channel[CHANNEL_A].start(this, CHANNEL_A, m_in_rxda_cb, m_out_txda_cb, m_out_dtra_cb, m_out_rtsa_cb, m_out_wrdya_cb, m_out_synca_cb, m_out_rxdrqa_cb, m_out_txdrqa_cb);
m_channel[CHANNEL_B].start(this, CHANNEL_B, m_in_rxdb_cb, m_out_txdb_cb, m_out_dtrb_cb, m_out_rtsb_cb, m_out_wrdyb_cb, m_out_syncb_cb, m_out_rxdrqa_cb, m_out_txdrqa_cb);
if (m_rx_clock_a != 0)
{
@ -481,7 +534,7 @@ z80dart_device::dart_channel::dart_channel()
// start - channel startup
//-------------------------------------------------
void z80dart_device::dart_channel::start(z80dart_device *device, int index, const devcb_read_line &in_rxd, const devcb_write_line &out_txd, const devcb_write_line &out_dtr, const devcb_write_line &out_rts, const devcb_write_line &out_wrdy, const devcb_write_line &out_sync)
void z80dart_device::dart_channel::start(z80dart_device *device, int index, const devcb_read_line &in_rxd, const devcb_write_line &out_txd, const devcb_write_line &out_dtr, const devcb_write_line &out_rts, const devcb_write_line &out_wrdy, const devcb_write_line &out_sync, const devcb_write_line &out_rxdrq, const devcb_write_line &out_txdrq)
{
m_index = index;
m_device = device;
@ -492,6 +545,8 @@ void z80dart_device::dart_channel::start(z80dart_device *device, int index, cons
m_out_rts_func.resolve(out_rts, *m_device);
m_out_wrdy_func.resolve(out_wrdy, *m_device);
m_out_sync_func.resolve(out_sync, *m_device);
m_out_rxdrq_func.resolve(out_rxdrq, *m_device);
m_out_txdrq_func.resolve(out_txdrq, *m_device);
m_device->save_item(NAME(m_rr), m_index);
m_device->save_item(NAME(m_wr), m_index);
@ -1430,57 +1485,6 @@ void z80dart_device::dart_channel::tx_w(int state)
// GLOBAL STUBS
//**************************************************************************
READ8_DEVICE_HANDLER( z80dart_c_r ) { return downcast<z80dart_device *>(device)->control_read(offset & 1); }
READ8_DEVICE_HANDLER( z80dart_d_r ) { return downcast<z80dart_device *>(device)->data_read(offset & 1); }
WRITE8_DEVICE_HANDLER( z80dart_c_w ) { downcast<z80dart_device *>(device)->control_write(offset & 1, data); }
WRITE8_DEVICE_HANDLER( z80dart_d_w ) { downcast<z80dart_device *>(device)->data_write(offset & 1, data); }
WRITE_LINE_DEVICE_HANDLER( z80dart_ctsa_w ) { downcast<z80dart_device *>(device)->cts_w(CHANNEL_A, state); }
WRITE_LINE_DEVICE_HANDLER( z80dart_ctsb_w ) { downcast<z80dart_device *>(device)->cts_w(CHANNEL_B, state); }
WRITE_LINE_DEVICE_HANDLER( z80dart_dcda_w ) { downcast<z80dart_device *>(device)->dcd_w(CHANNEL_A, state); }
WRITE_LINE_DEVICE_HANDLER( z80dart_dcdb_w ) { downcast<z80dart_device *>(device)->dcd_w(CHANNEL_B, state); }
WRITE_LINE_DEVICE_HANDLER( z80dart_ria_w ) { downcast<z80dart_device *>(device)->ri_w(CHANNEL_A, state); }
WRITE_LINE_DEVICE_HANDLER( z80dart_rib_w ) { downcast<z80dart_device *>(device)->ri_w(CHANNEL_B, state); }
WRITE_LINE_DEVICE_HANDLER( z80dart_synca_w ) { downcast<z80dart_device *>(device)->sync_w(CHANNEL_A, state); }
WRITE_LINE_DEVICE_HANDLER( z80dart_syncb_w ) { downcast<z80dart_device *>(device)->sync_w(CHANNEL_B, state); }
WRITE_LINE_DEVICE_HANDLER( z80dart_rxca_w ) { downcast<z80dart_device *>(device)->rx_w(CHANNEL_A, state); }
WRITE_LINE_DEVICE_HANDLER( z80dart_txca_w ) { downcast<z80dart_device *>(device)->tx_w(CHANNEL_A, state); }
WRITE_LINE_DEVICE_HANDLER( z80dart_rxcb_w ) { downcast<z80dart_device *>(device)->rx_w(CHANNEL_B, state); }
WRITE_LINE_DEVICE_HANDLER( z80dart_txcb_w ) { downcast<z80dart_device *>(device)->tx_w(CHANNEL_B, state); }
WRITE_LINE_DEVICE_HANDLER( z80dart_rxtxcb_w ) { downcast<z80dart_device *>(device)->rx_w(CHANNEL_B, state); downcast<z80dart_device *>(device)->tx_w(CHANNEL_B, state); }
READ8_DEVICE_HANDLER( z80dart_cd_ba_r )
{
return (offset & 2) ? z80dart_c_r(device, space, offset & 1) : z80dart_d_r(device, space, offset & 1);
}
WRITE8_DEVICE_HANDLER( z80dart_cd_ba_w )
{
if (offset & 2)
z80dart_c_w(device, space, offset & 1, data);
else
z80dart_d_w(device, space, offset & 1, data);
}
READ8_DEVICE_HANDLER( z80dart_ba_cd_r )
{
int channel = BIT(offset, 1);
return (offset & 1) ? z80dart_c_r(device, space, channel) : z80dart_d_r(device, space, channel);
}
WRITE8_DEVICE_HANDLER( z80dart_ba_cd_w )
{
int channel = BIT(offset, 1);
if (offset & 1)
z80dart_c_w(device, space, channel, data);
else
z80dart_d_w(device, space, channel, data);
}
READ8_MEMBER( z80dart_device::cd_ba_r )
{
return (offset & 2) ? control_read(offset & 1) : data_read(offset & 1);

217
src/emu/machine/z80dart.h
View File

@ -1,6 +1,9 @@
/***************************************************************************
Z80 DART Dual Asynchronous Receiver/Transmitter implementation
Z80-DART Dual Asynchronous Receiver/Transmitter emulation
Z80-SIO/1/2/4 Serial Input/Output Controller emulation
Intel 8274 Multi-Protocol Serial Controller emulation
NEC uPD7201 Multiprotocol Serial Communications Controller emulation
Copyright (c) 2008, The MESS Team.
Visit http://mamedev.org for licensing and usage restrictions.
@ -17,7 +20,7 @@
_M1 8 | | 33 C/_D
Vdd 9 | | 32 _RD
_W/RDYA 10 | Z80-DART | 31 GND
_RIA 11 | | 30 _W/RDYB
_RIA 11 | Z8470 | 30 _W/RDYB
RxDA 12 | | 29 _RIB
_RxCA 13 | | 28 RxDB
_TxCA 14 | | 27 _RxTxCB
@ -39,7 +42,7 @@
_M1 8 | | 33 C/_D
Vdd 9 | | 32 _RD
_W/RDYA 10 | Z80-SIO/0 | 31 GND
_SYNCA 11 | | 30 _W/RDYB
_SYNCA 11 | Z8440 | 30 _W/RDYB
RxDA 12 | | 29 _SYNCB
_RxCA 13 | | 28 RxDB
_TxCA 14 | | 27 _RxTxCB
@ -61,7 +64,7 @@
_M1 8 | | 33 C/_D
Vdd 9 | | 32 _RD
_W/RDYA 10 | Z80-SIO/1 | 31 GND
_SYNCA 11 | | 30 _W/RDYB
_SYNCA 11 | Z8441 | 30 _W/RDYB
RxDA 12 | | 29 _SYNCB
_RxCA 13 | | 28 RxDB
_TxCA 14 | | 27 _RxCB
@ -83,7 +86,7 @@
_M1 8 | | 33 C/_D
Vdd 9 | | 32 _RD
_W/RDYA 10 | Z80-SIO/2 | 31 GND
_SYNCA 11 | | 30 _W/RDYB
_SYNCA 11 | Z8442 | 30 _W/RDYB
RxDA 12 | | 29 _RxDB
_RxCA 13 | | 28 _RxCB
_TxCA 14 | | 27 _TxCB
@ -94,6 +97,50 @@
_DCDA 19 | | 22 _DCDB
CLK 20 |_____________| 21 _RESET
_____ _____
CLK 1 |* \_/ | 40 Vcc
_RESET 2 | | 39 _CTSA
_CDA 3 | | 38 _RTSA
_RxCB 4 | | 37 TxDA
_CDB 5 | | 36 _TxCA
_CTSB 6 | | 35 _RxCA
_TxCB 7 | | 34 RxDA
TxDB 8 | | 33 _SYNDETA
RxDB 9 | | 32 RDYA/RxDRQA
_RTSB/_SYNDETB 10 | I8274 | 31 _DTRA
RDYB/_TxDRQA 11 | | 30 _IPO/TxDRQB
D7 12 | | 29 _IPI/RxDRQB
D6 13 | | 28 _INT
D5 14 | | 27 _INTA
D4 15 | | 26 _DTRB
D3 16 | | 25 A0
D2 17 | | 24 A1
D1 18 | | 23 _CS
D0 19 | | 22 _RD
Vss 20 |_____________| 21 _WR
_____ _____
CLK 1 |* \_/ | 40 Vcc
_RESET 2 | | 39 _CTSA
_DCDA 3 | | 38 _RTSA
_RxCB 4 | | 37 TxDA
_DCDB 5 | | 36 _TxCA
_CTSB 6 | | 35 _RxCA
_TxCB 7 | | 34 RxDA
TxDB 8 | | 33 _SYNCA
RxDB 9 | | 32 _WAITA/DRQRxA
_RTSB/_SYNCB 10 | UPD7201 | 31 _DTRA/_HAO
_WAITB/_DRQTxA 11 | | 30 _PRO/DRQTxB
D7 12 | | 29 _PRI/DRQRxB
D6 13 | | 28 _INT
D5 14 | | 27 _INTAK
D4 15 | | 26 _DTRB/_HAI
D3 16 | | 25 B/_A
D2 17 | | 24 C/_D
D1 18 | | 23 _CS
D0 19 | | 22 _RD
Vss 20 |_____________| 21 _WR
***************************************************************************/
#ifndef __Z80DART_H__
@ -131,12 +178,23 @@
MCFG_DEVICE_ADD(_tag, Z80SIO4, _clock) \
MCFG_DEVICE_CONFIG(_config)
#define MCFG_I8274_ADD(_tag, _clock, _config) \
MCFG_DEVICE_ADD(_tag, I8274, _clock) \
MCFG_DEVICE_CONFIG(_config)
#define MCFG_UPD7201_ADD(_tag, _clock, _config) \
MCFG_DEVICE_ADD(_tag, UPD7201, _clock) \
MCFG_DEVICE_CONFIG(_config)
#define MCFG_Z80DART_REMOVE(_tag) \
MCFG_DEVICE_REMOVE(_tag)
#define Z80DART_INTERFACE(_name) \
const z80dart_interface (_name) =
#define UPD7201_INTERFACE(_name) \
const z80dart_interface (_name) =
//**************************************************************************
@ -168,10 +226,13 @@ struct z80dart_interface
devcb_write_line m_out_syncb_cb;
devcb_write_line m_out_int_cb;
devcb_write_line m_out_rxdrqa_cb;
devcb_write_line m_out_txdrqa_cb;
devcb_write_line m_out_rxdrqb_cb;
devcb_write_line m_out_txdrqb_cb;
};
// ======================> z80dart_device
class z80dart_device : public device_t,
@ -182,6 +243,7 @@ class z80dart_device : public device_t,
public:
// construction/destruction
z80dart_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source);
z80dart_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
DECLARE_READ8_MEMBER( cd_ba_r );
@ -217,14 +279,27 @@ public:
DECLARE_WRITE_LINE_MEMBER( dcdb_w ) { dcd_w(1, state); }
DECLARE_WRITE_LINE_MEMBER( ria_w ) { ri_w(0, state); }
DECLARE_WRITE_LINE_MEMBER( rib_w ) { ri_w(1, state); }
DECLARE_WRITE_LINE_MEMBER( rxa_w ) { rx_w(0, state); }
DECLARE_WRITE_LINE_MEMBER( rxb_w ) { rx_w(1, state); }
DECLARE_WRITE_LINE_MEMBER( txa_w ) { tx_w(0, state); }
DECLARE_WRITE_LINE_MEMBER( txb_w ) { tx_w(1, state); }
DECLARE_WRITE_LINE_MEMBER( rxca_w ) { rx_w(0, state); }
DECLARE_WRITE_LINE_MEMBER( rxcb_w ) { rx_w(1, state); }
DECLARE_WRITE_LINE_MEMBER( txca_w ) { tx_w(0, state); }
DECLARE_WRITE_LINE_MEMBER( txcb_w ) { tx_w(1, state); }
DECLARE_WRITE_LINE_MEMBER( rxtxcb_w ) { rx_w(1, state); tx_w(1, state); }
DECLARE_WRITE_LINE_MEMBER( synca_w ) { sync_w(0, state); }
DECLARE_WRITE_LINE_MEMBER( syncb_w ) { sync_w(1, state); }
private:
protected:
enum
{
TYPE_DART,
TYPE_SIO0,
TYPE_SIO1,
TYPE_SIO2,
TYPE_SIO3,
TYPE_SIO4,
TYPE_I8274,
TYPE_UPD7201
};
// device-level overrides
virtual void device_config_complete();
virtual void device_start();
@ -247,7 +322,7 @@ private:
public:
dart_channel();
void start(z80dart_device *device, int index, const devcb_read_line &in_rxd, const devcb_write_line &out_txd, const devcb_write_line &out_dtr, const devcb_write_line &out_rts, const devcb_write_line &out_wrdy, const devcb_write_line &out_sync);
void start(z80dart_device *device, int index, const devcb_read_line &in_rxd, const devcb_write_line &out_txd, const devcb_write_line &out_dtr, const devcb_write_line &out_rts, const devcb_write_line &out_wrdy, const devcb_write_line &out_sync, const devcb_write_line &out_rxdrq, const devcb_write_line &out_txdrq);
void reset();
UINT8 control_read();
@ -291,6 +366,8 @@ private:
devcb_resolved_write_line m_out_rts_func;
devcb_resolved_write_line m_out_wrdy_func;
devcb_resolved_write_line m_out_sync_func;
devcb_resolved_write_line m_out_rxdrq_func;
devcb_resolved_write_line m_out_txdrq_func;
// register state
UINT8 m_rr[3]; // read register
@ -341,6 +418,78 @@ private:
emu_timer * m_txca_timer;
emu_timer * m_rxcb_timer;
emu_timer * m_txcb_timer;
int m_variant;
};
// ======================> z80sio0_device
class z80sio0_device : public z80dart_device
{
public:
// construction/destruction
z80sio0_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
// ======================> z80sio1_device
class z80sio1_device : public z80dart_device
{
public:
// construction/destruction
z80sio1_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
// ======================> z80sio2_device
class z80sio2_device : public z80dart_device
{
public:
// construction/destruction
z80sio2_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
// ======================> z80sio3_device
class z80sio3_device : public z80dart_device
{
public:
// construction/destruction
z80sio3_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
// ======================> z80sio4_device
class z80sio4_device : public z80dart_device
{
public:
// construction/destruction
z80sio4_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
// ======================> i8274_device
class i8274_device : public z80dart_device
{
public:
// construction/destruction
i8274_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
// ======================> upd7201_device
class upd7201_device : public z80dart_device
{
public:
// construction/destruction
upd7201_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
@ -351,49 +500,9 @@ extern const device_type Z80SIO1;
extern const device_type Z80SIO2;
extern const device_type Z80SIO3;
extern const device_type Z80SIO4;
extern const device_type I8274;
extern const device_type UPD7201;
//**************************************************************************
// READ/WRITE HANDLERS
//**************************************************************************
// register access
DECLARE_READ8_DEVICE_HANDLER( z80dart_cd_ba_r );
DECLARE_WRITE8_DEVICE_HANDLER( z80dart_cd_ba_w );
DECLARE_READ8_DEVICE_HANDLER( z80dart_ba_cd_r );
DECLARE_WRITE8_DEVICE_HANDLER( z80dart_ba_cd_w );
// control register access
DECLARE_WRITE8_DEVICE_HANDLER( z80dart_c_w );
DECLARE_READ8_DEVICE_HANDLER( z80dart_c_r );
// data register access
DECLARE_WRITE8_DEVICE_HANDLER( z80dart_d_w );
DECLARE_READ8_DEVICE_HANDLER( z80dart_d_r );
// serial clocks
WRITE_LINE_DEVICE_HANDLER( z80dart_rxca_w );
WRITE_LINE_DEVICE_HANDLER( z80dart_txca_w );
WRITE_LINE_DEVICE_HANDLER( z80dart_rxcb_w );
WRITE_LINE_DEVICE_HANDLER( z80dart_txcb_w );
WRITE_LINE_DEVICE_HANDLER( z80dart_rxtxcb_w );
// ring indicator
WRITE_LINE_DEVICE_HANDLER( z80dart_ria_w );
WRITE_LINE_DEVICE_HANDLER( z80dart_rib_w );
// data carrier detected
WRITE_LINE_DEVICE_HANDLER( z80dart_dcda_w );
WRITE_LINE_DEVICE_HANDLER( z80dart_dcdb_w );
// clear to send
WRITE_LINE_DEVICE_HANDLER( z80dart_ctsa_w );
WRITE_LINE_DEVICE_HANDLER( z80dart_ctsb_w );
// sync
WRITE_LINE_DEVICE_HANDLER( z80dart_synca_w );
WRITE_LINE_DEVICE_HANDLER( z80dart_syncb_w );
#endif

12
src/mess/drivers/abc1600.c
View File

@ -267,7 +267,7 @@ UINT8 abc1600_state::read_internal_io(offs_t offset)
break;
case DRT:
data = z80dart_ba_cd_r(m_dart, program, A2_A1 ^ 0x03);
data = m_dart->ba_cd_r(program, A2_A1 ^ 0x03);
break;
case DMA0:
@ -521,7 +521,7 @@ void abc1600_state::write_internal_io(offs_t offset, UINT8 data)
break;
case DRT:
z80dart_ba_cd_w(m_dart, program, A2_A1 ^ 0x03, data);
m_dart->ba_cd_w(program, A2_A1 ^ 0x03, data);
break;
case DMA0:
@ -1635,8 +1635,8 @@ WRITE8_MEMBER( abc1600_state::cio_pb_w )
// printer baudrate
int prbr = BIT(data, 0);
z80dart_txca_w(m_dart, prbr);
z80dart_rxca_w(m_dart, prbr);
m_dart->txca_w(prbr);
m_dart->rxca_w(prbr);
}
READ8_MEMBER( abc1600_state::cio_pc_r )
@ -1736,8 +1736,8 @@ void abc1600_state::fdc_drq_w(bool state)
static ABC99_INTERFACE( abc99_intf )
{
DEVCB_DEVICE_LINE(Z8470AB1_TAG, z80dart_rxtxcb_w),
DEVCB_DEVICE_LINE(Z8470AB1_TAG, z80dart_dcdb_w)
DEVCB_DEVICE_LINE_MEMBER(Z8470AB1_TAG, z80dart_device, rxtxcb_w),
DEVCB_DEVICE_LINE_MEMBER(Z8470AB1_TAG, z80dart_device, dcdb_w)
};

36
src/mess/drivers/abc80x.c
View File

@ -440,7 +440,7 @@ static ADDRESS_MAP_START( abc800c_io, AS_IO, 8, abc800_state )
AM_RANGE(0x06, 0x06) AM_MIRROR(0x18) AM_WRITE(hrs_w)
AM_RANGE(0x07, 0x07) AM_MIRROR(0x18) AM_DEVREAD(ABCBUS_TAG, abcbus_slot_device, rst_r) AM_WRITE(hrc_w)
AM_RANGE(0x20, 0x23) AM_MIRROR(0x0c) AM_DEVREADWRITE(Z80DART_TAG, z80dart_device, ba_cd_r, ba_cd_w)
AM_RANGE(0x40, 0x43) AM_MIRROR(0x1c) AM_DEVREADWRITE(Z80SIO_TAG, z80dart_device, ba_cd_r, ba_cd_w)
AM_RANGE(0x40, 0x43) AM_MIRROR(0x1c) AM_DEVREADWRITE(Z80SIO_TAG, z80sio2_device, ba_cd_r, ba_cd_w)
AM_RANGE(0x60, 0x63) AM_MIRROR(0x1c) AM_DEVREADWRITE(Z80CTC_TAG, z80ctc_device, read, write)
ADDRESS_MAP_END
@ -501,7 +501,7 @@ static ADDRESS_MAP_START( abc802_io, AS_IO, 8, abc802_state )
AM_RANGE(0x31, 0x31) AM_MIRROR(0x06) AM_DEVREAD(MC6845_TAG, mc6845_device, register_r)
AM_RANGE(0x38, 0x38) AM_MIRROR(0x06) AM_DEVWRITE(MC6845_TAG, mc6845_device, address_w)
AM_RANGE(0x39, 0x39) AM_MIRROR(0x06) AM_DEVWRITE(MC6845_TAG, mc6845_device, register_w)
AM_RANGE(0x40, 0x43) AM_MIRROR(0x1c) AM_DEVREADWRITE(Z80SIO_TAG, z80dart_device, ba_cd_r, ba_cd_w)
AM_RANGE(0x40, 0x43) AM_MIRROR(0x1c) AM_DEVREADWRITE(Z80SIO_TAG, z80sio2_device, ba_cd_r, ba_cd_w)
AM_RANGE(0x60, 0x63) AM_MIRROR(0x1c) AM_DEVREADWRITE(Z80CTC_TAG, z80ctc_device, read, write)
ADDRESS_MAP_END
@ -553,7 +553,7 @@ static ADDRESS_MAP_START( abc806_io, AS_IO, 8, abc806_state )
AM_RANGE(0x37, 0x37) AM_MIRROR(0xff00) AM_MASK(0xff00) AM_READWRITE(cli_r, sso_w)
AM_RANGE(0x38, 0x38) AM_MIRROR(0xff00) AM_DEVWRITE(MC6845_TAG, mc6845_device, address_w)
AM_RANGE(0x39, 0x39) AM_MIRROR(0xff00) AM_DEVWRITE(MC6845_TAG, mc6845_device, register_w)
AM_RANGE(0x40, 0x43) AM_MIRROR(0xff1c) AM_DEVREADWRITE(Z80SIO_TAG, z80dart_device, ba_cd_r, ba_cd_w)
AM_RANGE(0x40, 0x43) AM_MIRROR(0xff1c) AM_DEVREADWRITE(Z80SIO_TAG, z80sio2_device, ba_cd_r, ba_cd_w)
AM_RANGE(0x60, 0x63) AM_MIRROR(0xff1c) AM_DEVREADWRITE(Z80CTC_TAG, z80ctc_device, read, write)
ADDRESS_MAP_END
@ -632,7 +632,7 @@ WRITE_LINE_MEMBER( abc800_state::ctc_z0_w )
{
if (BIT(m_sb, 2))
{
z80dart_txca_w(m_sio, state);
m_sio->txca_w(state);
m_ctc->trg3(state);
}
@ -643,20 +643,20 @@ WRITE_LINE_MEMBER( abc800_state::ctc_z1_w )
{
if (BIT(m_sb, 3))
{
z80dart_rxca_w(m_sio, state);
m_sio->rxca_w(state);
}
if (BIT(m_sb, 4))
{
z80dart_txca_w(m_sio, state);
m_sio->txca_w(state);
m_ctc->trg3(state);
}
}
WRITE_LINE_MEMBER( abc800_state::ctc_z2_w )
{
z80dart_rxca_w(m_dart, state);
z80dart_txca_w(m_dart, state);
m_dart->rxca_w(state);
m_dart->txca_w(state);
}
static Z80CTC_INTERFACE( ctc_intf )
@ -679,7 +679,7 @@ void abc800_state::clock_cassette(int state)
if (m_ctc_z0 && !state)
{
m_sio_txcb = !m_sio_txcb;
z80dart_txcb_w(m_sio, !m_sio_txcb);
m_sio->txcb_w(!m_sio_txcb);
if (m_sio_txdb || m_sio_txcb)
{
@ -692,7 +692,7 @@ void abc800_state::clock_cassette(int state)
m_tape_ctr++;
}
z80dart_rxcb_w(m_sio, m_tape_ctr == 15);
m_sio->rxcb_w(m_tape_ctr == 15);
}
m_ctc_z0 = state;
@ -861,8 +861,8 @@ static Z80DART_INTERFACE( abc806_dart_intf )
static ABC800_KEYBOARD_INTERFACE( abc800_kb_intf )
{
DEVCB_DEVICE_LINE(Z80DART_TAG, z80dart_rxtxcb_w),
DEVCB_DEVICE_LINE(Z80DART_TAG, z80dart_dcdb_w)
DEVCB_DEVICE_LINE_MEMBER(Z80DART_TAG, z80dart_device, rxtxcb_w),
DEVCB_DEVICE_LINE_MEMBER(Z80DART_TAG, z80dart_device, dcdb_w)
};
@ -872,8 +872,8 @@ static ABC800_KEYBOARD_INTERFACE( abc800_kb_intf )
static ABC77_INTERFACE( kb_intf )
{
DEVCB_DEVICE_LINE(Z80DART_TAG, z80dart_rxtxcb_w),
DEVCB_DEVICE_LINE(Z80DART_TAG, z80dart_dcdb_w)
DEVCB_DEVICE_LINE_MEMBER(Z80DART_TAG, z80dart_device, rxtxcb_w),
DEVCB_DEVICE_LINE_MEMBER(Z80DART_TAG, z80dart_device, dcdb_w)
};
@ -1083,16 +1083,16 @@ void abc802_state::machine_reset()
bankswitch();
// clear screen time out (S1)
z80dart_dcdb_w(m_sio, BIT(config, 0));
m_sio->dcdb_w(BIT(config, 0));
// unknown (S2)
z80dart_ctsb_w(m_sio, BIT(config, 1));
m_sio->ctsb_w(BIT(config, 1));
// 40/80 char (S3)
m_dart->ri_w(0, BIT(config, 2)); // 0 = 40, 1 = 80
m_dart->ria_w(BIT(config, 2)); // 0 = 40, 1 = 80
// 50/60 Hz
m_dart->cts_w(1, BIT(config, 3)); // 0 = 50Hz, 1 = 60Hz
m_dart->ctsb_w(BIT(config, 3)); // 0 = 50Hz, 1 = 60Hz
m_dfd_in = 0;
}

14
src/mess/drivers/apricotf.c
View File

@ -180,7 +180,7 @@ static ADDRESS_MAP_START( act_f1_io, AS_IO, 16, f1_state )
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(0x0000, 0x000f) AM_WRITE8(system_w, 0xffff)
AM_RANGE(0x0010, 0x0017) AM_DEVREADWRITE8(Z80CTC_TAG, z80ctc_device, read, write, 0x00ff)
AM_RANGE(0x0020, 0x0027) AM_DEVREADWRITE8_LEGACY(Z80SIO2_TAG, z80dart_ba_cd_r, z80dart_ba_cd_w, 0x00ff)
AM_RANGE(0x0020, 0x0027) AM_DEVREADWRITE8(Z80SIO2_TAG, z80sio2_device, ba_cd_r, ba_cd_w, 0x00ff)
// AM_RANGE(0x0030, 0x0031) AM_WRITE8(ctc_ack_w, 0x00ff)
AM_RANGE(0x0040, 0x0047) AM_DEVREADWRITE8_LEGACY(WD2797_TAG, wd17xx_r, wd17xx_w, 0x00ff)
// AM_RANGE(0x01e0, 0x01ff) winchester
@ -223,7 +223,7 @@ WRITE_LINE_MEMBER( f1_state::sio_int_w )
{
m_sio_int = state;
m_maincpu->set_input_line(INPUT_LINE_IRQ0, m_ctc_int | m_sio_int);
m_maincpu->set_input_line(INPUT_LINE_IRQ0, m_ctc_int || m_sio_int);
}
static Z80DART_INTERFACE( sio_intf )
@ -261,13 +261,13 @@ WRITE_LINE_MEMBER( f1_state::ctc_int_w )
WRITE_LINE_MEMBER( f1_state::ctc_z1_w )
{
z80dart_rxcb_w(m_sio, state);
z80dart_txcb_w(m_sio, state);
m_sio->rxcb_w(state);
m_sio->txcb_w(state);
}
WRITE_LINE_MEMBER( f1_state::ctc_z2_w )
{
z80dart_txca_w(m_sio, state);
m_sio->txca_w(state);
}
static Z80CTC_INTERFACE( ctc_intf )
@ -321,7 +321,7 @@ static const wd17xx_interface fdc_intf =
static const centronics_interface centronics_intf =
{
DEVCB_NULL,
DEVCB_DEVICE_LINE(Z80SIO2_TAG, z80dart_ctsa_w),
DEVCB_DEVICE_LINE_MEMBER(Z80SIO2_TAG, z80dart_device, ctsa_w),
DEVCB_NULL
};
@ -353,7 +353,7 @@ static MACHINE_CONFIG_START( act_f1, f1_state )
/* Devices */
MCFG_APRICOT_KEYBOARD_ADD(kb_intf)
MCFG_Z80DART_ADD(Z80SIO2_TAG, 2500000, sio_intf)
MCFG_Z80SIO2_ADD(Z80SIO2_TAG, 2500000, sio_intf)
MCFG_Z80CTC_ADD(Z80CTC_TAG, 2500000, ctc_intf)
MCFG_WD2797_ADD(WD2797_TAG, fdc_intf)
MCFG_LEGACY_FLOPPY_2_DRIVES_ADD(act_floppy_interface)

2
src/mess/drivers/apricotp.c
View File

@ -347,7 +347,7 @@ static ADDRESS_MAP_START( fp_io, AS_IO, 16, fp_state )
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(0x000, 0x007) AM_DEVREADWRITE8(WD2797_TAG, wd2797_t, read, write, 0x00ff)
AM_RANGE(0x008, 0x00f) AM_DEVREADWRITE8_LEGACY(I8253A5_TAG, pit8253_r, pit8253_w, 0x00ff)
AM_RANGE(0x018, 0x01f) AM_DEVREADWRITE8_LEGACY(Z80SIO0_TAG, z80dart_ba_cd_r, z80dart_ba_cd_w, 0x00ff)
AM_RANGE(0x018, 0x01f) AM_DEVREADWRITE8(Z80SIO0_TAG, z80sio0_device, ba_cd_r, ba_cd_w, 0x00ff)
AM_RANGE(0x020, 0x021) AM_DEVWRITE8(CENTRONICS_TAG, centronics_device, write, 0x00ff)
AM_RANGE(0x022, 0x023) AM_WRITE8(pint_clr_w, 0x00ff)
AM_RANGE(0x024, 0x025) AM_READ8(prtr_snd_r, 0x00ff)

16
src/mess/drivers/bullet.c
View File

@ -612,7 +612,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( bullet_io, AS_IO, 8, bullet_state )
ADDRESS_MAP_GLOBAL_MASK(0x1f)
AM_RANGE(0x00, 0x03) AM_DEVREADWRITE_LEGACY(Z80DART_TAG, z80dart_ba_cd_r, z80dart_ba_cd_w)
AM_RANGE(0x00, 0x03) AM_DEVREADWRITE(Z80DART_TAG, z80dart_device, ba_cd_r, ba_cd_w)
AM_RANGE(0x04, 0x07) AM_DEVREADWRITE(Z80PIO_TAG, z80pio_device, read, write)
AM_RANGE(0x08, 0x0b) AM_DEVREADWRITE(Z80CTC_TAG, z80ctc_device, read, write)
AM_RANGE(0x0c, 0x0c) AM_MIRROR(0x03) AM_READWRITE(win_r, wstrobe_w)
@ -642,7 +642,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( bulletf_io, AS_IO, 8, bulletf_state )
ADDRESS_MAP_GLOBAL_MASK(0x3f)
AM_RANGE(0x00, 0x03) AM_DEVREADWRITE_LEGACY(Z80DART_TAG, z80dart_ba_cd_r, z80dart_ba_cd_w)
AM_RANGE(0x00, 0x03) AM_DEVREADWRITE(Z80DART_TAG, z80dart_device, ba_cd_r, ba_cd_w)
AM_RANGE(0x04, 0x07) AM_DEVREADWRITE(Z80PIO_TAG, z80pio_device, read, write)
AM_RANGE(0x08, 0x0b) AM_DEVREADWRITE(Z80CTC_TAG, z80ctc_device, read, write)
AM_RANGE(0x10, 0x13) AM_DEVREADWRITE(MB8877_TAG, mb8877_t, read, write)
@ -734,17 +734,17 @@ TIMER_DEVICE_CALLBACK_MEMBER(bullet_state::ctc_tick)
m_ctc->trg2(0);
}
WRITE_LINE_MEMBER(bullet_state::dart_rxtxca_w)
WRITE_LINE_MEMBER( bullet_state::dart_rxtxca_w )
{
z80dart_txca_w(m_dart, state);
z80dart_rxca_w(m_dart, state);
m_dart->txca_w(state);
m_dart->rxca_w(state);
}
static Z80CTC_INTERFACE( ctc_intf )
{
DEVCB_CPU_INPUT_LINE(Z80_TAG, INPUT_LINE_IRQ0), // interrupt handler
DEVCB_DRIVER_LINE_MEMBER(bullet_state, dart_rxtxca_w), // ZC/TO0 callback
DEVCB_DEVICE_LINE(Z80DART_TAG, z80dart_rxtxcb_w), // ZC/TO1 callback
DEVCB_DEVICE_LINE_MEMBER(Z80DART_TAG, z80dart_device, rxtxcb_w), // ZC/TO1 callback
DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF, z80ctc_device, trg3) // ZC/TO2 callback
};
@ -1056,12 +1056,12 @@ SLOT_INTERFACE_END
void bullet_state::fdc_intrq_w(bool state)
{
z80dart_dcda_w(m_dart, state);
m_dart->dcda_w(state);
}
void bulletf_state::fdc_intrq_w(bool state)
{
z80dart_rib_w(m_dart, state);
m_dart->rib_w(state);
}
void bullet_state::fdc_drq_w(bool state)

13
src/mess/drivers/bw12.c
View File

@ -172,10 +172,7 @@ static ADDRESS_MAP_START( bw12_io, AS_IO, 8, bw12_state )
AM_RANGE(0x11, 0x11) AM_MIRROR(0x0e) AM_DEVREADWRITE(MC6845_TAG, mc6845_device, register_r, register_w)
AM_RANGE(0x20, 0x21) AM_MIRROR(0x0e) AM_DEVICE(UPD765_TAG, upd765a_device, map)
AM_RANGE(0x30, 0x33) AM_MIRROR(0x0c) AM_DEVREADWRITE(PIA6821_TAG, pia6821_device, read, write)
AM_RANGE(0x40, 0x40) AM_MIRROR(0x0c) AM_DEVREADWRITE_LEGACY(Z80SIO_TAG, z80dart_d_r, z80dart_d_w)
AM_RANGE(0x41, 0x41) AM_MIRROR(0x0c) AM_DEVREADWRITE_LEGACY(Z80SIO_TAG, z80dart_c_r, z80dart_c_w)
AM_RANGE(0x42, 0x42) AM_MIRROR(0x0c) AM_DEVREADWRITE_LEGACY(Z80SIO_TAG, z80dart_d_r, z80dart_d_w)
AM_RANGE(0x43, 0x43) AM_MIRROR(0x0c) AM_DEVREADWRITE_LEGACY(Z80SIO_TAG, z80dart_c_r, z80dart_c_w)
AM_RANGE(0x40, 0x43) AM_MIRROR(0x0c) AM_DEVREADWRITE(Z80SIO_TAG, z80sio0_device, ba_cd_r, ba_cd_w)
AM_RANGE(0x50, 0x50) AM_MIRROR(0x0f) AM_DEVWRITE(MC1408_TAG, dac_device, write_unsigned8)
AM_RANGE(0x60, 0x63) AM_MIRROR(0x0c) AM_DEVREADWRITE_LEGACY(PIT8253_TAG, pit8253_r, pit8253_w)
ADDRESS_MAP_END
@ -473,10 +470,10 @@ static Z80DART_INTERFACE( sio_intf )
/* PIT8253 Interface */
WRITE_LINE_MEMBER(bw12_state::pit_out0_w)
WRITE_LINE_MEMBER( bw12_state::pit_out0_w )
{
z80dart_txca_w(m_sio, state);
z80dart_rxca_w(m_sio, state);
m_sio->txca_w(state);
m_sio->rxca_w(state);
}
WRITE_LINE_MEMBER( bw12_state::pit_out2_w )
@ -495,7 +492,7 @@ static const struct pit8253_config pit_intf =
{
XTAL_1_8432MHz,
DEVCB_NULL,
DEVCB_DEVICE_LINE(Z80SIO_TAG, z80dart_rxtxcb_w)
DEVCB_DEVICE_LINE_MEMBER(Z80SIO_TAG, z80dart_device, rxtxcb_w)
},
{
XTAL_1_8432MHz,

4
src/mess/drivers/huebler.c
View File

@ -97,7 +97,7 @@ static ADDRESS_MAP_START( amu880_io, AS_IO, 8, amu880_state )
AM_RANGE(0x0c, 0x0f) AM_DEVREADWRITE(Z80PIO2_TAG, z80pio_device, read_alt, write_alt)
AM_RANGE(0x10, 0x13) AM_DEVREADWRITE(Z80PIO1_TAG, z80pio_device, read_alt, write_alt)
AM_RANGE(0x14, 0x17) AM_DEVREADWRITE(Z80CTC_TAG, z80ctc_device, read, write)
AM_RANGE(0x18, 0x1b) AM_DEVREADWRITE_LEGACY(Z80SIO_TAG, z80dart_ba_cd_r, z80dart_ba_cd_w)
AM_RANGE(0x18, 0x1b) AM_DEVREADWRITE(Z80SIO_TAG, z80sio0_device, ba_cd_r, ba_cd_w)
ADDRESS_MAP_END
/* Input Ports */
@ -252,7 +252,7 @@ static Z80CTC_INTERFACE( ctc_intf )
{
DEVCB_CPU_INPUT_LINE(Z80_TAG, INPUT_LINE_IRQ0), /* interrupt handler */
DEVCB_DRIVER_LINE_MEMBER(amu880_state,ctc_z0_w), /* ZC/TO0 callback */
DEVCB_DEVICE_LINE(Z80SIO_TAG, z80dart_rxtxcb_w), /* ZC/TO1 callback */
DEVCB_DEVICE_LINE_MEMBER(Z80SIO_TAG, z80dart_device, rxtxcb_w), /* ZC/TO1 callback */
DEVCB_DRIVER_LINE_MEMBER(amu880_state,ctc_z2_w) /* ZC/TO2 callback */
};

57
src/mess/drivers/mikromik.c
View File

@ -519,12 +519,12 @@ READ8_MEMBER( mm1_state::mpsc_dack_r )
// clear data request
m_dmac->dreq2_w(CLEAR_LINE);
return m_mpsc->dtra_r();
return 1;//m_mpsc->dtra_r();
}
WRITE8_MEMBER( mm1_state::mpsc_dack_w )
{
m_mpsc->hai_w(data);
//m_mpsc->hai_w(data);
// clear data request
m_dmac->dreq1_w(CLEAR_LINE);
@ -624,36 +624,27 @@ WRITE_LINE_MEMBER( mm1_state::drq1_w )
static UPD7201_INTERFACE( mpsc_intf )
{
DEVCB_NULL, // interrupt
{
{
0, // receive clock
0, // transmit clock
DEVCB_DRIVER_LINE_MEMBER(mm1_state, drq2_w), // receive DRQ
DEVCB_DRIVER_LINE_MEMBER(mm1_state, drq1_w), // transmit DRQ
DEVCB_DEVICE_LINE_MEMBER(RS232_A_TAG, serial_port_device, rx),
DEVCB_DEVICE_LINE_MEMBER(RS232_A_TAG, serial_port_device, tx),
DEVCB_DEVICE_LINE_MEMBER(RS232_A_TAG, rs232_port_device, cts_r),
DEVCB_DEVICE_LINE_MEMBER(RS232_A_TAG, rs232_port_device, dcd_r),
DEVCB_DEVICE_LINE_MEMBER(RS232_A_TAG, rs232_port_device, rts_w),
DEVCB_DEVICE_LINE_MEMBER(RS232_A_TAG, rs232_port_device, dtr_w),
DEVCB_NULL, // wait
DEVCB_NULL // sync output
}, {
0, // receive clock
0, // transmit clock
DEVCB_NULL, // receive DRQ
DEVCB_NULL, // transmit DRQ
DEVCB_NULL, // receive data
DEVCB_NULL, // transmit data
DEVCB_NULL, // clear to send
DEVCB_LINE_GND, // data carrier detect
DEVCB_NULL, // ready to send
DEVCB_NULL, // data terminal ready
DEVCB_NULL, // wait
DEVCB_NULL // sync output
}
}
0, 0, 0, 0,
DEVCB_DEVICE_LINE_MEMBER(RS232_A_TAG, serial_port_device, rx),
DEVCB_DEVICE_LINE_MEMBER(RS232_A_TAG, serial_port_device, tx),
DEVCB_DEVICE_LINE_MEMBER(RS232_A_TAG, rs232_port_device, dtr_w),
DEVCB_DEVICE_LINE_MEMBER(RS232_A_TAG, rs232_port_device, rts_w),
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_DRIVER_LINE_MEMBER(mm1_state, drq2_w), // receive DRQ
DEVCB_DRIVER_LINE_MEMBER(mm1_state, drq1_w), // transmit DRQ
DEVCB_NULL,
DEVCB_NULL
};
@ -740,7 +731,7 @@ static const rs232_port_interface rs232c_intf =
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_DEVICE_LINE_MEMBER(UPD7201_TAG, upd7201_device, ctsb_w)
DEVCB_DEVICE_LINE_MEMBER(UPD7201_TAG, z80dart_device, ctsb_w)
};

12
src/mess/drivers/mtx.c
View File

@ -84,7 +84,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( rs128_io, AS_IO, 8, mtx_state )
AM_IMPORT_FROM(mtx_io)
AM_RANGE(0x0c, 0x0f) AM_DEVREADWRITE_LEGACY(Z80DART_TAG, z80dart_cd_ba_r, z80dart_cd_ba_w)
AM_RANGE(0x0c, 0x0f) AM_DEVREADWRITE(Z80DART_TAG, z80dart_device, cd_ba_r, cd_ba_w)
ADDRESS_MAP_END
/***************************************************************************
@ -220,18 +220,18 @@ TIMER_DEVICE_CALLBACK_MEMBER(mtx_state::ctc_tick)
WRITE_LINE_MEMBER(mtx_state::ctc_trg1_w)
{
if (m_z80dart != NULL)
if (m_z80dart)
{
z80dart_rxca_w(m_z80dart, state);
z80dart_txca_w(m_z80dart, state);
m_z80dart->rxca_w(state);
m_z80dart->txca_w(state);
}
}
WRITE_LINE_MEMBER(mtx_state::ctc_trg2_w)
{
if (m_z80dart != NULL)
if (m_z80dart)
{
z80dart_rxtxcb_w(m_z80dart, state);
m_z80dart->rxtxcb_w(state);
}
}

2
src/mess/drivers/osbexec.c
View File

@ -214,7 +214,7 @@ static ADDRESS_MAP_START( osbexec_io, AS_IO, 8, osbexec_state )
AM_RANGE( 0x00, 0x03 ) AM_MIRROR( 0xff00 ) AM_DEVREADWRITE( "pia_0", pia6821_device, read, write) /* 6821 PIA @ UD12 */
/* 0x04 - 0x07 - 8253 @UD1 */
AM_RANGE( 0x08, 0x0B ) AM_MIRROR( 0xff00 ) AM_DEVREADWRITE_LEGACY("mb8877", wd17xx_r, wd17xx_w ) /* MB8877 @ UB17 input clock = 1MHz */
AM_RANGE( 0x0C, 0x0F ) AM_MIRROR( 0xff00 ) AM_DEVREADWRITE_LEGACY("sio", z80dart_ba_cd_r, z80dart_ba_cd_w ) /* SIO @ UD4 */
AM_RANGE( 0x0C, 0x0F ) AM_MIRROR( 0xff00 ) AM_DEVREADWRITE("sio", z80sio2_device, ba_cd_r, ba_cd_w ) /* SIO @ UD4 */
AM_RANGE( 0x10, 0x13 ) AM_MIRROR( 0xff00 ) AM_DEVREADWRITE( "pia_1", pia6821_device, read, write) /* 6821 PIA @ UD8 */
AM_RANGE( 0x14, 0x17 ) AM_MIRROR( 0xff00 ) AM_MASK( 0xff00 ) AM_READ(osbexec_kbd_r ) /* KBD */
AM_RANGE( 0x18, 0x1b ) AM_MIRROR( 0xff00 ) AM_READ(osbexec_rtc_r ) /* "RTC" @ UE13/UF13 */

2
src/mess/drivers/sun1.c
View File

@ -49,7 +49,7 @@
#include "emu.h"
#include "cpu/m68000/m68000.h"
#include "machine/upd7201.h"
#include "machine/z80dart.h"
#include "machine/terminal.h"

8
src/mess/drivers/super6.c
View File

@ -279,7 +279,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( super6_io, AS_IO, 8, super6_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x00, 0x03) AM_DEVREADWRITE_LEGACY(Z80DART_TAG, z80dart_ba_cd_r, z80dart_ba_cd_w)
AM_RANGE(0x00, 0x03) AM_DEVREADWRITE(Z80DART_TAG, z80dart_device, ba_cd_r, ba_cd_w)
AM_RANGE(0x04, 0x07) AM_DEVREADWRITE(Z80PIO_TAG, z80pio_device, read, write)
AM_RANGE(0x08, 0x0b) AM_DEVREADWRITE(Z80CTC_TAG, z80ctc_device, read, write)
AM_RANGE(0x0c, 0x0f) AM_DEVREADWRITE(WD2793_TAG, wd2793_t, read, write)
@ -449,8 +449,8 @@ static Z80PIO_INTERFACE( pio_intf )
WRITE_LINE_MEMBER( super6_state::fr_w )
{
z80dart_rxca_w(m_dart, state);
z80dart_txca_w(m_dart, state);
m_dart->rxca_w(state);
m_dart->txca_w(state);
m_ctc->trg1(state);
}
@ -459,7 +459,7 @@ static COM8116_INTERFACE( brg_intf )
{
DEVCB_NULL,
DEVCB_DRIVER_LINE_MEMBER(super6_state, fr_w),
DEVCB_DEVICE_LINE(Z80DART_TAG, z80dart_rxtxcb_w),
DEVCB_DEVICE_LINE_MEMBER(Z80DART_TAG, z80dart_device, rxtxcb_w),
COM8116_DIVISORS_16X_5_0688MHz, // receiver
COM8116_DIVISORS_16X_5_0688MHz // transmitter
};

12
src/mess/drivers/superslave.c
View File

@ -253,16 +253,16 @@ INPUT_PORTS_END
WRITE_LINE_MEMBER( superslave_state::fr_w )
{
z80dart_rxca_w(m_dart0, state);
z80dart_txca_w(m_dart0, state);
z80dart_rxca_w(m_dart1, state);
z80dart_txca_w(m_dart1, state);
m_dart0->rxca_w(state);
m_dart0->txca_w(state);
m_dart1->rxca_w(state);
m_dart1->txca_w(state);
}
WRITE_LINE_MEMBER( superslave_state::ft_w )
{
z80dart_rxtxcb_w(m_dart0, state);
z80dart_rxtxcb_w(m_dart1, state);
m_dart0->rxtxcb_w(state);
m_dart1->rxtxcb_w(state);
}
static COM8116_INTERFACE( dbrg_intf )

2
src/mess/drivers/tiki100.c
View File

@ -213,7 +213,7 @@ static ADDRESS_MAP_START( tiki100_io, AS_IO, 8, tiki100_state )
ADDRESS_MAP_UNMAP_HIGH
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x00, 0x00) AM_MIRROR(0x03) AM_READWRITE(keyboard_r, keyboard_w)
AM_RANGE(0x04, 0x07) AM_DEVREADWRITE_LEGACY(Z80DART_TAG, z80dart_cd_ba_r, z80dart_cd_ba_w)
AM_RANGE(0x04, 0x07) AM_DEVREADWRITE(Z80DART_TAG, z80dart_device, cd_ba_r, cd_ba_w)
AM_RANGE(0x08, 0x0b) AM_DEVREADWRITE(Z80PIO_TAG, z80pio_device, read, write)
AM_RANGE(0x0c, 0x0c) AM_MIRROR(0x03) AM_WRITE(video_mode_w)
AM_RANGE(0x10, 0x13) AM_DEVREADWRITE(FD1797_TAG, fd1797_t, read, write)

8
src/mess/drivers/trs80m2.c
View File

@ -329,7 +329,7 @@ static ADDRESS_MAP_START( z80_io, AS_IO, 8, trs80m2_state )
AM_RANGE(0xe4, 0xe7) AM_READWRITE(fdc_r, fdc_w)
AM_RANGE(0xef, 0xef) AM_WRITE(drvslt_w)
AM_RANGE(0xf0, 0xf3) AM_DEVREADWRITE(Z80CTC_TAG, z80ctc_device, read, write)
AM_RANGE(0xf4, 0xf7) AM_DEVREADWRITE_LEGACY(Z80SIO_TAG, z80dart_cd_ba_r, z80dart_cd_ba_w)
AM_RANGE(0xf4, 0xf7) AM_DEVREADWRITE(Z80SIO_TAG, z80sio0_device, cd_ba_r, cd_ba_w)
AM_RANGE(0xf8, 0xf8) AM_DEVREADWRITE_LEGACY(Z80DMA_TAG, z80dma_r, z80dma_w)
AM_RANGE(0xf9, 0xf9) AM_WRITE(rom_enable_w)
AM_RANGE(0xfc, 0xfc) AM_READ(keyboard_r) AM_DEVWRITE(MC6845_TAG, mc6845_device, address_w)
@ -688,9 +688,9 @@ TIMER_DEVICE_CALLBACK_MEMBER(trs80m2_state::ctc_tick)
static Z80CTC_INTERFACE( ctc_intf )
{
DEVCB_CPU_INPUT_LINE(Z80_TAG, INPUT_LINE_IRQ0), // interrupt handler
DEVCB_DEVICE_LINE(Z80SIO_TAG, z80dart_rxca_w), // ZC/TO0 callback
DEVCB_DEVICE_LINE(Z80SIO_TAG, z80dart_txca_w), // ZC/TO1 callback
DEVCB_DEVICE_LINE(Z80SIO_TAG, z80dart_rxtxcb_w) // ZC/TO2 callback
DEVCB_DEVICE_LINE_MEMBER(Z80SIO_TAG, z80dart_device, rxca_w), // ZC/TO0 callback
DEVCB_DEVICE_LINE_MEMBER(Z80SIO_TAG, z80dart_device, txca_w), // ZC/TO1 callback
DEVCB_DEVICE_LINE_MEMBER(Z80SIO_TAG, z80dart_device, rxtxcb_w) // ZC/TO2 callback
};

63
src/mess/drivers/victor9k.c
View File

@ -173,36 +173,27 @@ static const struct pit8253_config pit_intf =
static UPD7201_INTERFACE( mpsc_intf )
{
DEVCB_DEVICE_LINE_MEMBER(I8259A_TAG, pic8259_device, ir1_w), // interrupt
{
{
0, // receive clock
0, // transmit clock
DEVCB_NULL, // receive DRQ
DEVCB_NULL, // transmit DRQ
DEVCB_DEVICE_LINE_MEMBER(RS232_A_TAG, serial_port_device, rx),
DEVCB_DEVICE_LINE_MEMBER(RS232_A_TAG, serial_port_device, tx),
DEVCB_DEVICE_LINE_MEMBER(RS232_A_TAG, rs232_port_device, cts_r),
DEVCB_DEVICE_LINE_MEMBER(RS232_A_TAG, rs232_port_device, dcd_r),
DEVCB_DEVICE_LINE_MEMBER(RS232_A_TAG, rs232_port_device, rts_w),
DEVCB_DEVICE_LINE_MEMBER(RS232_A_TAG, rs232_port_device, dtr_w),
DEVCB_NULL, // wait
DEVCB_NULL // sync output
}, {
0, // receive clock
0, // transmit clock
DEVCB_NULL, // receive DRQ
DEVCB_NULL, // transmit DRQ
DEVCB_DEVICE_LINE_MEMBER(RS232_B_TAG, serial_port_device, rx),
DEVCB_DEVICE_LINE_MEMBER(RS232_B_TAG, serial_port_device, tx),
DEVCB_DEVICE_LINE_MEMBER(RS232_B_TAG, rs232_port_device, cts_r),
DEVCB_DEVICE_LINE_MEMBER(RS232_B_TAG, rs232_port_device, dcd_r),
DEVCB_DEVICE_LINE_MEMBER(RS232_B_TAG, rs232_port_device, rts_w),
DEVCB_DEVICE_LINE_MEMBER(RS232_B_TAG, rs232_port_device, dtr_w),
DEVCB_NULL, // wait
DEVCB_NULL // sync output
}
}
0, 0, 0, 0,
DEVCB_DEVICE_LINE_MEMBER(RS232_A_TAG, serial_port_device, rx),
DEVCB_DEVICE_LINE_MEMBER(RS232_A_TAG, serial_port_device, tx),
DEVCB_DEVICE_LINE_MEMBER(RS232_A_TAG, rs232_port_device, dtr_w),
DEVCB_DEVICE_LINE_MEMBER(RS232_A_TAG, rs232_port_device, rts_w),
DEVCB_NULL,
DEVCB_NULL,
DEVCB_DEVICE_LINE_MEMBER(RS232_B_TAG, serial_port_device, rx),
DEVCB_DEVICE_LINE_MEMBER(RS232_B_TAG, serial_port_device, tx),
DEVCB_DEVICE_LINE_MEMBER(RS232_B_TAG, rs232_port_device, dtr_w),
DEVCB_DEVICE_LINE_MEMBER(RS232_B_TAG, rs232_port_device, rts_w),
DEVCB_NULL,
DEVCB_NULL,
DEVCB_DEVICE_LINE_MEMBER(I8259A_TAG, pic8259_device, ir1_w),
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL
};
// MC6852 Interface
@ -888,10 +879,10 @@ SLOT_INTERFACE_END
static const rs232_port_interface rs232a_intf =
{
DEVCB_NULL,
DEVCB_DEVICE_LINE_MEMBER(UPD7201_TAG, z80dart_device, dcda_w),
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL
DEVCB_DEVICE_LINE_MEMBER(UPD7201_TAG, z80dart_device, ria_w),
DEVCB_DEVICE_LINE_MEMBER(UPD7201_TAG, z80dart_device, ctsa_w)
};
@ -902,10 +893,10 @@ static const rs232_port_interface rs232a_intf =
static const rs232_port_interface rs232b_intf =
{
DEVCB_NULL,
DEVCB_DEVICE_LINE_MEMBER(UPD7201_TAG, z80dart_device, dcdb_w),
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL
DEVCB_DEVICE_LINE_MEMBER(UPD7201_TAG, z80dart_device, rib_w),
DEVCB_DEVICE_LINE_MEMBER(UPD7201_TAG, z80dart_device, ctsb_w)
};
// Machine Initialization

4
src/mess/drivers/x1.c
View File

@ -1682,7 +1682,7 @@ READ8_MEMBER( x1_state::x1turbo_io_r )
else if(offset >= 0x1a00 && offset <= 0x1aff) { return machine().device<i8255_device>("ppi8255_0")->read(space, (offset-0x1a00) & 3); }
else if(offset >= 0x1b00 && offset <= 0x1bff) { return machine().device<ay8910_device>("ay")->data_r(space, 0); }
else if(offset >= 0x1f80 && offset <= 0x1f8f) { return z80dma_r(machine().device("dma"), space, 0); }
else if(offset >= 0x1f90 && offset <= 0x1f93) { return z80dart_ba_cd_r(machine().device("sio"), space, (offset-0x1f90) & 3); }
else if(offset >= 0x1f90 && offset <= 0x1f93) { return machine().device<z80sio0_device>("sio")->ba_cd_r(space, (offset-0x1f90) & 3); }
else if(offset >= 0x1f98 && offset <= 0x1f9f) { printf("Extended SIO/CTC read %04x\n",offset); return 0xff; }
else if(offset >= 0x1fa0 && offset <= 0x1fa3) { return m_ctc->read(space,offset-0x1fa0); }
else if(offset >= 0x1fa8 && offset <= 0x1fab) { return m_ctc->read(space,offset-0x1fa8); }
@ -1735,7 +1735,7 @@ WRITE8_MEMBER( x1_state::x1turbo_io_w )
else if(offset >= 0x1d00 && offset <= 0x1dff) { x1_rom_bank_1_w(space,0,data); }
else if(offset >= 0x1e00 && offset <= 0x1eff) { x1_rom_bank_0_w(space,0,data); }
else if(offset >= 0x1f80 && offset <= 0x1f8f) { z80dma_w(machine().device("dma"), space, 0,data); }
else if(offset >= 0x1f90 && offset <= 0x1f93) { z80dart_ba_cd_w(machine().device("sio"), space, (offset-0x1f90) & 3,data); }
else if(offset >= 0x1f90 && offset <= 0x1f93) { machine().device<z80sio0_device>("sio")->ba_cd_w(space, (offset-0x1f90) & 3,data); }
else if(offset >= 0x1f98 && offset <= 0x1f9f) { printf("Extended SIO/CTC write %04x %02x\n",offset,data); }
else if(offset >= 0x1fa0 && offset <= 0x1fa3) { m_ctc->write(space,offset-0x1fa0,data); }
else if(offset >= 0x1fa8 && offset <= 0x1fab) { m_ctc->write(space,offset-0x1fa8,data); }

9
src/mess/drivers/xerox820.c
View File

@ -153,8 +153,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( xerox820_io, AS_IO, 8, xerox820_state )
AM_RANGE(0x00, 0x00) AM_MIRROR(0xff03) AM_DEVWRITE(COM8116_TAG, com8116_device, str_w)
AM_RANGE(0x04, 0x04) AM_MIRROR(0xff02) AM_DEVREADWRITE_LEGACY(Z80SIO_TAG, z80dart_d_r, z80dart_d_w)
AM_RANGE(0x05, 0x05) AM_MIRROR(0xff02) AM_DEVREADWRITE_LEGACY(Z80SIO_TAG, z80dart_c_r, z80dart_c_w)
AM_RANGE(0x04, 0x07) AM_MIRROR(0xff00) AM_DEVREADWRITE(Z80SIO_TAG, z80sio0_device, ba_cd_r, ba_cd_w)
AM_RANGE(0x08, 0x0b) AM_MIRROR(0xff00) AM_DEVREADWRITE(Z80PIO_GP_TAG, z80pio_device, read_alt, write_alt)
AM_RANGE(0x0c, 0x0c) AM_MIRROR(0xff03) AM_DEVWRITE(COM8116_TAG, com8116_device, stt_w)
AM_RANGE(0x10, 0x13) AM_MIRROR(0xff00) AM_READWRITE(fdc_r, fdc_w)
@ -499,13 +498,13 @@ void xerox820_state::fdc_drq_w(bool state)
WRITE_LINE_MEMBER( xerox820_state::fr_w )
{
z80dart_rxca_w(m_sio, state);
z80dart_txca_w(m_sio, state);
m_sio->rxca_w(state);
m_sio->txca_w(state);
}
WRITE_LINE_MEMBER( xerox820_state::ft_w )
{
z80dart_rxtxcb_w(m_sio, state);
m_sio->rxtxcb_w(state);
}
static COM8116_INTERFACE( com8116_intf )

2
src/mess/includes/abc80x.h
View File

@ -97,7 +97,7 @@ public:
required_device<legacy_cpu_device> m_maincpu;
required_device<z80ctc_device> m_ctc;
required_device<z80dart_device> m_dart;
required_device<z80dart_device> m_sio;
required_device<z80sio2_device> m_sio;
optional_device<discrete_sound_device> m_discrete;
optional_device<cassette_image_device> m_cassette;
required_device<ram_device> m_ram;

5
src/mess/includes/apricotf.h
View File

@ -51,11 +51,12 @@ public:
m_ctc_int(CLEAR_LINE),
m_sio_int(CLEAR_LINE),
m_p_scrollram(*this, "p_scrollram"),
m_p_paletteram(*this, "p_paletteram"){ }
m_p_paletteram(*this, "p_paletteram")
{ }
required_device<cpu_device> m_maincpu;
required_device<z80ctc_device> m_ctc;
required_device<z80dart_device> m_sio;
required_device<z80sio2_device> m_sio;
required_device<wd2797_device> m_fdc;
required_device<legacy_floppy_image_device> m_floppy0;
required_device<centronics_device> m_centronics;

2
src/mess/includes/bw12.h
View File

@ -58,7 +58,7 @@ public:
required_device<cpu_device> m_maincpu;
required_device<pia6821_device> m_pia;
required_device<z80dart_device> m_sio;
required_device<z80sio0_device> m_sio;
required_device<upd765a_device> m_fdc;
required_device<ay3600_device> m_kbc;
required_device<mc6845_device> m_crtc;

2
src/mess/includes/mikromik.h
View File

@ -11,7 +11,7 @@
#include "machine/pit8253.h"
#include "machine/ram.h"
#include "machine/serial.h"
#include "machine/upd7201.h"
#include "machine/z80dart.h"
#include "machine/upd765.h"
#include "sound/speaker.h"
#include "video/i8275x.h"

14
src/mess/includes/mtx.h
View File

@ -10,6 +10,7 @@
#include "imagedev/snapquik.h"
#include "imagedev/cassette.h"
#include "machine/ctronics.h"
#include "machine/z80dart.h"
#include "machine/z80ctc.h"
#include "sound/sn76496.h"
#include "machine/ram.h"
@ -31,12 +32,18 @@ public:
: driver_device(mconfig, type, tag),
m_maincpu(*this, Z80_TAG),
m_sn(*this, SN76489A_TAG),
m_z80ctc(*this, Z80CTC_TAG),
m_z80dart(*this, Z80DART_TAG),
m_cassette(*this, "cassette"),
m_ram(*this, RAM_TAG)
{ }
required_device<cpu_device> m_maincpu;
required_device<sn76489a_device> m_sn;
required_device<z80ctc_device> m_z80ctc;
optional_device<z80dart_device> m_z80dart;
required_device<cassette_image_device> m_cassette;
required_device<ram_device> m_ram;
/* keyboard state */
UINT8 m_key_sense;
@ -48,13 +55,6 @@ public:
/* sound state */
UINT8 m_sound_latch;
/* devices */
z80ctc_device *m_z80ctc;
device_t *m_z80dart;
required_device<cassette_image_device> m_cassette;
required_device<ram_device> m_ram;
centronics_device *m_centronics;
/* timers */
device_t *m_cassette_timer;

2
src/mess/includes/victor9k.h
View File

@ -15,7 +15,7 @@
#include "machine/pit8253.h"
#include "machine/pic8259.h"
#include "machine/serial.h"
#include "machine/upd7201.h"
#include "machine/z80dart.h"
#include "machine/victor9kb.h"
#include "sound/hc55516.h"
#include "video/mc6845.h"

2
src/mess/includes/xerox820.h
View File

@ -69,7 +69,7 @@ public:
required_device<cpu_device> m_maincpu;
required_device<z80pio_device> m_kbpio;
required_device<z80ctc_device> m_ctc;
required_device<z80dart_device> m_sio;
required_device<z80sio0_device> m_sio;
required_device<wd_fdc_t> m_fdc;
required_device<ram_device> m_ram;
required_device<floppy_connector> m_floppy0;

4
src/mess/machine/mtx.c
View File

@ -368,10 +368,6 @@ MACHINE_START_MEMBER(mtx_state,mtx512)
{
ram_device *messram = m_ram;
/* find devices */
m_z80ctc = machine().device<z80ctc_device>(Z80CTC_TAG);
m_z80dart = machine().device(Z80DART_TAG);
/* configure memory */
membank("bank1")->set_base(memregion("user1")->base());
membank("bank2")->configure_entries(0, 8, memregion("user2")->base(), 0x2000);

57
src/mess/machine/tf20.c
View File

@ -86,36 +86,27 @@ ioport_constructor epson_tf20_device::device_input_ports() const
static UPD7201_INTERFACE( tf20_upd7201_intf )
{
DEVCB_NULL, /* interrupt: nc */
{
{
XTAL_CR2 / 128, /* receive clock: 38400 baud (default) */
XTAL_CR2 / 128, /* transmit clock: 38400 baud (default) */
DEVCB_NULL, /* receive DRQ */
DEVCB_NULL, /* transmit DRQ */
DEVCB_NULL, /* receive data */
DEVCB_NULL, /* transmit data */
DEVCB_NULL, /* clear to send */
DEVCB_LINE_GND, /* data carrier detect */
DEVCB_NULL, /* ready to send */
DEVCB_NULL, /* data terminal ready */
DEVCB_NULL, /* wait */
DEVCB_NULL /* sync output: nc */
}, {
XTAL_CR2 / 128, /* receive clock: 38400 baud (default) */
XTAL_CR2 / 128, /* transmit clock: 38400 baud (default) */
DEVCB_NULL, /* receive DRQ: nc */
DEVCB_NULL, /* transmit DRQ */
DEVCB_NULL, /* receive data */
DEVCB_NULL, /* transmit data */
DEVCB_LINE_GND, /* clear to send */
DEVCB_LINE_GND, /* data carrier detect */
DEVCB_NULL, /* ready to send */
DEVCB_NULL, /* data terminal ready: nc */
DEVCB_NULL, /* wait */
DEVCB_NULL /* sync output: nc */
}
}
XTAL_CR2 / 128, XTAL_CR2 / 128, XTAL_CR2 / 128, XTAL_CR2 / 128,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL
};
static SLOT_INTERFACE_START( tf20_floppies )
@ -262,7 +253,7 @@ void epson_tf20_device::fdc_irq(bool state)
void epson_tf20_device::tx_w(int level)
{
logerror("%s: tx_w(%d)\n", tag(), level);
m_mpsc->rxda_w(level);
//m_mpsc->rxda_w(level);
}
@ -284,7 +275,7 @@ void epson_tf20_device::pout_w(int level)
int epson_tf20_device::rx_r()
{
logerror("%s: rx_r\n", tag());
return m_mpsc->txda_r();
return 1;//m_mpsc->txda_r();
}
@ -295,7 +286,7 @@ int epson_tf20_device::rx_r()
int epson_tf20_device::pin_r()
{
logerror("%s: pin_r\n", tag());
return m_mpsc->dtra_r();
return 1;//m_mpsc->dtra_r();
}

2
src/mess/machine/tf20.h
View File

@ -18,7 +18,7 @@
#include "cpu/z80/z80.h"
#include "machine/ram.h"
#include "machine/upd765.h"
#include "machine/upd7201.h"
#include "machine/z80dart.h"
#include "machine/epson_sio.h"

4
src/mess/machine/wangpc_rtc.c
View File

@ -68,7 +68,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( wangpc_rtc_io, AS_IO, 8, wangpc_rtc_device )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x00, 0x03) AM_DEVREADWRITE_LEGACY(Z80SIO_TAG, z80dart_cd_ba_r, z80dart_cd_ba_w)
AM_RANGE(0x00, 0x03) AM_DEVREADWRITE(Z80SIO_TAG, z80sio0_device, cd_ba_r, cd_ba_w)
AM_RANGE(0x10, 0x1f) AM_DEVREADWRITE(AM9517A_TAG, am9517a_device, read, write)
AM_RANGE(0x20, 0x23) AM_DEVREADWRITE(Z80CTC_0_TAG, z80ctc_device, read, write)
AM_RANGE(0x30, 0x30) //AM_WRITE(clear_char_w)
@ -190,7 +190,7 @@ static MACHINE_CONFIG_FRAGMENT( wangpc_rtc )
MCFG_I8237_ADD(AM9517A_TAG, 2000000, dmac_intf)
MCFG_Z80CTC_ADD(Z80CTC_0_TAG, 2000000, ctc0_intf)
MCFG_Z80CTC_ADD(Z80CTC_1_TAG, 2000000, ctc1_intf)
MCFG_Z80DART_ADD(Z80SIO_TAG, 2000000, sio_intf)
MCFG_Z80SIO0_ADD(Z80SIO_TAG, 2000000, sio_intf)
MACHINE_CONFIG_END

2
src/mess/video/abc800.c
View File

@ -282,7 +282,7 @@ static MC6845_INTERFACE( crtc_intf )
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_DEVICE_LINE(Z80DART_TAG, z80dart_rib_w),
DEVCB_DEVICE_LINE_MEMBER(Z80DART_TAG, z80dart_device, rib_w),
NULL
};