mirror of
https://github.com/holub/mame
synced 2025-06-03 11:26:56 +03:00
gameboy: more updates to the cart emulation [Tauwasser]
- fixed some MBC1, MBC2 details
- added MMM01 notes on registers
- fixed Sachen MMC1 implementation so that Sachen logo
is properly displayed
- started work on the emulation of Sachen MMC2 mapper
This commit is contained in:
etabeta78
parent
5ba57c6cde
commit
05ac233c0a
@ -23524,6 +23524,18 @@ These were produced between 2000 and 2001 by Rocket Games, run by Datel Design
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</part>
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</software>
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<software name="4in1_01c">
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<description>4 in 1 (4B-001)</description>
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<year>20??</year>
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<publisher>Sachen</publisher>
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<part name="cart" interface="gameboy_cart">
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<feature name="slot" value="rom_sachen1" />
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<dataarea name="rom" size="524288">
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<rom name="4b-001.gbc" size="524288" crc="42a2fdf8" sha1="79a4faddfd1aca397e56d7895e45b1bc12900dab" offset="000000" />
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</dataarea>
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</part>
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</software>
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<software name="mc_8in1">
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<description>8 in 1 (Tw)</description>
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<year>19??</year>
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@ -26,8 +26,8 @@ const device_type GB_ROM_MBC6 = &device_creator<gb_rom_mbc6_device>;
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const device_type GB_ROM_MBC7 = &device_creator<gb_rom_mbc7_device>;
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const device_type GB_ROM_M161_M12 = &device_creator<gb_rom_m161_device>;
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const device_type GB_ROM_MMM01 = &device_creator<gb_rom_mmm01_device>;
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const device_type GB_ROM_SACHEN1 = &device_creator<gb_rom_sachen1_device>;
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const device_type GB_ROM_SACHEN2 = &device_creator<gb_rom_sachen1_device>; // Just a placeholder for the moment...
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const device_type GB_ROM_SACHEN1 = &device_creator<gb_rom_sachen_mmc1_device>;
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const device_type GB_ROM_SACHEN2 = &device_creator<gb_rom_sachen_mmc2_device>;
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const device_type GB_ROM_188IN1 = &device_creator<gb_rom_188in1_device>;
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const device_type GB_ROM_SINTAX = &device_creator<gb_rom_sintax_device>;
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const device_type GB_ROM_CHONGWU = &device_creator<gb_rom_chongwu_device>;
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@ -97,8 +97,18 @@ gb_rom_mmm01_device::gb_rom_mmm01_device(const machine_config &mconfig, const ch
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{
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}
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gb_rom_sachen1_device::gb_rom_sachen1_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: gb_rom_mbc1_device(mconfig, GB_ROM_SACHEN1, "GB Sachen MMC1 Carts", tag, owner, clock, "gb_rom_sachen1", __FILE__)
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gb_rom_sachen_mmc1_device::gb_rom_sachen_mmc1_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: gb_rom_mbc_device(mconfig, GB_ROM_SACHEN1, "GB Sachen MMC1 Carts", tag, owner, clock, "gb_rom_sachen1", __FILE__)
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{
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}
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gb_rom_sachen_mmc1_device::gb_rom_sachen_mmc1_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source)
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: gb_rom_mbc_device(mconfig, type, name, tag, owner, clock, shortname, source)
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{
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}
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gb_rom_sachen_mmc2_device::gb_rom_sachen_mmc2_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: gb_rom_sachen_mmc1_device(mconfig, GB_ROM_SACHEN2, "GB Sachen MMC2 Carts", tag, owner, clock, "gb_rom_sachen2", __FILE__)
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{
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}
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@ -233,18 +243,40 @@ void gb_rom_mmm01_device::device_reset()
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m_reg = 0;
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}
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void gb_rom_sachen1_device::device_start()
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void gb_rom_sachen_mmc1_device::device_start()
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{
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shared_start();
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save_item(NAME(m_base_bank));
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save_item(NAME(m_mask));
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save_item(NAME(m_mode));
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save_item(NAME(m_unlock_cnt));
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}
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void gb_rom_sachen1_device::device_reset()
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void gb_rom_sachen_mmc1_device::device_reset()
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{
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shared_reset();
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m_base_bank = 0;
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m_mask = 0;
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m_base_bank = 0x00;
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m_mask = 0x00;
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m_mode = MODE_LOCKED;
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m_unlock_cnt = 0x00;
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}
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void gb_rom_sachen_mmc2_device::device_start()
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{
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shared_start();
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save_item(NAME(m_base_bank));
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save_item(NAME(m_mask));
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save_item(NAME(m_mode));
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save_item(NAME(m_unlock_cnt));
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}
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void gb_rom_sachen_mmc2_device::device_reset()
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{
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shared_reset();
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m_base_bank = 0x00;
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m_mask = 0x00;
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m_mode = MODE_LOCKED_DMG;
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m_unlock_cnt = 0x00;
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}
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void gb_rom_sintax_device::device_start()
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@ -310,18 +342,18 @@ WRITE8_MEMBER(gb_rom_mbc_device::write_ram)
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READ8_MEMBER(gb_rom_mbc1_device::read_rom)
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{
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if (offset < 0x4000)
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{
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if (offset & 0x4000) /* RB1 */
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return m_rom[rom_bank_map[(m_ram_bank << (5 + m_shift)) | m_latch_bank2] * 0x4000 + (offset & 0x3fff)];
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else
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{ /* RB0 */
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int bank = (m_mode == MODE_4M_256k) ? (m_ram_bank << (5 + m_shift)) : 0;
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return m_rom[rom_bank_map[bank] * 0x4000 + (offset & 0x3fff)];
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}
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else
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return m_rom[rom_bank_map[(m_ram_bank << (5 + m_shift)) | m_latch_bank2] * 0x4000 + (offset & 0x3fff)];
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}
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WRITE8_MEMBER(gb_rom_mbc1_device::write_bank)
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{
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// the mapper only uses inputs A13-A15
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// the mapper only uses inputs A15..A13
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switch (offset & 0xe000)
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{
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case 0x0000: // RAM Enable Register
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@ -395,7 +427,7 @@ WRITE8_MEMBER(gb_rom_mbc2_device::write_bank)
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READ8_MEMBER(gb_rom_mbc2_device::read_ram)
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{
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if (!m_ram.empty() && m_ram_enable)
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return m_ram[ram_bank_map[m_ram_bank] * 0x2000 + (offset & 0x1fff)];
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return m_ram[ram_bank_map[m_ram_bank] * 0x2000 + (offset & 0x01ff)] | 0xF0;
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else
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return 0xff;
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}
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@ -403,7 +435,7 @@ READ8_MEMBER(gb_rom_mbc2_device::read_ram)
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WRITE8_MEMBER(gb_rom_mbc2_device::write_ram)
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{
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if (!m_ram.empty() && m_ram_enable)
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m_ram[ram_bank_map[m_ram_bank] * 0x2000 + (offset & 0x1fff)] = data;
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m_ram[ram_bank_map[m_ram_bank] * 0x2000 + (offset & 0x01ff)] = data & 0x0F;
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}
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@ -661,6 +693,14 @@ WRITE8_MEMBER(gb_rom_m161_device::write_bank)
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// MMM01
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// This mmm01 implementation is mostly guess work, no clue how correct it all is
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/* TODO: This implementation is wrong. Tauwasser
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*
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* Register 0: Map Latch, AA Mask, RAM Enable
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* Register 1: EA1..EA0, RA18..RA14
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* Register 2: ??, AA18..AA15, AA14..AA13
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* Register 3: AA Multiplex, RA Mask, ???, MBC1 Mode
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*
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*/
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READ8_MEMBER(gb_rom_mmm01_device::read_rom)
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{
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@ -704,37 +744,140 @@ WRITE8_MEMBER(gb_rom_mmm01_device::write_bank)
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}
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}
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// Sachen MMC1
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READ8_MEMBER(gb_rom_sachen1_device::read_rom)
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READ8_MEMBER(gb_rom_sachen_mmc1_device::read_rom)
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{
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if (offset < 0x4000)
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return m_rom[rom_bank_map[(m_base_bank & m_mask) | (m_latch_bank & ~m_mask)] * 0x4000 + (offset & 0x3fff)];
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UINT16 off_edit = offset;
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/* Wait for 0x31 transitions of A15 (hi -> lo), i.e. ROM accesses; A15 = HI while in bootstrap */
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/* This is 0x31 transitions, because we increment counter _after_ checking it */
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if (m_unlock_cnt == 0x30)
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m_mode = MODE_UNLOCKED;
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else
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m_unlock_cnt++;
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/* Logo Switch */
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if (m_mode == MODE_LOCKED)
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off_edit |= 0x80;
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/* Header Un-Scramble */
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if ((off_edit & 0xFF00) == 0x0100) {
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off_edit &= 0xFFAC;
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off_edit |= ((offset >> 6) & 0x01) << 0;
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off_edit |= ((offset >> 4) & 0x01) << 1;
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off_edit |= ((offset >> 1) & 0x01) << 4;
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off_edit |= ((offset >> 0) & 0x01) << 6;
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}
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//logerror("read from %04X (%04X)\n", offset, off_edit);
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if (offset & 0x4000) /* RB1 */
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return m_rom[rom_bank_map[(m_base_bank & m_mask) | (m_latch_bank2 & ~m_mask)] * 0x4000 + (offset & 0x3fff)];
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else /* RB0 */
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return m_rom[rom_bank_map[(m_base_bank & m_mask) | (m_latch_bank & ~m_mask)] * 0x4000 + (off_edit & 0x3fff)];
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}
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WRITE8_MEMBER(gb_rom_sachen1_device::write_bank)
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WRITE8_MEMBER(gb_rom_sachen_mmc1_device::write_bank)
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{
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if (offset < 0x2000) // Base ROM Bank register
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/* Only A15..A6, A4, A1..A0 are connected */
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/* We only decode upper three bits */
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switch ((offset & 0xFFD3) & 0xE000)
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{
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if ((m_latch_bank2 & 0x30) == 0x30 && data)
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m_base_bank = data & 0x0f;
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//logerror("write to base bank %X - %X\n", data, (m_base_bank & m_mask) | (m_latch_bank2 & ~m_mask));
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case 0x0000: /* Base ROM Bank Register */
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if ((m_latch_bank2 & 0x30) == 0x30)
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m_base_bank = data;
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//logerror("write to base bank %X - %X\n", data, (m_base_bank & m_mask) | (m_latch_bank2 & ~m_mask));
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break;
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case 0x2000: /* ROM Bank Register */
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m_latch_bank2 = data ? data : 0x01;
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//logerror("write to latch %X - %X\n", data, (m_base_bank & m_mask) | (m_latch_bank2 & ~m_mask));
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break;
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case 0x4000: /* ROM Bank Mask Register */
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if ((m_latch_bank2 & 0x30) == 0x30)
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m_mask = data;
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//logerror("write to mask %X - %X\n", data, (m_base_bank & m_mask) | (m_latch_bank2 & ~m_mask));
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break;
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case 0x6000:
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/* nothing happens when writing to 0x6000-0x7fff, as verified by Tauwasser */
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break;
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default:
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//logerror("write to unknown/unmapped area %04X <= %02X\n", offset, data);
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/* did not extensively test other unlikely ranges */
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break;
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}
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else if (offset < 0x4000) // ROM Bank Register
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{
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m_latch_bank2 = data ? data : 1;
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//logerror("write to latch %X - %X\n", data, (m_base_bank & m_mask) | (m_latch_bank2 & ~m_mask));
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}
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// Sachen MMC2
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READ8_MEMBER(gb_rom_sachen_mmc2_device::read_rom)
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{
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UINT16 off_edit = offset;
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/* Wait for 0x30 transitions of A15 (lo -> hi), i.e. ROM accesses; A15 = HI while in bootstrap */
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/* This is 0x30 transitions, because we increment counter _after_ checking it, but A15 lo -> hi*/
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/* transition means first read (hi -> lo transition) must not count */
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if (m_unlock_cnt == 0x30 && m_mode == MODE_LOCKED_DMG) {
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m_mode = MODE_LOCKED_CGB;
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m_unlock_cnt = 0x00;
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} else if (m_unlock_cnt == 0x30 && m_mode == MODE_LOCKED_CGB) {
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m_mode = MODE_UNLOCKED;
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}
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else if (offset < 0x6000) // ROM bank mask register
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{
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if ((m_latch_bank2 & 0x30) == 0x30)
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m_mask = data;
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//logerror("write to mask %X - %X\n", data, (m_base_bank & m_mask) | (m_latch_bank2 & ~m_mask));
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if (m_unlock_cnt != 0x30)
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m_unlock_cnt++;
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/* Logo Switch */
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if (m_mode == MODE_LOCKED_CGB)
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off_edit |= 0x80;
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/* Header Un-Scramble */
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if ((off_edit & 0xFF00) == 0x0100) {
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off_edit &= 0xFFAC;
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off_edit |= ((offset >> 6) & 0x01) << 0;
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off_edit |= ((offset >> 4) & 0x01) << 1;
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off_edit |= ((offset >> 1) & 0x01) << 4;
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off_edit |= ((offset >> 0) & 0x01) << 6;
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}
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// nothing happens when writing to 0x6000-0x7fff, as verified by Tauwasser
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//logerror("read from %04X (%04X) cnt: %02X\n", offset, off_edit, m_unlock_cnt);
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if (offset & 0x4000) /* RB1 */
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return m_rom[rom_bank_map[(m_base_bank & m_mask) | (m_latch_bank2 & ~m_mask)] * 0x4000 + (offset & 0x3fff)];
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else /* RB0 */
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return m_rom[rom_bank_map[(m_base_bank & m_mask) | (m_latch_bank & ~m_mask)] * 0x4000 + (off_edit & 0x3fff)];
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}
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READ8_MEMBER(gb_rom_sachen_mmc2_device::read_ram)
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{
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if (m_mode == MODE_LOCKED_DMG) {
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m_unlock_cnt = 0x00;
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m_mode = MODE_LOCKED_CGB;
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}
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return 0xFF;
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}
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WRITE8_MEMBER(gb_rom_sachen_mmc2_device::write_ram)
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{
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if (m_mode == MODE_LOCKED_DMG) {
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m_unlock_cnt = 0x00;
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m_mode = MODE_LOCKED_CGB;
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}
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}
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@ -191,14 +191,20 @@ public:
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UINT8 m_bank_mask, m_bank, m_reg;
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};
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// ======================> gb_rom_sachen1_device
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// ======================> gb_rom_sachen_mmc1_device
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class gb_rom_sachen1_device : public gb_rom_mbc1_device
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class gb_rom_sachen_mmc1_device : public gb_rom_mbc_device
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{
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public:
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enum {
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MODE_LOCKED,
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MODE_UNLOCKED
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};
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// construction/destruction
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gb_rom_sachen1_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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gb_rom_sachen_mmc1_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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gb_rom_sachen_mmc1_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
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// device-level overrides
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virtual void device_start();
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@ -209,7 +215,32 @@ public:
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virtual DECLARE_READ8_MEMBER(read_ram) { return 0xff; }
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virtual DECLARE_WRITE8_MEMBER(write_ram) { }
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UINT8 m_base_bank, m_mask;
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UINT8 m_base_bank, m_mask, m_mode, m_unlock_cnt;
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};
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// ======================> gb_rom_sachen_mmc2_device
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class gb_rom_sachen_mmc2_device : public gb_rom_sachen_mmc1_device
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{
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public:
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enum {
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MODE_LOCKED_DMG,
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MODE_LOCKED_CGB,
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MODE_UNLOCKED
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};
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// construction/destruction
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gb_rom_sachen_mmc2_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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// device-level overrides
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virtual void device_start();
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virtual void device_reset();
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virtual DECLARE_READ8_MEMBER(read_rom);
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virtual DECLARE_READ8_MEMBER(read_ram);
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virtual DECLARE_WRITE8_MEMBER(write_ram);
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};
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// ======================> gb_rom_188in1_device
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