m740: Fix cycle timings for CLB/SEB ($zz), BBC/BBS (all modes) & RRF

This commit is contained in:
AJR 2020-10-28 16:40:39 -04:00
parent d8ece59cc7
commit 05e1ead028

View File

@ -43,6 +43,7 @@ seb_bac
clb_biz
TMP = read_pc();
TMP2 = read(TMP);
read(TMP);
TMP2 = do_clb(TMP2, (IR>>5) & 7);
write(TMP, TMP2);
prefetch();
@ -50,6 +51,7 @@ clb_biz
seb_biz
TMP = read_pc();
TMP2 = read(TMP);
read(TMP);
TMP2 = do_seb(TMP2, (IR>>5) & 7);
write(TMP, TMP2);
prefetch();
@ -57,42 +59,68 @@ seb_biz
bbc_bzr
TMP = read_pc();
TMP2 = read(TMP);
TMP = read_pc();
read_pc_noinc();
if(!(TMP2 & (1 << ((IR>>5) & 7)))) {
TMP = read_pc_noinc();
read_arg(set_l(PC, PC+1));
PC++;
read_arg(set_l(PC, PC+int8_t(TMP)));
PC += int8_t(TMP);
} else {
read_pc();
}
prefetch();
bbs_bzr
TMP = read_pc();
TMP2 = read(TMP);
TMP = read_pc();
read_pc_noinc();
if(TMP2 & (1 << ((IR>>5) & 7))) {
TMP = read_pc_noinc();
read_arg(set_l(PC, PC+1));
PC++;
read_arg(set_l(PC, PC+int8_t(TMP)));
PC += int8_t(TMP);
} else {
read_pc();
}
prefetch();
bbc_bar
TMP = read_pc();
read_pc_noinc();
read_pc_noinc();
if(!(A & (1 << ((IR>>5) & 7)))) {
TMP = read_pc_noinc();
read_arg(set_l(PC, PC+1));
PC++;
read_arg(set_l(PC, PC+int8_t(TMP)));
PC += int8_t(TMP);
} else {
read_pc();
}
prefetch();
bbs_bar
TMP = read_pc();
read_pc_noinc();
read_pc_noinc();
if(A & (1 << ((IR>>5) & 7))) {
TMP = read_pc_noinc();
read_arg(set_l(PC, PC+1));
PC++;
read_arg(set_l(PC, PC+int8_t(TMP)));
PC += int8_t(TMP);
} else {
read_pc();
}
prefetch();
rrf_zpg
TMP = read_pc();
TMP2 = read(TMP);
read(TMP);
read(TMP);
read(TMP);
read(TMP);
TMP2 = do_rrf(TMP2);
write(TMP, TMP2);
prefetch();