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https://github.com/holub/mame
synced 2025-07-01 08:18:59 +03:00
Improved irq routine
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parent
67b59583c9
commit
06514dbcc6
@ -191,8 +191,7 @@ public:
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UINT32 screen_update__3do(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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private:
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void m_3do_request_fiq0(UINT32 irq_req);
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void m_3do_request_fiq1(UINT32 irq_req);
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void m_3do_request_fiq(UINT32 irq_req, UINT8 type);
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};
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/*----------- defined in machine/3do.c -----------*/
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@ -61,14 +61,14 @@ Expansion bus stuff:
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#define LOG(x) do { if (VERBOSE) printf x; } while (0)
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/*
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0x80000000 Second Priority (?)
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0x80000000 Second Priority
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0x40000000 SW irq
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0x20000000 DMA<->EXP
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0x1fff0000 DMA RAM->DSPP *
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0x0000f000 DMA DSPP->RAM *
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0x00000800 DSPP
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0x00000400 Timer 1
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0x00000200 Timer 3
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0x00000200 Timer 3 <- needed to surpass current hang point
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0x00000100 Timer 5
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0x00000080 Timer 7
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0x00000040 Timer 9
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@ -79,15 +79,23 @@ Expansion bus stuff:
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0x00000002 Vertical 1
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0x00000001 Vertical 0
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*/
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void _3do_state::m_3do_request_fiq0(UINT32 irq_req)
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void _3do_state::m_3do_request_fiq(UINT32 irq_req, UINT8 type)
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{
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m_clio.irq0 |= irq_req;
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if(type)
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m_clio.irq1 |= irq_req;
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else
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m_clio.irq0 |= irq_req;
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if(m_clio.irq0 & m_clio.irq0_enable)
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m_maincpu->set_input_line(ARM7_FIRQ_LINE, ASSERT_LINE);
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if(m_clio.irq1)
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m_clio.irq0 |= 1 << 31; // Second Priority
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else
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m_clio.irq0 &= ~(1 << 31);
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if((m_clio.irq0 & m_clio.irq0_enable) == 0)
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m_maincpu->set_input_line(ARM7_FIRQ_LINE, CLEAR_LINE);
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if((m_clio.irq0 & m_clio.irq0_enable) || (m_clio.irq1 & m_clio.irq1_enable))
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{
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printf("Go irq %08x & %08x %08x & %08x\n",m_clio.irq0, m_clio.irq0_enable, m_clio.irq1, m_clio.irq1_enable);
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generic_pulse_irq_line(m_maincpu, ARM7_FIRQ_LINE, 1);
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}
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}
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/*
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@ -103,16 +111,6 @@ void _3do_state::m_3do_request_fiq0(UINT32 irq_req)
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0x00000002 Disk Inserted
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0x00000001 DMA Player bus
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*/
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void _3do_state::m_3do_request_fiq1(UINT32 irq_req)
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{
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m_clio.irq1 |= irq_req;
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if(m_clio.irq1 & m_clio.irq1_enable)
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m_maincpu->set_input_line(ARM7_FIRQ_LINE, ASSERT_LINE);
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if((m_clio.irq1 & m_clio.irq1_enable) == 0)
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m_maincpu->set_input_line(ARM7_FIRQ_LINE, CLEAR_LINE);
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}
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READ32_MEMBER(_3do_state::_3do_nvarea_r){
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@ -608,7 +606,8 @@ void _3do_madam_init( running_machine &machine )
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READ32_MEMBER(_3do_state::_3do_clio_r)
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{
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logerror( "%08X: CLIO read offset = %08X\n", machine().device("maincpu")->safe_pc(), offset * 4 );
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if (!space.debugger_access())
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logerror( "%08X: CLIO read offset = %08X\n", machine().device("maincpu")->safe_pc(), offset * 4 );
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switch( offset )
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{
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@ -759,6 +758,7 @@ READ32_MEMBER(_3do_state::_3do_clio_r)
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return m_clio.uncle_rom;
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default:
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if (!space.debugger_access())
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logerror( "%08X: unhandled CLIO read offset = %08X\n", machine().device("maincpu")->safe_pc(), offset * 4 );
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break;
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}
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@ -806,22 +806,22 @@ WRITE32_MEMBER(_3do_state::_3do_clio_w)
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case 0x0040/4:
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LOG(("%08x PEND0\n",data));
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m_clio.irq0 |= data;
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m_3do_request_fiq0(0);
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m_3do_request_fiq(0,0);
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break;
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case 0x0044/4:
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LOG(("%08x PEND0 CLEAR\n",data));
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m_clio.irq0 &= ~data;
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m_3do_request_fiq0(0);
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m_3do_request_fiq(0,0);
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break;
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case 0x0048/4:
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LOG(("%08x MASK0\n",data));
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m_clio.irq0_enable |= data;
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m_3do_request_fiq0(0);
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m_3do_request_fiq(0,0);
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break;
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case 0x004c/4:
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LOG(("%08x MASK0 CLEAR\n",data));
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m_clio.irq0_enable &= ~data;
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m_3do_request_fiq0(0);
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m_3do_request_fiq(0,0);
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break;
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case 0x0050/4:
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m_clio.mode |= data;
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@ -838,22 +838,22 @@ WRITE32_MEMBER(_3do_state::_3do_clio_w)
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case 0x0060/4:
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LOG(("%08x PEND1\n",data));
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m_clio.irq1 |= data;
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m_3do_request_fiq1(0);
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m_3do_request_fiq(0,1);
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break;
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case 0x0064/4:
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LOG(("%08x PEND1 CLEAR\n",data));
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m_clio.irq1 &= ~data;
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m_3do_request_fiq1(0);
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m_3do_request_fiq(0,1);
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break;
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case 0x0068/4:
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LOG(("%08x MASK1\n",data));
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m_clio.irq1_enable |= data;
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m_3do_request_fiq1(0);
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m_3do_request_fiq(0,1);
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break;
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case 0x006c/4:
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LOG(("%08x MASK1 CLEAR\n",data));
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m_clio.irq1_enable &= ~data;
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m_3do_request_fiq1(0);
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m_3do_request_fiq(0,1);
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break;
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case 0x0080/4:
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m_clio.hdelay = data;
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