mirror of
https://github.com/holub/mame
synced 2025-05-03 21:13:18 +03:00
cleanups (nw)
This commit is contained in:
Olivier Galibert
parent
1a4e058f66
commit
06ec83d2aa
@ -250,8 +250,6 @@ WRITE8_MEMBER( mm1_state::ls259_w )
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if (LOG) logerror("MOTOR %u\n", d);
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m_floppy0->mon_w(!d);
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m_floppy1->mon_w(!d);
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if (ioport("T5")->read()) m_fdc->ready_w(d);
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break;
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}
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}
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@ -745,9 +743,6 @@ void mm1_state::machine_reset()
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// reset LS259
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for (i = 0; i < 8; i++) ls259_w(program, i, 0);
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// set FDC ready
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if (!ioport("T5")->read()) m_fdc->ready_w(true);
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// reset FDC
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m_fdc->reset();
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}
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@ -1024,21 +1024,19 @@ TIMER_CALLBACK_MEMBER(pc88va_state::pc88va_fdc_motor_start_1)
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m_fdc_motor_status[1] = 1;
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}
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/* TODO: double check schematics */
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void pc88va_state::pc88va_fdc_update_ready(floppy_image_device *, int)
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{
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bool ready_0 = m_fdc_ctrl_2 & 0x20;
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bool ready_1 = m_fdc_ctrl_2 & 0x40;
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bool ready = m_fdc_ctrl_2 & 0x40;
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floppy_image_device *floppy;
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floppy = machine().device<floppy_connector>("upd765:0")->get_device();
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if(floppy && ready_0)
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ready_0 = floppy->ready_r();
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if(floppy && ready)
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ready = floppy->ready_r();
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floppy = machine().device<floppy_connector>("upd765:1")->get_device();
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if(floppy && ready_1)
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ready_1 = floppy->ready_r();
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if(floppy && ready)
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ready = floppy->ready_r();
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m_fdc->ready_w(ready_0 && ready_1);
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m_fdc->ready_w(ready);
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}
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WRITE8_MEMBER(pc88va_state::pc88va_fdc_w)
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@ -195,571 +195,3 @@ pc_fdc_at_device::pc_fdc_at_device(const machine_config &mconfig, const char *ta
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{
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m_shortname = "pc_fdc_at";
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}
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#if 0
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/* if not 1, DACK and TC inputs to FDC are disabled, and DRQ and IRQ are held
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* at high impedance i.e they are not affective */
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#define PC_FDC_FLAGS_DOR_DMA_ENABLED (1<<3)
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#define PC_FDC_FLAGS_DOR_FDC_ENABLED (1<<2)
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#define PC_FDC_FLAGS_DOR_MOTOR_ON (1<<4)
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#define LOG_FDC 0
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/* registers etc */
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struct pc_fdc
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{
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int status_register_a;
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int status_register_b;
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int digital_output_register;
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int tape_drive_register;
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int data_rate_register;
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int digital_input_register;
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int configuration_control_register;
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/* stored tc state - state present at pins */
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int tc_state;
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/* stored dma drq state */
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int dma_state;
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/* stored int state */
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int int_state;
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/* PCJR watchdog timer */
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emu_timer *watchdog;
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struct pc_fdc_interface fdc_interface;
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};
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static struct pc_fdc *fdc;
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/* Prototypes */
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static TIMER_CALLBACK( watchdog_timeout );
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static WRITE_LINE_DEVICE_HANDLER( pc_fdc_hw_interrupt );
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static WRITE_LINE_DEVICE_HANDLER( pc_fdc_hw_dma_drq );
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static UPD765_GET_IMAGE ( pc_fdc_get_image );
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static UPD765_GET_IMAGE ( pcjr_fdc_get_image );
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const upd765_interface pc_fdc_upd765_connected_interface =
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{
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DEVCB_LINE(pc_fdc_hw_interrupt),
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DEVCB_LINE(pc_fdc_hw_dma_drq),
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pc_fdc_get_image,
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UPD765_RDY_PIN_CONNECTED,
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{FLOPPY_0, FLOPPY_1, NULL, NULL}
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};
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const upd765_interface pc_fdc_upd765_connected_1_drive_interface =
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{
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DEVCB_LINE(pc_fdc_hw_interrupt),
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DEVCB_LINE(pc_fdc_hw_dma_drq),
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pc_fdc_get_image,
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UPD765_RDY_PIN_CONNECTED,
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{FLOPPY_0, NULL, NULL, NULL}
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};
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const upd765_interface pc_fdc_upd765_not_connected_interface =
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{
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DEVCB_LINE(pc_fdc_hw_interrupt),
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DEVCB_LINE(pc_fdc_hw_dma_drq),
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pc_fdc_get_image,
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UPD765_RDY_PIN_NOT_CONNECTED,
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{FLOPPY_0, FLOPPY_1, NULL, NULL}
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};
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const upd765_interface pcjr_fdc_upd765_interface =
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{
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DEVCB_LINE(pc_fdc_hw_interrupt),
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DEVCB_NULL,
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pcjr_fdc_get_image,
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UPD765_RDY_PIN_NOT_CONNECTED,
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{FLOPPY_0, NULL, NULL, NULL}
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};
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static device_t* pc_get_device(running_machine &machine)
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{
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return (*fdc->fdc_interface.get_device)(machine);
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}
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void pc_fdc_reset(running_machine &machine)
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{
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/* setup reset condition */
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fdc->data_rate_register = 2;
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fdc->digital_output_register = 0;
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/* bit 7 is disk change */
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fdc->digital_input_register = 0x07f;
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upd765_reset(pc_get_device(machine),0);
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/* set FDC at reset */
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upd765_reset_w(pc_get_device(machine), 1);
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}
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void pc_fdc_init(running_machine &machine, const struct pc_fdc_interface *iface)
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{
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/* initialize fdc structure */
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fdc = auto_alloc_clear(machine, struct pc_fdc);
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/* copy specified interface */
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if (iface)
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memcpy(&fdc->fdc_interface, iface, sizeof(fdc->fdc_interface));
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fdc->watchdog = machine.scheduler().timer_alloc(FUNC(watchdog_timeout));
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pc_fdc_reset(machine);
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}
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static UPD765_GET_IMAGE ( pc_fdc_get_image )
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{
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device_t *image = NULL;
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if (!fdc->fdc_interface.get_image)
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{
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image = floppy_get_device(device->machine(), (fdc->digital_output_register & 0x03));
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}
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else
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{
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image = fdc->fdc_interface.get_image(device->machine(), (fdc->digital_output_register & 0x03));
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}
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return image;
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}
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static UPD765_GET_IMAGE ( pcjr_fdc_get_image )
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{
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device_t *image = NULL;
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if (!fdc->fdc_interface.get_image)
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{
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image = floppy_get_device(device->machine(), 0);
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}
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else
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{
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image = fdc->fdc_interface.get_image(device->machine(), 0);
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}
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return image;
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}
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void pc_fdc_set_tc_state(running_machine &machine, int state)
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{
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/* store state */
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fdc->tc_state = state;
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/* if dma is not enabled, tc's are not acknowledged */
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if ((fdc->digital_output_register & PC_FDC_FLAGS_DOR_DMA_ENABLED)!=0)
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{
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upd765_tc_w(pc_get_device(machine), state);
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}
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}
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static WRITE_LINE_DEVICE_HANDLER( pc_fdc_hw_interrupt )
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{
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fdc->int_state = state;
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/* if dma is not enabled, irq's are masked */
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if ((fdc->digital_output_register & PC_FDC_FLAGS_DOR_DMA_ENABLED)==0)
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return;
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/* send irq */
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if (fdc->fdc_interface.pc_fdc_interrupt)
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fdc->fdc_interface.pc_fdc_interrupt(device->machine(), state);
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}
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int pc_fdc_dack_r(running_machine &machine, address_space &space)
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{
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int data;
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/* what is output if dack is not acknowledged? */
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data = 0x0ff;
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/* if dma is not enabled, dacks are not acknowledged */
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if ((fdc->digital_output_register & PC_FDC_FLAGS_DOR_DMA_ENABLED)!=0)
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{
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data = upd765_dack_r(pc_get_device(machine), space, 0);
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}
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return data;
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}
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void pc_fdc_dack_w(running_machine &machine, address_space &space, int data)
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{
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/* if dma is not enabled, dacks are not issued */
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if ((fdc->digital_output_register & PC_FDC_FLAGS_DOR_DMA_ENABLED)!=0)
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{
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/* dma acknowledge - and send byte to fdc */
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upd765_dack_w(pc_get_device(machine), space, 0,data);
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}
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}
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static WRITE_LINE_DEVICE_HANDLER( pc_fdc_hw_dma_drq )
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{
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fdc->dma_state = state;
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/* if dma is not enabled, drqs are masked */
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if ((fdc->digital_output_register & PC_FDC_FLAGS_DOR_DMA_ENABLED)==0)
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return;
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if (fdc->fdc_interface.pc_fdc_dma_drq)
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fdc->fdc_interface.pc_fdc_dma_drq(device->machine(), state);
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}
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static void pc_fdc_data_rate_w(running_machine &machine, UINT8 data)
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{
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if ((data & 0x080)!=0)
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{
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/* set ready state */
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upd765_ready_w(pc_get_device(machine),1);
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/* toggle reset state */
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upd765_reset_w(pc_get_device(machine), 1);
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upd765_reset_w(pc_get_device(machine), 0);
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/* bit is self-clearing */
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data &= ~0x080;
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}
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fdc->data_rate_register = data;
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}
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/* FDC Digitial Output Register (DOR)
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|7|6|5|4|3|2|1|0|
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| | | | | | `------ floppy drive select (0=A, 1=B, 2=floppy C, ...)
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| | | | | `-------- 1 = FDC enable, 0 = hold FDC at reset
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| | | | `---------- 1 = DMA & I/O interface enabled
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| | | `------------ 1 = turn floppy drive A motor on
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| | `-------------- 1 = turn floppy drive B motor on
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| `---------------- 1 = turn floppy drive C motor on
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`------------------ 1 = turn floppy drive D motor on
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*/
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static WRITE8_HANDLER( pc_fdc_dor_w )
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{
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int selected_drive;
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int floppy_count;
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floppy_count = floppy_get_count(space.machine());
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if (floppy_count > (fdc->digital_output_register & 0x03))
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floppy_drive_set_ready_state(floppy_get_device(space.machine(), fdc->digital_output_register & 0x03), 1, 0);
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fdc->digital_output_register = data;
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selected_drive = data & 0x03;
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/* set floppy drive motor state */
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if (floppy_count > 0)
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floppy_mon_w(floppy_get_device(space.machine(), 0), !BIT(data, 4));
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if (floppy_count > 1)
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floppy_mon_w(floppy_get_device(space.machine(), 1), !BIT(data, 5));
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if (floppy_count > 2)
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floppy_mon_w(floppy_get_device(space.machine(), 2), !BIT(data, 6));
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if (floppy_count > 3)
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floppy_mon_w(floppy_get_device(space.machine(), 3), !BIT(data, 7));
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if ((data>>4) & (1<<selected_drive))
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{
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if (floppy_count > selected_drive)
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floppy_drive_set_ready_state(floppy_get_device(space.machine(), selected_drive), 1, 0);
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}
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/* changing the DMA enable bit, will affect the terminal count state
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from reaching the fdc - if dma is enabled this will send it through
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otherwise it will be ignored */
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pc_fdc_set_tc_state(space.machine(), fdc->tc_state);
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/* changing the DMA enable bit, will affect the dma drq state
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from reaching us - if dma is enabled this will send it through
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otherwise it will be ignored */
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pc_fdc_hw_dma_drq(pc_get_device(space.machine()), fdc->dma_state);
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/* changing the DMA enable bit, will affect the irq state
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from reaching us - if dma is enabled this will send it through
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otherwise it will be ignored */
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pc_fdc_hw_interrupt(pc_get_device(space.machine()), fdc->int_state);
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/* reset? */
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if ((fdc->digital_output_register & PC_FDC_FLAGS_DOR_FDC_ENABLED)==0)
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{
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/* yes */
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/* pc-xt expects a interrupt to be generated
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when the fdc is reset.
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In the FDC docs, it states that a INT will
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be generated if READY input is true when the
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fdc is reset.
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It also states, that outputs to drive are set to 0.
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Maybe this causes the drive motor to go on, and therefore
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the ready line is set.
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This in return causes a int?? ---
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what is not yet clear is if this is a result of the drives ready state
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changing...
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*/
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upd765_ready_w(pc_get_device(space.machine()),1);
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/* set FDC at reset */
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upd765_reset_w(pc_get_device(space.machine()), 1);
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}
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else
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{
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pc_fdc_set_tc_state(space.machine(), 0);
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/* release reset on fdc */
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upd765_reset_w(pc_get_device(space.machine()), 0);
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}
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}
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/* PCJr FDC Digitial Output Register (DOR)
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On a PC Jr the DOR is wired up a bit differently:
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|7|6|5|4|3|2|1|0|
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| | | | | | | `--- Drive enable ( 0 = off, 1 = on )
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| | | | | | `----- Reserved
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| | | | | `------- Reserved
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| | | | `--------- Reserved
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| | | `----------- Reserved
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| | `------------- Watchdog Timer Enable ( 0 = watchdog disabled, 1 = watchdog enabled )
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| `--------------- Watchdog Timer Trigger ( on a 1->0 transition to strobe the trigger )
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`----------------- FDC Reset ( 0 = hold reset, 1 = release reset )
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*/
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static TIMER_CALLBACK( watchdog_timeout )
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{
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/* Trigger a watchdog timeout signal */
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if ( fdc->fdc_interface.pc_fdc_interrupt && ( fdc->digital_output_register & 0x20 ) )
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{
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fdc->fdc_interface.pc_fdc_interrupt(machine, 1 );
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}
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else
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{
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fdc->fdc_interface.pc_fdc_interrupt(machine, 0 );
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}
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}
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static WRITE8_HANDLER( pcjr_fdc_dor_w )
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{
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int floppy_count;
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floppy_count = floppy_get_count(space.machine());
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/* set floppy drive motor state */
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if (floppy_count > 0)
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floppy_mon_w(floppy_get_device(space.machine(), 0), BIT(data, 0) ? CLEAR_LINE : ASSERT_LINE);
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if ( data & 0x01 )
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{
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if ( floppy_count )
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floppy_drive_set_ready_state(floppy_get_device(space.machine(), 0), 1, 0);
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}
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/* Is the watchdog timer disabled */
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if ( ! ( data & 0x20 ) )
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{
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fdc->watchdog->adjust( attotime::never );
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if ( fdc->fdc_interface.pc_fdc_interrupt )
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{
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fdc->fdc_interface.pc_fdc_interrupt(space.machine(), 0 );
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}
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} else {
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/* Check for 1->0 watchdog trigger */
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if ( ( fdc->digital_output_register & 0x40 ) && ! ( data & 0x40 ) )
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{
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/* Start watchdog timer here */
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fdc->watchdog->adjust( attotime::from_seconds(3) );
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}
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}
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/* reset? */
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if ( ! (data & 0x80) )
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{
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/* yes */
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/* pc-xt expects a interrupt to be generated
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when the fdc is reset.
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In the FDC docs, it states that a INT will
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be generated if READY input is true when the
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fdc is reset.
|
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|
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It also states, that outputs to drive are set to 0.
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Maybe this causes the drive motor to go on, and therefore
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the ready line is set.
|
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|
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This in return causes a int?? ---
|
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|
||||
|
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what is not yet clear is if this is a result of the drives ready state
|
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changing...
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*/
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upd765_ready_w(pc_get_device(space.machine()),1);
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/* set FDC at reset */
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upd765_reset_w(pc_get_device(space.machine()), 1);
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}
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else
|
||||
{
|
||||
pc_fdc_set_tc_state(space.machine(), 0);
|
||||
|
||||
/* release reset on fdc */
|
||||
upd765_reset_w(pc_get_device(space.machine()), 0);
|
||||
}
|
||||
|
||||
logerror("pcjr_fdc_dor_w: changing dor from %02x to %02x\n", fdc->digital_output_register, data);
|
||||
|
||||
fdc->digital_output_register = data;
|
||||
}
|
||||
|
||||
#define RATE_250 2
|
||||
#define RATE_300 1
|
||||
#define RATE_500 0
|
||||
#define RATE_1000 3
|
||||
|
||||
static void pc_fdc_check_data_rate(running_machine &machine)
|
||||
{
|
||||
device_t *device = floppy_get_device(machine, fdc->digital_output_register & 0x03);
|
||||
floppy_image_legacy *image;
|
||||
int tracks, sectors, rate;
|
||||
|
||||
upd765_set_bad(pc_get_device(machine), 0); // unset in case format is unknown
|
||||
if (!device) return;
|
||||
image = flopimg_get_image(device);
|
||||
if (!image) return;
|
||||
tracks = floppy_get_tracks_per_disk(image);
|
||||
tracks -= (tracks % 10); // ignore extra tracks
|
||||
floppy_get_sector_count(image, 0, 0, §ors);
|
||||
|
||||
if (tracks == 40) {
|
||||
if ((fdc->data_rate_register != RATE_250) && (fdc->data_rate_register != RATE_300))
|
||||
upd765_set_bad(pc_get_device(machine), 1);
|
||||
return;
|
||||
} else if (tracks == 80) {
|
||||
if (sectors <= 14) rate = RATE_250; // 720KB 5 1/4 and 3 1/2
|
||||
else if (sectors <= 24) rate = RATE_500; // 1.2MB 5 1/4 and 1.44MB 3 1/2
|
||||
else rate = RATE_1000; // 2.88MB 3 1/2
|
||||
} else return;
|
||||
|
||||
if (rate != (fdc->data_rate_register & 3))
|
||||
upd765_set_bad(pc_get_device(machine), 1);
|
||||
}
|
||||
|
||||
READ8_HANDLER ( pc_fdc_r )
|
||||
{
|
||||
UINT8 data = 0xff;
|
||||
|
||||
switch(offset)
|
||||
{
|
||||
case 0: /* status register a */
|
||||
case 1: /* status register b */
|
||||
data = 0x00;
|
||||
break;
|
||||
case 2:
|
||||
data = fdc->digital_output_register;
|
||||
break;
|
||||
case 3: /* tape drive select? */
|
||||
break;
|
||||
case 4:
|
||||
data = upd765_status_r(pc_get_device(space.machine()), space, 0);
|
||||
break;
|
||||
case 5:
|
||||
data = upd765_data_r(pc_get_device(space.machine()), space, offset);
|
||||
break;
|
||||
case 6: /* FDC reserved */
|
||||
break;
|
||||
case 7:
|
||||
device_t *dev = floppy_get_device(space.machine(), fdc->digital_output_register & 0x03);
|
||||
data = fdc->digital_input_register;
|
||||
if(dev) data |= (!floppy_dskchg_r(dev)<<7);
|
||||
break;
|
||||
}
|
||||
|
||||
if (LOG_FDC)
|
||||
logerror("pc_fdc_r(): pc=0x%08x offset=%d result=0x%02X\n", (unsigned) space.machine().firstcpu->pc(), offset, data);
|
||||
return data;
|
||||
}
|
||||
|
||||
|
||||
|
||||
WRITE8_HANDLER ( pc_fdc_w )
|
||||
{
|
||||
if (LOG_FDC)
|
||||
logerror("pc_fdc_w(): pc=0x%08x offset=%d data=0x%02X\n", (unsigned) space.machine().firstcpu->pc(), offset, data);
|
||||
|
||||
pc_fdc_check_data_rate(space.machine()); // check every time a command may start
|
||||
switch(offset)
|
||||
{
|
||||
case 0: /* n/a */
|
||||
case 1: /* n/a */
|
||||
break;
|
||||
case 2:
|
||||
pc_fdc_dor_w(space, 0, data, mem_mask);
|
||||
break;
|
||||
case 3:
|
||||
/* tape drive select? */
|
||||
break;
|
||||
case 4:
|
||||
pc_fdc_data_rate_w(space.machine(), data);
|
||||
break;
|
||||
case 5:
|
||||
upd765_data_w(pc_get_device(space.machine()), space, 0, data);
|
||||
break;
|
||||
case 6:
|
||||
/* FDC reserved */
|
||||
break;
|
||||
case 7:
|
||||
/* Configuration Control Register
|
||||
*
|
||||
* Currently unimplemented; bits 1-0 are supposed to control data
|
||||
* flow rates:
|
||||
* 0 0 500 kbps
|
||||
* 0 1 300 kbps
|
||||
* 1 0 250 kbps
|
||||
* 1 1 1000 kbps
|
||||
*/
|
||||
pc_fdc_data_rate_w(space.machine(), data & 3);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
WRITE8_HANDLER ( pcjr_fdc_w )
|
||||
{
|
||||
if (LOG_FDC)
|
||||
logerror("pcjr_fdc_w(): pc=0x%08x offset=%d data=0x%02X\n", (unsigned) space.machine().firstcpu->pc(), offset, data);
|
||||
|
||||
switch(offset)
|
||||
{
|
||||
case 2:
|
||||
pcjr_fdc_dor_w( space, 0, data, mem_mask );
|
||||
break;
|
||||
case 4:
|
||||
case 7:
|
||||
break;
|
||||
default:
|
||||
pc_fdc_w( space, offset, data );
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user