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https://github.com/holub/mame
synced 2025-07-05 09:57:47 +03:00
swim2: Add mfm read, fix mfm write and mfm detection. SWIM2 seems done at that point.
This commit is contained in:
Olivier Galibert
parent
c3e15affc3
commit
07318ffb9d
@ -2422,7 +2422,7 @@ bool mac_floppy_device::wpt_r()
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// actual_ss may have changed after the phases were set
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m_reg = (m_reg & 7) | (actual_ss ? 8 : 0);
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if(m_reg != 4 && m_reg != 12)
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if(m_reg != 4 && m_reg != 12 && m_reg != 5 && m_reg != 13)
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logerror("fdc disk sense reg %x %s %p\n", m_reg, regnames[m_reg], image.get());
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switch(m_reg) {
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@ -2433,8 +2433,9 @@ bool mac_floppy_device::wpt_r()
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case 0x2: // Is the motor on?
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return mon;
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case 0x4: // Used when reading data, result ignored
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return false;
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case 0x4:
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case 0xc: // Index pulse, probably only on the superdrive though
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return !m_has_mfm ? false : !image || mon ? true : idx;
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case 0x5: // Is it a superdrive (supports 1.4M MFM) ?
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return m_has_mfm;
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@ -2454,9 +2455,6 @@ bool mac_floppy_device::wpt_r()
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case 0xa: // Not on track 0?
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return cyl != 0;
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case 0xc: // Another identification bit
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return m_rd1;
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case 0xd: // Is the current mode GCR or MFM?
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return m_mfm;
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@ -2588,9 +2586,7 @@ bool oa_d34v_device::is_2m() const
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mfd51w_device::mfd51w_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : mac_floppy_device(mconfig, MFD51W, tag, owner, clock)
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{
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m_has_mfm = true;
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}
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void mfd51w_device::setup_characteristics()
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{
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form_factor = floppy_image::FF_35;
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@ -2626,5 +2622,5 @@ void mfd75w_device::setup_characteristics()
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bool mfd75w_device::is_2m() const
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{
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return true;
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return false;
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}
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@ -287,7 +287,6 @@ protected:
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u8 m_reg;
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bool m_strb;
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bool m_mfm, m_has_mfm;
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bool m_rd1;
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mac_floppy_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
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@ -33,6 +33,11 @@ void swim2_device::device_start()
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save_item(NAME(m_current_bit));
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save_item(NAME(m_tss_sr));
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save_item(NAME(m_tss_output));
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save_item(NAME(m_sr));
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save_item(NAME(m_mfm_sync_counter));
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save_item(NAME(m_flux_write_start));
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save_item(NAME(m_flux_write));
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save_item(NAME(m_flux_write_count));
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}
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void swim2_device::device_reset()
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@ -52,11 +57,14 @@ void swim2_device::device_reset()
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m_current_bit = 0;
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m_tss_sr = 0;
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m_tss_output = 0;
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m_sr = 0;
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m_mfm_sync_counter = 0;
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m_devsel_cb(0);
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m_sel35_cb(true);
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m_hdsel_cb(false);
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m_flux_write_start = 0;
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m_flux_write_count = 0;
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std::fill(m_flux_write.begin(), m_flux_write.end(), 0);
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m_last_sync = machine().time().as_ticks(clock());
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}
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@ -93,13 +101,9 @@ void swim2_device::flush_write(u64 when)
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m_flux_write_count--;
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attotime start = cycles_to_time(m_flux_write_start);
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attotime end = cycles_to_time(when);
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logerror("wbuf start %s\n", start.to_string());
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std::vector<attotime> fluxes(m_flux_write_count);
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for(u32 i=0; i != m_flux_write_count; i++) {
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for(u32 i=0; i != m_flux_write_count; i++)
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fluxes[i] = cycles_to_time(m_flux_write[i]);
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logerror("wbuf flux %s\n", fluxes[i].to_string());
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}
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logerror("wbuf end %s\n", end.to_string());
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m_floppy->write_flux(start, end, m_flux_write_count, m_flux_write_count ? &fluxes[0] : nullptr);
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}
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m_flux_write_count = 0;
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@ -172,10 +176,10 @@ u8 swim2_device::read(offs_t offset)
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if(m_fifo_pos > 0) {
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if(m_fifo[m_fifo_pos - 1] & M_MARK)
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h |= 0x01;
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if(m_fifo[m_fifo_pos - 1] & M_CRC0)
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if(!(m_fifo[m_fifo_pos - 1] & M_CRC0))
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h |= 0x02;
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}
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// addata on 4
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// rddata on 4
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if(!m_floppy || m_floppy->wpt_r())
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h |= 0x08;
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if(m_error)
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@ -193,7 +197,6 @@ u8 swim2_device::read(offs_t offset)
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else if(m_fifo_pos == 1)
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h |= 0x80;
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}
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// logerror("handshake %02x\n", h);
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return h;
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}
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@ -304,6 +307,7 @@ void swim2_device::write(offs_t offset, u8 data)
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// Entering read mode
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m_current_bit = 0;
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m_sr = 0;
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m_mfm_sync_counter = 0;
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logerror("%s read start %s %s floppy=%p\n", machine().time().to_string(), m_setup & 0x04 ? "gcr" : "mfm", m_setup & 0x08 ? "fclk/2" : "fclk", m_floppy);
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m_pll.reset(machine().time());
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@ -326,6 +330,20 @@ u64 swim2_device::time_to_cycles(const attotime &tm) const
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return tm.as_ticks(clock());
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}
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void swim2_device::crc_clear()
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{
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m_crc = 0xcdb4;
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}
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void swim2_device::crc_update(int bit)
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{
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if((m_crc ^ (bit ? 0x8000 : 0x0000)) & 0x8000)
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m_crc = (m_crc << 1) ^ 0x1021;
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else
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m_crc = m_crc << 1;
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}
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attotime swim2_device::cycles_to_time(u64 cycles) const
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{
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return attotime::from_ticks(cycles, clock());
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@ -334,13 +352,11 @@ attotime swim2_device::cycles_to_time(u64 cycles) const
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void swim2_device::fifo_clear()
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{
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m_fifo_pos = 0;
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// must clear the crc to the appropriate r/w-dependant value. No idea yet which it is, but I have my suspicions.
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m_crc = 0x1234;
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crc_clear();
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}
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bool swim2_device::fifo_push(u16 data)
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{
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logerror("fifo push %03x\n", data);
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if(m_fifo_pos == 2)
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return true;
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m_fifo[m_fifo_pos ++] = data;
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@ -380,15 +396,12 @@ void swim2_device::sync()
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return;
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}
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logerror("ACTIVE %s %d-%d\n", m_mode & 0x10 ? "write" : "read", m_last_sync, next_sync);
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if(m_mode & 0x10) {
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// We count in half-cycles but only toggle write on full cycles
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u32 cycles = (next_sync - m_last_sync) << 1;
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// Write mode
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while(cycles) {
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// logerror("half cycles avail %d needed %d\n", cycles, m_half_cycles_before_change);
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if(m_half_cycles_before_change) {
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if(cycles >= m_half_cycles_before_change) {
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cycles -= m_half_cycles_before_change;
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@ -402,7 +415,6 @@ void swim2_device::sync()
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if(m_tss_output & 0xc) {
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logerror("SR %03x.%d TSS %c%c\n", m_sr, m_current_bit, m_tss_output & 8 ? m_tss_output & 2 ? '1' : '0' : '.', m_tss_output & 4 ? m_tss_output & 1 ? '1' : '0' : '.');
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bool bit;
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if(m_tss_output & 8) {
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bit = (m_tss_output >> 1) & 1;
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@ -420,40 +432,44 @@ void swim2_device::sync()
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m_half_cycles_before_change = m_setup & 0x40 ? 63 : 31;
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if(m_setup & 8)
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m_half_cycles_before_change <<= 1;
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logerror("T%d, %d half cycles\n", bit, m_half_cycles_before_change);
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continue;
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}
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if(m_current_bit == 0xff)
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fatalerror("Sequence break on write\n");
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if(m_current_bit == 0) {
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u16 r = fifo_pop();
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if(m_setup & 0x40)
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logerror("DATAW %02x\n", r);
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logerror("fifo pop %03x\n", r);
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if(r == 0xffff && !m_error) {
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m_error |= 0x01;
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flush_write();
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m_current_bit = 0xff;
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m_half_cycles_before_change = 0;
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m_mode &= ~8;
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logerror("write end on underrun\n");
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break;
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if(m_sr & M_CRC)
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m_sr = m_crc >> 8;
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else {
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u16 r = fifo_pop();
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if(r == 0xffff && !m_error) {
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m_error |= 0x01;
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flush_write();
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m_current_bit = 0xff;
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m_half_cycles_before_change = 0;
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m_mode &= ~8;
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logerror("write end on underrun\n");
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break;
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}
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if(r & M_CRC)
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m_sr = M_CRC | (m_crc >> 8);
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else
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m_sr = r & (M_MARK | M_CRC | 0xff);
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}
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if(r & M_CRC) {
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fatalerror("crc alpha\n");
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}
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m_sr = r & (M_MARK | M_CRC | 0xff);
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m_current_bit = 8;
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if(m_sr & M_MARK)
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crc_clear();
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}
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m_current_bit --;
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bool bit = (m_sr >> m_current_bit) & 1;
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if(!(m_sr & M_MARK))
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crc_update(bit);
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m_tss_sr = (m_tss_sr << 1) | bit;
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if(m_setup & 0x40)
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m_tss_output = 4 | bit;
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else {
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static const u8 tss[4] = { 5, 0xd, 4, 5 };
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if((m_sr & M_MARK) && (m_tss_sr == 8))
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if((m_sr & M_MARK) && ((m_tss_sr & 0xf) == 8))
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m_tss_output = 0xc;
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else
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m_tss_output = tss[m_tss_sr & 3];
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@ -471,16 +487,7 @@ void swim2_device::sync()
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if(bit == -1)
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break;
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m_sr = ((m_sr << 1) | bit) & 0xff;
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logerror("%s: bit %d, sr=%02x\n", when.to_string(), bit, m_sr);
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if(m_sr & 0x80) {
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static u8 m1, m2, m3;
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m1 = m2;
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m2 = m3;
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m3 = m_sr;
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logerror("DATAR %02x\n", m_sr);
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if(m1 == 0xd5 && m2 == 0xaa && m3 == 0xad)
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machine().debug_break();
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logerror("read byte %02x\n", m_sr);
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if(fifo_push(m_sr) && !m_error)
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m_error |= 0x01;
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m_sr = 0;
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@ -488,8 +495,56 @@ void swim2_device::sync()
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}
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} else {
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// MFM mode
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}
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for(;;) {
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static u16 xinf = 0xffff;
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attotime when;
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int bit = m_pll.get_next_bit(when, m_floppy, limit);
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if(bit == -1)
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break;
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xinf = (xinf << 1) | bit;
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if(m_mfm_sync_counter < 64) {
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if(bit != (m_mfm_sync_counter & 1))
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m_mfm_sync_counter ++;
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else
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m_mfm_sync_counter = 0;
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} else {
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if(m_mfm_sync_counter == 64 && bit)
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m_mfm_sync_counter --;
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else {
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if(m_mfm_sync_counter == 65 || m_mfm_sync_counter == 81) {
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m_tss_sr = 0xff;
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m_sr = 0;
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}
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if(m_mfm_sync_counter & 1) {
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m_sr |= bit << (((96 - m_mfm_sync_counter) >> 1) & 7);
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crc_update(bit);
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}
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m_tss_sr = (m_tss_sr << 1) | bit;
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if((m_tss_sr & 0xf) == 1 && !(m_mfm_sync_counter & 1))
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m_sr |= M_MARK;
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m_mfm_sync_counter ++;
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if(m_mfm_sync_counter == 80) {
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if(!(m_sr & M_MARK))
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m_mfm_sync_counter = 0;
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else {
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crc_clear();
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if(fifo_push(m_sr) && !m_error)
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m_error |= 0x01;
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}
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} else if(m_mfm_sync_counter == 96) {
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m_mfm_sync_counter -= 16;
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if(m_sr & M_MARK)
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crc_clear();
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else if(!m_crc)
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m_sr |= M_CRC0;
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if(fifo_push(m_sr) && !m_error)
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m_error |= 0x01;
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}
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}
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}
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}
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}
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}
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m_last_sync = next_sync;
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@ -49,7 +49,7 @@ private:
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u8 m_param[4];
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u8 m_mode, m_setup, m_error, m_param_idx, m_fifo_pos, m_tss_sr, m_tss_output, m_current_bit;
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u16 m_fifo[2], m_sr;
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u16 m_crc;
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u16 m_crc, m_mfm_sync_counter;
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u32 m_half_cycles_before_change;
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u64 m_last_sync;
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@ -67,6 +67,9 @@ private:
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u16 fifo_pop();
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void flush_write(u64 when = 0);
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void show_mode() const;
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void crc_update(int bit);
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void crc_clear();
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};
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DECLARE_DEVICE_TYPE(SWIM2, swim2_device)
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