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cpu/drcbearm64.cpp: Emit optimised memory access code. (#13464)
Emit optimised code for native-width reads and writes no larger than native width.
This commit is contained in:
Vas Crabb
GitHub
parent
ed02d60d9a
commit
0793350fd4
@ -540,6 +540,9 @@ private:
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void emit_float_ldr_mem(asmjit::a64::Assembler &a, const asmjit::a64::Vec ®, const void *ptr) const;
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void emit_float_str_mem(asmjit::a64::Assembler &a, const asmjit::a64::Vec ®, const void *ptr) const;
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void emit_memaccess_setup(asmjit::a64::Assembler &a, const be_parameter &addrp, const memory_accessors &accessors, const address_space::specific_access_info::side &side) const;
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void emit_narrow_memwrite(asmjit::a64::Assembler &a, const be_parameter &addrp, const parameter &spacesizep, const memory_accessors &accessors) const;
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void get_carry(asmjit::a64::Assembler &a, const asmjit::a64::Gp ®, bool inverted = false) const;
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void load_carry(asmjit::a64::Assembler &a, bool inverted = false) const;
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void store_carry(asmjit::a64::Assembler &a, bool inverted = false) const;
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@ -906,6 +909,139 @@ void drcbe_arm64::emit_strh_mem(a64::Assembler &a, const a64::Gp ®, const voi
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void drcbe_arm64::emit_float_ldr_mem(a64::Assembler &a, const a64::Vec ®, const void *ptr) const { emit_ldr_str_base_mem(a, a64::Inst::kIdLdr_v, reg, reg.isVecS() ? 2 : 3, ptr); }
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void drcbe_arm64::emit_float_str_mem(a64::Assembler &a, const a64::Vec ®, const void *ptr) const { emit_ldr_str_base_mem(a, a64::Inst::kIdStr_v, reg, reg.isVecS() ? 2 : 3, ptr); }
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void drcbe_arm64::emit_memaccess_setup(asmjit::a64::Assembler &a, const be_parameter &addrp, const memory_accessors &accessors, const address_space::specific_access_info::side &side) const
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{
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auto const addrreg = (accessors.no_mask || accessors.mask_simple) ? REG_PARAM2 : a64::x6;
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mov_reg_param(a, 4, addrreg, addrp);
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get_imm_relative(a, a64::x8, uintptr_t(side.dispatch));
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// if the high bits aren't affected by the global mask, extract them early
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if (accessors.high_bits && !accessors.mask_high_bits)
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a.ubfx(a64::w7, addrreg.w(), accessors.specific.low_bits, accessors.high_bits);
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if (accessors.mask_simple)
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a.and_(REG_PARAM2.w(), addrreg.w(), accessors.address_mask);
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else if (!accessors.no_mask)
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a.mov(REG_PARAM2.w(), accessors.address_mask); // 32-bit value, no more than two instructions
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// if the high address bits aren't affected by the global mask, load the dispatch table entry now
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if (!accessors.high_bits)
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a.ldr(REG_PARAM1, a64::Mem(a64::x8));
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else if (!accessors.mask_high_bits)
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a.ldr(REG_PARAM1, a64::Mem(a64::x8, a64::x7, arm::Shift(arm::ShiftOp::kLSL, 3)));
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// apply non-trivial global mask if necessary
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if (!accessors.no_mask && !accessors.mask_simple)
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a.and_(REG_PARAM2.w(), REG_PARAM2.w(), addrreg.w());
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// if the high address bits are affected by the global mask, load the dispatch table entry now
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if (accessors.mask_high_bits)
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{
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a.lsr(a64::w7, REG_PARAM2.w(), accessors.specific.low_bits);
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a.ldr(REG_PARAM1, a64::Mem(a64::x8, a64::x7, arm::Shift(arm::ShiftOp::kLSL, 3)));
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}
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// apply this pointer displacement if necessary
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if (side.displacement)
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a.add(REG_PARAM1, REG_PARAM1, side.displacement); // assume less than 4K
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// adjusted dispatch table entry pointer in REG_PARAM1
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// masked address in REG_PARAM2
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// x8, x7 and potentially x6 clobbered
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}
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void drcbe_arm64::emit_narrow_memwrite(asmjit::a64::Assembler &a, const be_parameter &addrp, const parameter &spacesizep, const memory_accessors &accessors) const
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{
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// expects data in REG_PARAM3 and mask in REG_PARAM4
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address_space &space = *m_space[spacesizep.space()];
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auto const addrreg = (accessors.no_mask || accessors.mask_simple) ? REG_PARAM2 : a64::x5;
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mov_reg_param(a, 4, addrreg, addrp);
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get_imm_relative(a, a64::x8, uintptr_t(accessors.specific.write.dispatch));
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// get the shift count for the data and offset in w7
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int const shift = space.addr_shift() - 3;
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uint32_t const shiftmask = (accessors.specific.native_bytes - (1 << spacesizep.size())) << 3;
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if (space.endianness() != ENDIANNESS_LITTLE)
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{
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// swizzle for big Endian spaces
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bool const smallshift = (shift <= 0) && (shift >= -3);
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if (!smallshift)
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{
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if (shift < 0)
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a.lsl(a64::w6, addrreg.w(), -shift);
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else
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a.lsr(a64::w6, addrreg.w(), shift);
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}
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a.mov(a64::w7, shiftmask);
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if (smallshift)
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a.bic(a64::w7, a64::w7, addrreg.w(), -shift);
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else
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a.bic(a64::w7, a64::w7, a64::w6);
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}
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else
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{
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if (!shift)
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{
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a.and_(a64::w7, addrreg.w(), shiftmask);
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}
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else
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{
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if (shift < 0)
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a.lsl(a64::w7, addrreg.w(), -shift);
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else
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a.lsr(a64::w7, addrreg.w(), shift);
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a.and_(a64::w7, a64::w7, shiftmask);
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}
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}
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// if the high bits aren't affected by the global mask, extract them early
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if (accessors.high_bits && !accessors.mask_high_bits)
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a.ubfx(a64::w6, addrreg.w(), accessors.specific.low_bits, accessors.high_bits);
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if (accessors.mask_simple)
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a.and_(REG_PARAM2.w(), addrreg.w(), accessors.address_mask);
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else if (!accessors.no_mask)
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a.mov(REG_PARAM2.w(), accessors.address_mask); // 32-bit value, no more than two instructions
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// if the high address bits aren't affected by the global mask, load the dispatch table entry now
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if (!accessors.high_bits)
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a.ldr(REG_PARAM1, a64::Mem(a64::x8));
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else if (!accessors.mask_high_bits)
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a.ldr(REG_PARAM1, a64::Mem(a64::x8, a64::x6, arm::Shift(arm::ShiftOp::kLSL, 3)));
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// apply non-trivial global mask if necessary
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if (!accessors.no_mask && !accessors.mask_simple)
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a.and_(REG_PARAM2.w(), REG_PARAM2.w(), addrreg.w());
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// if the high address bits are affected by the global mask, load the dispatch table entry now
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if (accessors.mask_high_bits)
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{
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a.lsr(a64::w6, REG_PARAM2.w(), accessors.specific.low_bits);
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a.ldr(REG_PARAM1, a64::Mem(a64::x8, a64::x6, arm::Shift(arm::ShiftOp::kLSL, 3)));
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}
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// apply this pointer displacement if necessary
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if (accessors.specific.write.displacement)
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a.add(REG_PARAM1, REG_PARAM1, accessors.specific.write.displacement); // assume less than 4K
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// shift the data and mask
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a.lsl(REG_PARAM3, REG_PARAM3, a64::x7);
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a.lsl(REG_PARAM4, REG_PARAM4, a64::x7);
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// call the write function
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if (accessors.specific.write.is_virtual)
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{
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a.ldr(a64::x8, a64::Mem(REG_PARAM1));
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a.ldr(a64::x8, a64::Mem(a64::x8, accessors.specific.write.function)); // assume no more than 4096 vtable entries
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a.blr(a64::x8);
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}
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else
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{
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call_arm_addr(a, (const void *)accessors.specific.write.function);
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}
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}
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void drcbe_arm64::mov_reg_param(a64::Assembler &a, uint32_t regsize, const a64::Gp &dst, const be_parameter &src) const
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{
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if (src.is_immediate())
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@ -2332,28 +2468,46 @@ void drcbe_arm64::op_read(a64::Assembler &a, const uml::instruction &inst)
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assert(spacesizep.is_size_space());
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auto const &accessors = m_memory_accessors[spacesizep.space()];
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bool const have_specific = (uintptr_t(nullptr) != accessors.specific.read.function) || accessors.specific.read.is_virtual;
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mov_reg_param(a, 4, REG_PARAM2, addrp);
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if (have_specific && ((1 << spacesizep.size()) == accessors.specific.native_bytes))
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{
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emit_memaccess_setup(a, addrp, accessors, accessors.specific.read);
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if (accessors.specific.read.is_virtual)
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{
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a.ldr(a64::x8, a64::Mem(REG_PARAM1));
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a.ldr(a64::x8, a64::Mem(a64::x8, accessors.specific.read.function)); // assume no more than 4096 vtable entries
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}
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a.mov(REG_PARAM3, make_bitmask<uint64_t>(accessors.specific.native_bytes << 3));
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if (accessors.specific.read.is_virtual)
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a.blr(a64::x8);
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else
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call_arm_addr(a, (const void *)accessors.specific.read.function);
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}
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else
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{
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mov_reg_param(a, 4, REG_PARAM2, addrp);
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if (spacesizep.size() == SIZE_BYTE)
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{
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get_imm_relative(a, REG_PARAM1, accessors.resolved.read_byte.obj);
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call_arm_addr(a, accessors.resolved.read_byte.func);
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}
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else if (spacesizep.size() == SIZE_WORD)
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{
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get_imm_relative(a, REG_PARAM1, accessors.resolved.read_word.obj);
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call_arm_addr(a, accessors.resolved.read_word.func);
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}
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else if (spacesizep.size() == SIZE_DWORD)
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{
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get_imm_relative(a, REG_PARAM1, accessors.resolved.read_dword.obj);
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call_arm_addr(a, accessors.resolved.read_dword.func);
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}
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else if (spacesizep.size() == SIZE_QWORD)
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{
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get_imm_relative(a, REG_PARAM1, accessors.resolved.read_qword.obj);
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call_arm_addr(a, accessors.resolved.read_qword.func);
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if (spacesizep.size() == SIZE_BYTE)
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{
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get_imm_relative(a, REG_PARAM1, accessors.resolved.read_byte.obj);
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call_arm_addr(a, accessors.resolved.read_byte.func);
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}
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else if (spacesizep.size() == SIZE_WORD)
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{
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get_imm_relative(a, REG_PARAM1, accessors.resolved.read_word.obj);
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call_arm_addr(a, accessors.resolved.read_word.func);
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}
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else if (spacesizep.size() == SIZE_DWORD)
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{
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get_imm_relative(a, REG_PARAM1, accessors.resolved.read_dword.obj);
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call_arm_addr(a, accessors.resolved.read_dword.func);
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}
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else if (spacesizep.size() == SIZE_QWORD)
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{
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get_imm_relative(a, REG_PARAM1, accessors.resolved.read_qword.obj);
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call_arm_addr(a, accessors.resolved.read_qword.func);
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}
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}
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mov_param_reg(a, inst.size(), dstp, REG_PARAM1);
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@ -2372,29 +2526,48 @@ void drcbe_arm64::op_readm(a64::Assembler &a, const uml::instruction &inst)
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assert(spacesizep.is_size_space());
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auto const &accessors = m_memory_accessors[spacesizep.space()];
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bool const have_specific = (uintptr_t(nullptr) != accessors.specific.read.function) || accessors.specific.read.is_virtual;
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mov_reg_param(a, 4, REG_PARAM2, addrp);
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mov_reg_param(a, inst.size(), REG_PARAM3, maskp);
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if (have_specific && ((1 << spacesizep.size()) == accessors.specific.native_bytes))
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{
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emit_memaccess_setup(a, addrp, accessors, accessors.specific.read);
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mov_reg_param(a, inst.size(), REG_PARAM3, maskp);
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if (accessors.specific.read.is_virtual)
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{
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a.ldr(a64::x8, a64::Mem(REG_PARAM1));
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a.ldr(a64::x8, a64::Mem(a64::x8, accessors.specific.read.function)); // assume no more than 4096 vtable entries
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a.blr(a64::x8);
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}
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else
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{
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call_arm_addr(a, (const void *)accessors.specific.read.function);
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}
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}
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else
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{
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mov_reg_param(a, 4, REG_PARAM2, addrp);
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mov_reg_param(a, inst.size(), REG_PARAM3, maskp);
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if (spacesizep.size() == SIZE_BYTE)
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{
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get_imm_relative(a, REG_PARAM1, accessors.resolved.read_byte_masked.obj);
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call_arm_addr(a, accessors.resolved.read_byte_masked.func);
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}
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else if (spacesizep.size() == SIZE_WORD)
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{
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get_imm_relative(a, REG_PARAM1, accessors.resolved.read_word_masked.obj);
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call_arm_addr(a, accessors.resolved.read_word_masked.func);
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}
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else if (spacesizep.size() == SIZE_DWORD)
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{
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get_imm_relative(a, REG_PARAM1, accessors.resolved.read_dword_masked.obj);
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call_arm_addr(a, accessors.resolved.read_dword_masked.func);
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}
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else if (spacesizep.size() == SIZE_QWORD)
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{
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get_imm_relative(a, REG_PARAM1, accessors.resolved.read_qword_masked.obj);
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call_arm_addr(a, accessors.resolved.read_qword_masked.func);
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if (spacesizep.size() == SIZE_BYTE)
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{
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get_imm_relative(a, REG_PARAM1, accessors.resolved.read_byte_masked.obj);
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call_arm_addr(a, accessors.resolved.read_byte_masked.func);
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}
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else if (spacesizep.size() == SIZE_WORD)
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{
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get_imm_relative(a, REG_PARAM1, accessors.resolved.read_word_masked.obj);
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call_arm_addr(a, accessors.resolved.read_word_masked.func);
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}
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else if (spacesizep.size() == SIZE_DWORD)
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{
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get_imm_relative(a, REG_PARAM1, accessors.resolved.read_dword_masked.obj);
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call_arm_addr(a, accessors.resolved.read_dword_masked.func);
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}
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else if (spacesizep.size() == SIZE_QWORD)
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{
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get_imm_relative(a, REG_PARAM1, accessors.resolved.read_qword_masked.obj);
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call_arm_addr(a, accessors.resolved.read_qword_masked.func);
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}
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}
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mov_param_reg(a, inst.size(), dstp, REG_PARAM1);
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@ -2412,29 +2585,54 @@ void drcbe_arm64::op_write(a64::Assembler &a, const uml::instruction &inst)
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assert(spacesizep.is_size_space());
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auto const &accessors = m_memory_accessors[spacesizep.space()];
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bool const have_specific = (uintptr_t(nullptr) != accessors.specific.write.function) || accessors.specific.write.is_virtual;
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mov_reg_param(a, 4, REG_PARAM2, addrp);
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mov_reg_param(a, inst.size(), REG_PARAM3, srcp);
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if (have_specific && ((1 << spacesizep.size()) == accessors.specific.native_bytes))
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{
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emit_memaccess_setup(a, addrp, accessors, accessors.specific.write);
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mov_reg_param(a, inst.size(), REG_PARAM3, srcp);
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if (accessors.specific.write.is_virtual)
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{
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a.ldr(a64::x8, a64::Mem(REG_PARAM1));
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a.ldr(a64::x8, a64::Mem(a64::x8, accessors.specific.write.function)); // assume no more than 4096 vtable entries
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}
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a.mov(REG_PARAM4, make_bitmask<uint64_t>(accessors.specific.native_bytes << 3));
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if (accessors.specific.write.is_virtual)
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a.blr(a64::x8);
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else
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call_arm_addr(a, (const void *)accessors.specific.write.function);
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}
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else if (have_specific && ((1 << spacesizep.size()) < accessors.specific.native_bytes))
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{
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mov_reg_param(a, inst.size(), REG_PARAM3, srcp);
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a.mov(REG_PARAM4, make_bitmask<uint64_t>(8 << spacesizep.size()));
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emit_narrow_memwrite(a, addrp, spacesizep, accessors);
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}
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else
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{
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mov_reg_param(a, 4, REG_PARAM2, addrp);
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mov_reg_param(a, inst.size(), REG_PARAM3, srcp);
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if (spacesizep.size() == SIZE_BYTE)
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{
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get_imm_relative(a, REG_PARAM1, accessors.resolved.write_byte.obj);
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call_arm_addr(a, accessors.resolved.write_byte.func);
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}
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else if (spacesizep.size() == SIZE_WORD)
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{
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get_imm_relative(a, REG_PARAM1, accessors.resolved.write_word.obj);
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call_arm_addr(a, accessors.resolved.write_word.func);
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}
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else if (spacesizep.size() == SIZE_DWORD)
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{
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get_imm_relative(a, REG_PARAM1, accessors.resolved.write_dword.obj);
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call_arm_addr(a, accessors.resolved.write_dword.func);
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}
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else if (spacesizep.size() == SIZE_QWORD)
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{
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get_imm_relative(a, REG_PARAM1, accessors.resolved.write_qword.obj);
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call_arm_addr(a, accessors.resolved.write_qword.func);
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if (spacesizep.size() == SIZE_BYTE)
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{
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get_imm_relative(a, REG_PARAM1, accessors.resolved.write_byte.obj);
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call_arm_addr(a, accessors.resolved.write_byte.func);
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}
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else if (spacesizep.size() == SIZE_WORD)
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{
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get_imm_relative(a, REG_PARAM1, accessors.resolved.write_word.obj);
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call_arm_addr(a, accessors.resolved.write_word.func);
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}
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else if (spacesizep.size() == SIZE_DWORD)
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{
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get_imm_relative(a, REG_PARAM1, accessors.resolved.write_dword.obj);
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call_arm_addr(a, accessors.resolved.write_dword.func);
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}
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else if (spacesizep.size() == SIZE_QWORD)
|
||||
{
|
||||
get_imm_relative(a, REG_PARAM1, accessors.resolved.write_qword.obj);
|
||||
call_arm_addr(a, accessors.resolved.write_qword.func);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -2452,30 +2650,55 @@ void drcbe_arm64::op_writem(a64::Assembler &a, const uml::instruction &inst)
|
||||
|
||||
// set up a call to the write handler
|
||||
auto const &accessors = m_memory_accessors[spacesizep.space()];
|
||||
bool const have_specific = (uintptr_t(nullptr) != accessors.specific.write.function) || accessors.specific.write.is_virtual;
|
||||
|
||||
mov_reg_param(a, 4, REG_PARAM2, addrp);
|
||||
mov_reg_param(a, inst.size(), REG_PARAM3, srcp);
|
||||
mov_reg_param(a, inst.size(), REG_PARAM4, maskp);
|
||||
if (have_specific && ((1 << spacesizep.size()) == accessors.specific.native_bytes))
|
||||
{
|
||||
emit_memaccess_setup(a, addrp, accessors, accessors.specific.write);
|
||||
mov_reg_param(a, inst.size(), REG_PARAM3, srcp);
|
||||
if (accessors.specific.write.is_virtual)
|
||||
{
|
||||
a.ldr(a64::x8, a64::Mem(REG_PARAM1));
|
||||
a.ldr(a64::x8, a64::Mem(a64::x8, accessors.specific.write.function)); // assume no more than 4096 vtable entries
|
||||
}
|
||||
mov_reg_param(a, inst.size(), REG_PARAM4, maskp);
|
||||
if (accessors.specific.write.is_virtual)
|
||||
a.blr(a64::x8);
|
||||
else
|
||||
call_arm_addr(a, (const void *)accessors.specific.write.function);
|
||||
}
|
||||
else if (have_specific && ((1 << spacesizep.size()) < accessors.specific.native_bytes))
|
||||
{
|
||||
mov_reg_param(a, inst.size(), REG_PARAM3, srcp);
|
||||
mov_reg_param(a, inst.size(), REG_PARAM4, maskp);
|
||||
emit_narrow_memwrite(a, addrp, spacesizep, accessors);
|
||||
}
|
||||
else
|
||||
{
|
||||
mov_reg_param(a, 4, REG_PARAM2, addrp);
|
||||
mov_reg_param(a, inst.size(), REG_PARAM3, srcp);
|
||||
mov_reg_param(a, inst.size(), REG_PARAM4, maskp);
|
||||
|
||||
if (spacesizep.size() == SIZE_BYTE)
|
||||
{
|
||||
get_imm_relative(a, REG_PARAM1, accessors.resolved.write_byte_masked.obj);
|
||||
call_arm_addr(a, accessors.resolved.write_byte_masked.func);
|
||||
}
|
||||
else if (spacesizep.size() == SIZE_WORD)
|
||||
{
|
||||
get_imm_relative(a, REG_PARAM1, accessors.resolved.write_word_masked.obj);
|
||||
call_arm_addr(a, accessors.resolved.write_word_masked.func);
|
||||
}
|
||||
else if (spacesizep.size() == SIZE_DWORD)
|
||||
{
|
||||
get_imm_relative(a, REG_PARAM1, accessors.resolved.write_dword_masked.obj);
|
||||
call_arm_addr(a, accessors.resolved.write_dword_masked.func);
|
||||
}
|
||||
else if (spacesizep.size() == SIZE_QWORD)
|
||||
{
|
||||
get_imm_relative(a, REG_PARAM1, accessors.resolved.write_qword_masked.obj);
|
||||
call_arm_addr(a, accessors.resolved.write_qword_masked.func);
|
||||
if (spacesizep.size() == SIZE_BYTE)
|
||||
{
|
||||
get_imm_relative(a, REG_PARAM1, accessors.resolved.write_byte_masked.obj);
|
||||
call_arm_addr(a, accessors.resolved.write_byte_masked.func);
|
||||
}
|
||||
else if (spacesizep.size() == SIZE_WORD)
|
||||
{
|
||||
get_imm_relative(a, REG_PARAM1, accessors.resolved.write_word_masked.obj);
|
||||
call_arm_addr(a, accessors.resolved.write_word_masked.func);
|
||||
}
|
||||
else if (spacesizep.size() == SIZE_DWORD)
|
||||
{
|
||||
get_imm_relative(a, REG_PARAM1, accessors.resolved.write_dword_masked.obj);
|
||||
call_arm_addr(a, accessors.resolved.write_dword_masked.func);
|
||||
}
|
||||
else if (spacesizep.size() == SIZE_QWORD)
|
||||
{
|
||||
get_imm_relative(a, REG_PARAM1, accessors.resolved.write_qword_masked.obj);
|
||||
call_arm_addr(a, accessors.resolved.write_qword_masked.func);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user