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Removed legacy Z80 CTC interfaces.

Browse Source 
Removed Star Force sound hack in favor of just driving a DAC
directly with the CTC output line (MAME can handle sound
frequency timers no problem).
This commit is contained in:
Aaron Giles 2012-08-08 08:36:31 +00:00
parent f3b6f56ed6
commit 081fb69aec
21 changed files with 108 additions and 140 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/emu/machine/ldv1000.c
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@ -100,7 +100,7 @@ static ADDRESS_MAP_START( ldv1000_portmap, AS_IO, 8, pioneer_ldv1000_device )
AM_RANGE(0x00, 0x07) AM_MIRROR(0x38) AM_READWRITE(z80_decoder_display_port_r, z80_decoder_display_port_w)
AM_RANGE(0x40, 0x40) AM_MIRROR(0x3f) AM_READ(z80_controller_r)
AM_RANGE(0x80, 0x80) AM_MIRROR(0x3f) AM_WRITE(z80_controller_w)
AM_RANGE(0xc0, 0xc3) AM_MIRROR(0x3c) AM_DEVREADWRITE_LEGACY("ldvctc", z80ctc_r, z80ctc_w)
AM_RANGE(0xc0, 0xc3) AM_MIRROR(0x3c) AM_DEVREADWRITE("ldvctc", z80ctc_device, read, write)
ADDRESS_MAP_END

45
src/emu/machine/z80ctc.c
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@ -86,6 +86,37 @@ z80ctc_device::z80ctc_device(const machine_config &mconfig, const char *tag, dev
}
//-------------------------------------------------
// read - standard handler for reading
//-------------------------------------------------
READ8_MEMBER( z80ctc_device::read )
{
return read(offset & 3);
}
//-------------------------------------------------
// write - standard handler for writing
//-------------------------------------------------
WRITE8_MEMBER( z80ctc_device::write )
{
write(offset & 3, data);
}
//-------------------------------------------------
// trg0-3 - standard write line handlers for each
// trigger
//-------------------------------------------------
WRITE_LINE_MEMBER( z80ctc_device::trg0 ) { trigger(0, state); }
WRITE_LINE_MEMBER( z80ctc_device::trg1 ) { trigger(1, state); }
WRITE_LINE_MEMBER( z80ctc_device::trg2 ) { trigger(2, state); }
WRITE_LINE_MEMBER( z80ctc_device::trg3 ) { trigger(3, state); }
//-------------------------------------------------
// device_config_complete - perform any
// operations now that the configuration is
@ -510,17 +541,3 @@ void z80ctc_device::ctc_channel::timer_callback()
// reset the down counter
m_down = m_tconst;
}
//**************************************************************************
// GLOBAL STUBS
//**************************************************************************
WRITE8_DEVICE_HANDLER( z80ctc_w ) { downcast<z80ctc_device *>(device)->write(offset & 3, data); }
READ8_DEVICE_HANDLER( z80ctc_r ) { return downcast<z80ctc_device *>(device)->read(offset & 3); }
WRITE_LINE_DEVICE_HANDLER( z80ctc_trg0_w ) { downcast<z80ctc_device *>(device)->trigger(0, state); }
WRITE_LINE_DEVICE_HANDLER( z80ctc_trg1_w ) { downcast<z80ctc_device *>(device)->trigger(1, state); }
WRITE_LINE_DEVICE_HANDLER( z80ctc_trg2_w ) { downcast<z80ctc_device *>(device)->trigger(2, state); }
WRITE_LINE_DEVICE_HANDLER( z80ctc_trg3_w ) { downcast<z80ctc_device *>(device)->trigger(3, state); }

22
src/emu/machine/z80ctc.h
View File

@ -90,6 +90,14 @@ public:
UINT8 read(int ch) { return m_channel[ch].read(); }
void write(int ch, UINT8 data) { m_channel[ch].write(data); }
void trigger(int ch, UINT8 data) { m_channel[ch].trigger(data); }
// read/write handlers
DECLARE_READ8_MEMBER( read );
DECLARE_WRITE8_MEMBER( write );
DECLARE_WRITE_LINE_MEMBER( trg0 );
DECLARE_WRITE_LINE_MEMBER( trg1 );
DECLARE_WRITE_LINE_MEMBER( trg2 );
DECLARE_WRITE_LINE_MEMBER( trg3 );
private:
// device-level overrides
@ -151,18 +159,4 @@ private:
extern const device_type Z80CTC;
//**************************************************************************
// READ/WRITE HANDLERS
//**************************************************************************
WRITE8_DEVICE_HANDLER( z80ctc_w );
READ8_DEVICE_HANDLER( z80ctc_r );
WRITE_LINE_DEVICE_HANDLER( z80ctc_trg0_w );
WRITE_LINE_DEVICE_HANDLER( z80ctc_trg1_w );
WRITE_LINE_DEVICE_HANDLER( z80ctc_trg2_w );
WRITE_LINE_DEVICE_HANDLER( z80ctc_trg3_w );
#endif

10
src/mame/audio/cchasm.c
View File

@ -17,7 +17,7 @@ WRITE8_MEMBER(cchasm_state::cchasm_reset_coin_flag_w)
if (m_coin_flag)
{
m_coin_flag = 0;
z80ctc_trg0_w(m_ctc, m_coin_flag);
m_ctc->trg0(m_coin_flag);
}
}
@ -26,7 +26,7 @@ INPUT_CHANGED_MEMBER(cchasm_state::cchasm_set_coin_flag )
if (!newval && !m_coin_flag)
{
m_coin_flag = 1;
z80ctc_trg0_w(m_ctc, m_coin_flag);
m_ctc->trg0(m_coin_flag);
}
}
@ -39,7 +39,7 @@ READ8_MEMBER(cchasm_state::cchasm_coin_sound_r)
READ8_MEMBER(cchasm_state::cchasm_soundlatch2_r)
{
m_sound_flags &= ~0x80;
z80ctc_trg2_w(m_ctc, 0);
m_ctc->trg2(0);
return soundlatch2_byte_r(space, offset);
}
@ -65,7 +65,7 @@ WRITE16_MEMBER(cchasm_state::cchasm_io_w)
case 1:
m_sound_flags |= 0x80;
soundlatch2_byte_w(space, offset, data);
z80ctc_trg2_w(m_ctc, 1);
m_ctc->trg2(1);
cputag_set_input_line(machine(), "audiocpu", INPUT_LINE_NMI, PULSE_LINE);
break;
case 2:
@ -134,5 +134,5 @@ SOUND_START( cchasm )
state->m_sound_flags = 0;
state->m_output[0] = 0; state->m_output[1] = 0;
state->m_ctc = machine.device("ctc");
state->m_ctc = machine.device<z80ctc_device>("ctc");
}

4
src/mame/audio/cinemat.c
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@ -1435,8 +1435,8 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( demon_sound_ports, AS_IO, 8, driver_device )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x00, 0x03) AM_DEVWRITE_LEGACY("ctc", z80ctc_w)
AM_RANGE(0x1c, 0x1f) AM_DEVWRITE_LEGACY("ctc", z80ctc_w)
AM_RANGE(0x00, 0x03) AM_DEVWRITE("ctc", z80ctc_device, write)
AM_RANGE(0x1c, 0x1f) AM_DEVWRITE("ctc", z80ctc_device, write)
ADDRESS_MAP_END

62
src/mame/audio/senjyo.c
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@ -1,12 +1,7 @@
#include "emu.h"
#include "sound/samples.h"
#include "includes/senjyo.h"
/* single tone generator */
#define SINGLE_LENGTH 10000
#define SINGLE_DIVIDER 8
const z80_daisy_config senjyo_daisy_chain[] =
{
{ "z80ctc" },
@ -38,56 +33,23 @@ Z80PIO_INTERFACE( senjyo_pio_intf )
/* z80 ctc */
Z80CTC_INTERFACE( senjyo_ctc_intf )
{
NOTIMER_2, /* timer disables */
0, /* timer disables */
DEVCB_CPU_INPUT_LINE("sub", INPUT_LINE_IRQ0), /* interrupt handler */
DEVCB_LINE(z80ctc_trg1_w), /* ZC/TO0 callback */
DEVCB_NULL, /* ZC/TO1 callback */
DEVCB_NULL /* ZC/TO2 callback */
DEVCB_DEVICE_LINE_MEMBER("z80ctc", z80ctc_device, trg1), /* ZC/TO0 callback */
DEVCB_NULL, /* ZC/TO1 callback */
DEVCB_DRIVER_LINE_MEMBER(senjyo_state, sound_line_clock) /* ZC/TO2 callback */
};
WRITE_LINE_MEMBER(senjyo_state::sound_line_clock)
{
if (state != 0)
{
dac_signed_data_16_w(m_dac, 2184 * 2 * ((m_sound_state & 8) ? m_single_volume : 0));
m_sound_state++;
}
}
WRITE8_MEMBER(senjyo_state::senjyo_volume_w)
{
samples_device *samples = machine().device<samples_device>("samples");
m_single_volume = data & 0x0f;
samples->set_volume(0, m_single_volume / 15.0);
}
static TIMER_CALLBACK( senjyo_sh_update )
{
samples_device *samples = machine.device<samples_device>("samples");
senjyo_state *state = machine.driver_data<senjyo_state>();
/* ctc2 timer single tone generator frequency */
z80ctc_device *ctc = machine.device<z80ctc_device>("z80ctc");
attotime period = ctc->period(2);
if (period != attotime::zero)
state->m_single_rate = ATTOSECONDS_TO_HZ(period.attoseconds);
else
state->m_single_rate = 0;
samples->set_frequency(0, state->m_single_rate);
}
SAMPLES_START( senjyo_sh_start )
{
running_machine &machine = device.machine();
senjyo_state *state = machine.driver_data<senjyo_state>();
int i;
state->m_single_data = auto_alloc_array(machine, INT16, SINGLE_LENGTH);
for (i = 0;i < SINGLE_LENGTH;i++) /* freq = ctc2 zco / 8 */
state->m_single_data[i] = ((i/SINGLE_DIVIDER)&0x01)*127*256;
/* CTC2 single tone generator */
state->m_single_rate = 1000;
state->m_single_volume = 0;
device.set_volume(0, state->m_single_volume / 15.0);
device.start_raw(0, state->m_single_data, SINGLE_LENGTH, state->m_single_rate, true);
machine.scheduler().timer_pulse(machine.primary_screen->frame_period(), FUNC(senjyo_sh_update));
}

2
src/mame/drivers/astrocde.c
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@ -707,7 +707,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( tenpin_sub_io_map, AS_IO, 8, astrocde_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x90, 0x93) AM_DEVREADWRITE_LEGACY("ctc", z80ctc_r, z80ctc_w)
AM_RANGE(0x90, 0x93) AM_DEVREADWRITE("ctc", z80ctc_device, read, write)
AM_RANGE(0x97, 0x97) AM_READ(soundlatch_byte_r)
AM_RANGE(0x98, 0x98) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_w)
AM_RANGE(0x98, 0x98) AM_DEVREAD_LEGACY("aysnd", ay8910_r)

2
src/mame/drivers/cchasm.c
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@ -64,7 +64,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( sound_portmap, AS_IO, 8, cchasm_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x00, 0x03) AM_DEVREADWRITE_LEGACY("ctc", z80ctc_r, z80ctc_w)
AM_RANGE(0x00, 0x03) AM_DEVREADWRITE("ctc", z80ctc_device, read, write)
ADDRESS_MAP_END
WRITE_LINE_MEMBER(cchasm_state::cchasm_6840_irq)

4
src/mame/drivers/csplayh5.c
View File

@ -357,7 +357,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( csplayh5_sound_io_map, AS_IO, 8, csplayh5_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_DEVREADWRITE_LEGACY("ctc", z80ctc_r, z80ctc_w)
AM_RANGE(0x10, 0x13) AM_DEVREADWRITE("ctc", z80ctc_device, read, write)
AM_RANGE(0x50, 0x50) AM_READWRITE(tmpz84c011_0_pa_r, tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_READWRITE(tmpz84c011_0_pb_r, tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_READWRITE(tmpz84c011_0_pc_r, tmpz84c011_0_pc_w)
@ -567,7 +567,7 @@ static Z80CTC_INTERFACE( ctc_intf )
{
0, /* timer disables */
DEVCB_CPU_INPUT_LINE("audiocpu", INPUT_LINE_IRQ0),/* interrupt handler */
DEVCB_LINE(z80ctc_trg3_w), /* ZC/TO0 callback ctc1.zc0 -> ctc1.trg3 */
DEVCB_DEVICE_LINE_MEMBER("ctc", z80ctc_device, trg3), /* ZC/TO0 callback ctc1.zc0 -> ctc1.trg3 */
DEVCB_NULL, /* ZC/TO1 callback */
DEVCB_NULL /* ZC/TO2 callback */
};

2
src/mame/drivers/dlair.c
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@ -443,7 +443,7 @@ ADDRESS_MAP_END
/* complete memory map derived from schematics */
static ADDRESS_MAP_START( dleuro_io_map, AS_IO, 8, dlair_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x00, 0x03) AM_MIRROR(0x7c) AM_DEVREADWRITE_LEGACY("ctc", z80ctc_r, z80ctc_w)
AM_RANGE(0x00, 0x03) AM_MIRROR(0x7c) AM_DEVREADWRITE("ctc", z80ctc_device, read, write)
AM_RANGE(0x80, 0x83) AM_MIRROR(0x7c) AM_DEVREADWRITE_LEGACY("sio", z80sio_ba_cd_r, z80sio_ba_cd_w)
ADDRESS_MAP_END

2
src/mame/drivers/jankenmn.c
View File

@ -237,7 +237,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( jankenmn_port_map, AS_IO, 8, jankenmn_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x00, 0x03) AM_DEVREADWRITE_LEGACY("ctc", z80ctc_r, z80ctc_w)
AM_RANGE(0x00, 0x03) AM_DEVREADWRITE("ctc", z80ctc_device, read, write)
AM_RANGE(0x10, 0x13) AM_DEVREADWRITE("ppi8255_0", i8255_device, read, write)
AM_RANGE(0x20, 0x23) AM_DEVREADWRITE("ppi8255_1", i8255_device, read, write)
AM_RANGE(0x30, 0x30) AM_WRITENOP // ???

8
src/mame/drivers/mcr.c
View File

@ -674,7 +674,7 @@ static ADDRESS_MAP_START( cpu_90009_portmap, AS_IO, 8, mcr_state )
SSIO_INPUT_PORTS("ssio")
AM_RANGE(0xe0, 0xe0) AM_WRITE(watchdog_reset_w)
AM_RANGE(0xe8, 0xe8) AM_WRITENOP
AM_RANGE(0xf0, 0xf3) AM_DEVREADWRITE_LEGACY("ctc", z80ctc_r, z80ctc_w)
AM_RANGE(0xf0, 0xf3) AM_DEVREADWRITE("ctc", z80ctc_device, read, write)
ADDRESS_MAP_END
@ -701,7 +701,7 @@ static ADDRESS_MAP_START( cpu_90010_portmap, AS_IO, 8, mcr_state )
SSIO_INPUT_PORTS("ssio")
AM_RANGE(0xe0, 0xe0) AM_WRITE(watchdog_reset_w)
AM_RANGE(0xe8, 0xe8) AM_WRITENOP
AM_RANGE(0xf0, 0xf3) AM_DEVREADWRITE_LEGACY("ctc", z80ctc_r, z80ctc_w)
AM_RANGE(0xf0, 0xf3) AM_DEVREADWRITE("ctc", z80ctc_device, read, write)
ADDRESS_MAP_END
@ -729,7 +729,7 @@ static ADDRESS_MAP_START( cpu_91490_portmap, AS_IO, 8, mcr_state )
SSIO_INPUT_PORTS("ssio")
AM_RANGE(0xe0, 0xe0) AM_WRITE(watchdog_reset_w)
AM_RANGE(0xe8, 0xe8) AM_WRITENOP
AM_RANGE(0xf0, 0xf3) AM_DEVREADWRITE_LEGACY("ctc", z80ctc_r, z80ctc_w)
AM_RANGE(0xf0, 0xf3) AM_DEVREADWRITE("ctc", z80ctc_device, read, write)
ADDRESS_MAP_END
@ -753,7 +753,7 @@ static ADDRESS_MAP_START( ipu_91695_portmap, AS_IO, 8, mcr_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x00, 0x03) AM_MIRROR(0xe0) AM_DEVREADWRITE_LEGACY("ipu_pio0", z80pio_cd_ba_r, z80pio_cd_ba_w)
AM_RANGE(0x04, 0x07) AM_MIRROR(0xe0) AM_DEVREADWRITE_LEGACY("ipu_sio", z80sio_cd_ba_r, z80sio_cd_ba_w)
AM_RANGE(0x08, 0x0b) AM_MIRROR(0xe0) AM_DEVREADWRITE_LEGACY("ipu_ctc", z80ctc_r, z80ctc_w)
AM_RANGE(0x08, 0x0b) AM_MIRROR(0xe0) AM_DEVREADWRITE("ipu_ctc", z80ctc_device, read, write)
AM_RANGE(0x0c, 0x0f) AM_MIRROR(0xe0) AM_DEVREADWRITE_LEGACY("ipu_pio1", z80pio_cd_ba_r, z80pio_cd_ba_w)
AM_RANGE(0x10, 0x13) AM_MIRROR(0xe0) AM_WRITE(mcr_ipu_laserdisk_w)
AM_RANGE(0x1c, 0x1f) AM_MIRROR(0xe0) AM_READWRITE(mcr_ipu_watchdog_r, mcr_ipu_watchdog_w)

4
src/mame/drivers/mcr3.c
View File

@ -497,7 +497,7 @@ static ADDRESS_MAP_START( mcrmono_portmap, AS_IO, 8, mcr3_state )
AM_RANGE(0x04, 0x04) AM_MIRROR(0x78) AM_READ_PORT("MONO.IP4")
AM_RANGE(0x05, 0x05) AM_MIRROR(0x78) AM_WRITE(mcrmono_control_port_w)
AM_RANGE(0x07, 0x07) AM_MIRROR(0x78) AM_WRITE(watchdog_reset_w)
AM_RANGE(0xf0, 0xf3) AM_MIRROR(0x0c) AM_DEVREADWRITE_LEGACY("ctc", z80ctc_r, z80ctc_w)
AM_RANGE(0xf0, 0xf3) AM_MIRROR(0x0c) AM_DEVREADWRITE("ctc", z80ctc_device, read, write)
ADDRESS_MAP_END
@ -527,7 +527,7 @@ static ADDRESS_MAP_START( spyhunt_portmap, AS_IO, 8, mcr3_state )
AM_RANGE(0x84, 0x86) AM_WRITE(spyhunt_scroll_value_w)
AM_RANGE(0xe0, 0xe0) AM_WRITE(watchdog_reset_w)
AM_RANGE(0xe8, 0xe8) AM_WRITENOP
AM_RANGE(0xf0, 0xf3) AM_DEVREADWRITE_LEGACY("ctc", z80ctc_r, z80ctc_w)
AM_RANGE(0xf0, 0xf3) AM_DEVREADWRITE("ctc", z80ctc_device, read, write)
ADDRESS_MAP_END

12
src/mame/drivers/nbmj9195.c
View File

@ -613,9 +613,9 @@ WRITE8_MEMBER(nbmj9195_state::tmpz84c011_1_dir_pe_w)
/* CTC of main cpu, ch0 trigger is vblank */
static INTERRUPT_GEN( ctc0_trg1 )
{
device_t *ctc = device->machine().device("main_ctc");
z80ctc_trg1_w(ctc, 1);
z80ctc_trg1_w(ctc, 0);
z80ctc_device *ctc = device->machine().device<z80ctc_device>("main_ctc");
ctc->trg1(1);
ctc->trg1(0);
}
static Z80CTC_INTERFACE( ctc_intf_main )
@ -631,7 +631,7 @@ static Z80CTC_INTERFACE( ctc_intf_audio )
{
0, /* timer disables */
DEVCB_CPU_INPUT_LINE("audiocpu", INPUT_LINE_IRQ0),/* interrupt handler */
DEVCB_LINE(z80ctc_trg3_w), /* ZC/TO0 callback ctc1.zc0 -> ctc1.trg3 */
DEVCB_DEVICE_LINE_MEMBER("audio_ctc", z80ctc_device, trg3), /* ZC/TO0 callback ctc1.zc0 -> ctc1.trg3 */
DEVCB_NULL, /* ZC/TO1 callback */
DEVCB_NULL /* ZC/TO2 callback */
};
@ -665,7 +665,7 @@ static DRIVER_INIT( nbmj9195 )
}
static ADDRESS_MAP_START( tmpz84c011_regs, AS_IO, 8, nbmj9195_state )
AM_RANGE(0x10, 0x13) AM_DEVREADWRITE_LEGACY("main_ctc", z80ctc_r,z80ctc_w)
AM_RANGE(0x10, 0x13) AM_DEVREADWRITE("main_ctc", z80ctc_device, read, write)
AM_RANGE(0x50, 0x50) AM_READWRITE(tmpz84c011_0_pa_r,tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_READWRITE(tmpz84c011_0_pb_r,tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_READWRITE(tmpz84c011_0_pc_r,tmpz84c011_0_pc_w)
@ -1157,7 +1157,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( sailorws_sound_io_map, AS_IO, 8, nbmj9195_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_DEVREADWRITE_LEGACY("audio_ctc", z80ctc_r,z80ctc_w)
AM_RANGE(0x10, 0x13) AM_DEVREADWRITE("audio_ctc", z80ctc_device, read, write)
AM_RANGE(0x50, 0x50) AM_READWRITE(tmpz84c011_1_pa_r,tmpz84c011_1_pa_w)
AM_RANGE(0x51, 0x51) AM_READWRITE(tmpz84c011_1_pb_r,tmpz84c011_1_pb_w)
AM_RANGE(0x52, 0x52) AM_READWRITE(tmpz84c011_1_pc_r,tmpz84c011_1_pc_w)

4
src/mame/drivers/niyanpai.c
View File

@ -239,7 +239,7 @@ static Z80CTC_INTERFACE( ctc_intf )
{
0, /* timer disables */
DEVCB_CPU_INPUT_LINE("audiocpu", INPUT_LINE_IRQ0),/* interrupt handler */
DEVCB_LINE(z80ctc_trg3_w), /* ZC/TO0 callback ctc1.zc0 -> ctc1.trg3 */
DEVCB_DEVICE_LINE_MEMBER("ctc", z80ctc_device, trg3), /* ZC/TO0 callback ctc1.zc0 -> ctc1.trg3 */
DEVCB_NULL, /* ZC/TO1 callback */
DEVCB_NULL /* ZC/TO2 callback */
};
@ -497,7 +497,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( niyanpai_sound_io_map, AS_IO, 8, niyanpai_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x10, 0x13) AM_DEVREADWRITE_LEGACY("ctc", z80ctc_r, z80ctc_w)
AM_RANGE(0x10, 0x13) AM_DEVREADWRITE("ctc", z80ctc_device, read, write)
AM_RANGE(0x50, 0x50) AM_READWRITE(tmpz84c011_0_pa_r, tmpz84c011_0_pa_w)
AM_RANGE(0x51, 0x51) AM_READWRITE(tmpz84c011_0_pb_r, tmpz84c011_0_pb_w)
AM_RANGE(0x52, 0x52) AM_READWRITE(tmpz84c011_0_pc_r, tmpz84c011_0_pc_w)

2
src/mame/drivers/pipeline.c
View File

@ -208,7 +208,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( sound_port, AS_IO, 8, pipeline_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x00, 0x03) AM_DEVREADWRITE_LEGACY("ctc", z80ctc_r, z80ctc_w)
AM_RANGE(0x00, 0x03) AM_DEVREADWRITE("ctc", z80ctc_device, read, write)
AM_RANGE(0x06, 0x07) AM_NOP
ADDRESS_MAP_END

16
src/mame/drivers/proconn.c
View File

@ -38,10 +38,10 @@ public:
DECLARE_WRITE8_MEMBER( ay_w0 ) { ay8910_address_data_w(m_ay, 0, data); }
DECLARE_WRITE8_MEMBER( ay_w1 ) { ay8910_address_data_w(m_ay, 1, data); }
DECLARE_WRITE8_MEMBER( ctc_w0 ) { z80ctc_w(m_z80ctc, 0, data); }
DECLARE_WRITE8_MEMBER( ctc_w1 ) { z80ctc_w(m_z80ctc, 1, data); }
DECLARE_WRITE8_MEMBER( ctc_w2 ) { z80ctc_w(m_z80ctc, 2, data); }
DECLARE_WRITE8_MEMBER( ctc_w3 ) { z80ctc_w(m_z80ctc, 3, data); }
DECLARE_WRITE8_MEMBER( ctc_w0 ) { m_z80ctc->write(0, data); }
DECLARE_WRITE8_MEMBER( ctc_w1 ) { m_z80ctc->write(1, data); }
DECLARE_WRITE8_MEMBER( ctc_w2 ) { m_z80ctc->write(2, data); }
DECLARE_WRITE8_MEMBER( ctc_w3 ) { m_z80ctc->write(3, data); }
DECLARE_WRITE8_MEMBER( sio_w0 ) { z80sio_cd_ba_w(m_z80sio, 0, data); }
DECLARE_WRITE8_MEMBER( sio_w1 ) { z80sio_cd_ba_w(m_z80sio, 1, data); }
@ -75,10 +75,10 @@ public:
DECLARE_READ8_MEMBER( ay_r0 ) { return ay8910_r(m_ay, 0); }
DECLARE_READ8_MEMBER( ctc_r0 ) { return z80ctc_r(m_z80ctc, 0); }
DECLARE_READ8_MEMBER( ctc_r1 ) { return z80ctc_r(m_z80ctc, 1); }
DECLARE_READ8_MEMBER( ctc_r2 ) { return z80ctc_r(m_z80ctc, 2); }
DECLARE_READ8_MEMBER( ctc_r3 ) { return z80ctc_r(m_z80ctc, 3); }
DECLARE_READ8_MEMBER( ctc_r0 ) { return m_z80ctc->read(0); }
DECLARE_READ8_MEMBER( ctc_r1 ) { return m_z80ctc->read(1); }
DECLARE_READ8_MEMBER( ctc_r2 ) { return m_z80ctc->read(2); }
DECLARE_READ8_MEMBER( ctc_r3 ) { return m_z80ctc->read(3); }
DECLARE_READ8_MEMBER( sio_r0 ) { return z80sio_cd_ba_r(m_z80sio, 0); }
DECLARE_READ8_MEMBER( sio_r1 ) { return z80sio_cd_ba_r(m_z80sio, 1); }

14
src/mame/drivers/senjyo.c
View File

@ -175,7 +175,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( senjyo_sound_io_map, AS_IO, 8, senjyo_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x00, 0x03) AM_DEVREADWRITE_LEGACY("z80pio", z80pio_ba_cd_r, z80pio_ba_cd_w)
AM_RANGE(0x08, 0x0b) AM_DEVREADWRITE_LEGACY("z80ctc", z80ctc_r, z80ctc_w)
AM_RANGE(0x08, 0x0b) AM_DEVREADWRITE("z80ctc", z80ctc_device, read, write)
ADDRESS_MAP_END
/* For the bootleg */
@ -552,14 +552,6 @@ GFXDECODE_END
static const samples_interface senjyo_samples_interface =
{
1,
NULL,
senjyo_sh_start
};
static MACHINE_CONFIG_START( senjyo, senjyo_state )
/* basic machine hardware */
@ -602,8 +594,8 @@ static MACHINE_CONFIG_START( senjyo, senjyo_state )
MCFG_SOUND_ADD("sn3", SN76496, 2000000)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
MCFG_SAMPLES_ADD("samples", senjyo_samples_interface)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.15)
MCFG_SOUND_ADD("dac", DAC, 0)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.05)
MACHINE_CONFIG_END

2
src/mame/includes/cchasm.h
View File

@ -15,7 +15,7 @@ public:
int m_sound_flags;
int m_coin_flag;
device_t *m_ctc;
z80ctc_device *m_ctc;
int m_channel_active[2];
int m_output[2];
required_shared_ptr<UINT16> m_ram;

11
src/mame/includes/senjyo.h
View File

@ -1,4 +1,4 @@
#include "sound/samples.h"
#include "sound/dac.h"
#include "cpu/z80/z80daisy.h"
#include "machine/z80pio.h"
#include "machine/z80ctc.h"
@ -7,7 +7,8 @@ class senjyo_state : public driver_device
{
public:
senjyo_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag) ,
: driver_device(mconfig, type, tag),
m_dac(*this, "dac"),
m_spriteram(*this, "spriteram"),
m_fgscroll(*this, "fgscroll"),
m_scrollx1(*this, "scrollx1"),
@ -29,6 +30,9 @@ public:
INT16 *m_single_data;
int m_single_rate;
int m_single_volume;
int m_sound_state;
required_device<dac_device> m_dac;
required_shared_ptr<UINT8> m_spriteram;
required_shared_ptr<UINT8> m_fgscroll;
@ -64,6 +68,7 @@ public:
DECLARE_WRITE8_MEMBER(senjyo_bg3videoram_w);
DECLARE_WRITE8_MEMBER(senjyo_bgstripes_w);
DECLARE_WRITE8_MEMBER(senjyo_volume_w);
DECLARE_WRITE_LINE_MEMBER(sound_line_clock);
DECLARE_WRITE8_MEMBER(sound_cmd_w);
};
@ -74,8 +79,6 @@ extern const z80_daisy_config senjyo_daisy_chain[];
extern const z80pio_interface senjyo_pio_intf;
extern const z80ctc_interface senjyo_ctc_intf;
SAMPLES_START( senjyo_sh_start );
/*----------- defined in video/senjyo.c -----------*/

18
src/mame/machine/mcr.c
View File

@ -106,7 +106,7 @@ Z80CTC_INTERFACE( mcr_ctc_intf )
{
0, /* timer disables */
DEVCB_CPU_INPUT_LINE("maincpu", INPUT_LINE_IRQ0), /* interrupt handler */
DEVCB_LINE(z80ctc_trg1_w), /* ZC/TO0 callback */
DEVCB_DEVICE_LINE_MEMBER("ctc", z80ctc_device, trg1), /* ZC/TO0 callback */
DEVCB_NULL, /* ZC/TO1 callback */
DEVCB_NULL /* ZC/TO2 callback */
};
@ -187,38 +187,38 @@ MACHINE_RESET( mcr )
TIMER_DEVICE_CALLBACK( mcr_interrupt )
{
//mcr_state *state = timer.machine().driver_data<mcr_state>();
device_t *ctc = timer.machine().device("ctc");
z80ctc_device *ctc = timer.machine().device<z80ctc_device>("ctc");
int scanline = param;
/* CTC line 2 is connected to VBLANK, which is once every 1/2 frame */
/* for the 30Hz interlaced display */
if(scanline == 0 || scanline == 240)
{
z80ctc_trg2_w(ctc, 1);
z80ctc_trg2_w(ctc, 0);
ctc->trg2(1);
ctc->trg2(0);
}
/* CTC line 3 is connected to 493, which is signalled once every */
/* frame at 30Hz */
if (scanline == 0)
{
z80ctc_trg3_w(ctc, 1);
z80ctc_trg3_w(ctc, 0);
ctc->trg3(1);
ctc->trg3(0);
}
}
TIMER_DEVICE_CALLBACK( mcr_ipu_interrupt )
{
//mcr_state *state = timer.machine().driver_data<mcr_state>();
device_t *ctc = timer.machine().device("ctc");
z80ctc_device *ctc = timer.machine().device<z80ctc_device>("ctc");
int scanline = param;
/* CTC line 3 is connected to 493, which is signalled once every */
/* frame at 30Hz */
if (scanline == 0)
{
z80ctc_trg3_w(ctc, 1);
z80ctc_trg3_w(ctc, 0);
ctc->trg3(1);
ctc->trg3(0);
}
}