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fidel_eag68k: disable_interrupt_mixer for feagv5 (nw)
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@ -35,6 +35,10 @@ constexpr int M68K_IRQ_5 = 5;
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constexpr int M68K_IRQ_6 = 6;
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constexpr int M68K_IRQ_7 = 7;
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constexpr int M68K_IRQ_IPL0 = 0;
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constexpr int M68K_IRQ_IPL1 = 1;
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constexpr int M68K_IRQ_IPL2 = 2;
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constexpr int M68K_SZ_LONG = 0;
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constexpr int M68K_SZ_BYTE = 1;
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constexpr int M68K_SZ_WORD = 2;
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@ -657,7 +657,7 @@ Stephh's inputs notes (based on some tests on the "parent" set) :
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TIMER_DEVICE_CALLBACK_MEMBER(cps2_state::cps2_interrupt)
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{
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/* direct irq line connection, irq1 is vblank, irq2 is some sort of scanline interrupt. */
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/* direct irq line connection, IPL1 is vblank, IPL2 is some sort of scanline interrupt. */
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if (param == 0)
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m_scancalls = 0;
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@ -173,6 +173,7 @@ class eag_state : public fidelbase_state
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public:
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eag_state(const machine_config &mconfig, device_type type, const char *tag) :
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fidelbase_state(mconfig, type, tag),
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m_maincpu(*this, "maincpu"),
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m_ram(*this, "ram")
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{ }
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@ -191,6 +192,7 @@ protected:
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void eag_base(machine_config &config);
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// devices/pointers
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required_device<m68000_base_device> m_maincpu;
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optional_device<ram_device> m_ram;
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// address maps
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@ -519,12 +521,13 @@ void eag_state::eag_base(machine_config &config)
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{
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/* basic machine hardware */
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M68000(config, m_maincpu, 16_MHz_XTAL);
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m_maincpu->disable_interrupt_mixer();
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m_maincpu->set_addrmap(AS_PROGRAM, &eag_state::eag_map);
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const attotime irq_period = attotime::from_hz(4.9152_MHz_XTAL/0x2000); // 4060 Q13, 600Hz
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TIMER(config, m_irq_on).configure_periodic(FUNC(eag_state::irq_on<M68K_IRQ_2>), irq_period);
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TIMER(config, m_irq_on).configure_periodic(FUNC(eag_state::irq_on<M68K_IRQ_IPL1>), irq_period);
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m_irq_on->set_start_delay(irq_period - attotime::from_nsec(8250)); // active for 8.25us
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TIMER(config, "irq_off").configure_periodic(FUNC(eag_state::irq_off<M68K_IRQ_2>), irq_period);
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TIMER(config, "irq_off").configure_periodic(FUNC(eag_state::irq_off<M68K_IRQ_IPL1>), irq_period);
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NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_1);
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@ -573,7 +576,7 @@ void eagv5_state::eagv5(machine_config &config)
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GENERIC_LATCH_8(config, m_mainlatch);
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GENERIC_LATCH_8(config, m_sublatch);
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m_sublatch->data_pending_callback().set_inputline(m_maincpu, M68K_IRQ_1); // IPL0
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m_sublatch->data_pending_callback().set_inputline(m_maincpu, M68K_IRQ_IPL0);
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// gen_latch syncs on write, but this is still needed with tight cpu comms
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// (not that it locks up or anything, but it will calculate moves much slower if timing is off)
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@ -586,6 +589,7 @@ void eag_state::eagv7(machine_config &config)
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/* basic machine hardware */
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M68020(config.replace(), m_maincpu, 20_MHz_XTAL); // also seen with 25MHz XTAL
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m_maincpu->disable_interrupt_mixer();
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m_maincpu->set_addrmap(AS_PROGRAM, &eag_state::eagv7_map);
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}
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@ -595,6 +599,7 @@ void eag_state::eagv9(machine_config &config)
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/* basic machine hardware */
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M68030(config.replace(), m_maincpu, 32_MHz_XTAL/2); // also seen with 40MHz XTAL
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m_maincpu->disable_interrupt_mixer();
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m_maincpu->set_addrmap(AS_PROGRAM, &eag_state::eagv7_map);
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}
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@ -604,6 +609,7 @@ void eag_state::eagv10(machine_config &config)
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/* basic machine hardware */
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M68040(config.replace(), m_maincpu, 25_MHz_XTAL);
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m_maincpu->disable_interrupt_mixer();
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m_maincpu->set_addrmap(AS_PROGRAM, &eag_state::eagv10_map);
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}
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