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https://github.com/holub/mame
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r4000.cpp: partially implement secondary cache tag manipulation (#9923)
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Brice Onken
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084c103df0
@ -55,6 +55,8 @@
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// experimental primary instruction cache
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#define ICACHE 0
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#define SCACHE !(m_cp0[CP0_Config] & CONFIG_SC)
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#include "logmacro.h"
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#define USE_ABI_REG_NAMES 1
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@ -197,6 +199,9 @@ void r4000_base_device::device_start()
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m_icache_data = std::make_unique<u32 []>((0x1000U << config_ic) >> 2);
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R4000_ENDIAN_LE_BE(accessors(m_le), accessors(m_be));
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if (SCACHE)
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save_pointer(NAME(m_scache_tag), m_scache_tag_size);
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}
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void r4000_base_device::device_reset()
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@ -945,75 +950,7 @@ void r4000_base_device::cpu_execute(u32 const op)
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cpu_swr(op);
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break;
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case 0x2f: // CACHE
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if ((SR & SR_KSU) && !(SR & SR_CU0) && !(SR & (SR_EXL | SR_ERL)))
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{
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cpu_exception(EXCEPTION_CP0);
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break;
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}
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switch ((op >> 16) & 0x1f)
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{
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case 0x00: // index invalidate (I)
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if (ICACHE)
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{
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m_icache_tag[(ADDR(m_r[RSREG], s16(op)) & m_icache_mask_hi) >> m_icache_shift] &= ~ICACHE_V;
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break;
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}
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[[fallthrough]];
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case 0x04: // index load tag (I)
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if (ICACHE)
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{
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u32 const tag = m_icache_tag[(ADDR(m_r[RSREG], s16(op)) & m_icache_mask_hi) >> m_icache_shift];
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m_cp0[CP0_TagLo] = ((tag & ICACHE_PTAG) << 8) | ((tag & ICACHE_V) >> 18) | ((tag & ICACHE_P) >> 25);
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m_cp0[CP0_ECC] = 0; // data ecc or parity
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break;
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}
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[[fallthrough]];
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case 0x08: // index store tag (I)
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if (ICACHE)
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{
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// FIXME: compute parity
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m_icache_tag[(ADDR(m_r[RSREG], s16(op)) & m_icache_mask_hi) >> m_icache_shift] =
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(m_cp0[CP0_TagLo] & TAGLO_PTAGLO) >> 8 | (m_cp0[CP0_TagLo] & TAGLO_PSTATE) << 18;
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break;
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}
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[[fallthrough]];
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case 0x01: // index writeback invalidate (D)
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case 0x02: // index invalidate (SI)
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case 0x03: // index writeback invalidate (SD)
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case 0x05: // index load tag (D)
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case 0x06: // index load tag (SI)
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case 0x07: // index load tag (SI)
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case 0x09: // index store tag (D)
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case 0x0a: // index store tag (SI)
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case 0x0b: // index store tag (SD)
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case 0x0d: // create dirty exclusive (D)
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case 0x0f: // create dirty exclusive (SD)
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case 0x10: // hit invalidate (I)
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case 0x11: // hit invalidate (D)
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case 0x12: // hit invalidate (SI)
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case 0x13: // hit invalidate (SD)
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case 0x14: // fill (I)
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case 0x15: // hit writeback invalidate (D)
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case 0x17: // hit writeback invalidate (SD)
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case 0x18: // hit writeback (I)
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case 0x19: // hit writeback (D)
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case 0x1b: // hit writeback (SD)
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case 0x1e: // hit set virtual (SI)
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case 0x1f: // hit set virtual (SD)
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//LOGMASKED(LOG_CACHE, "cache 0x%08x unimplemented (%s)\n", op, machine().describe_context());
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break;
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}
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cp0_cache(op);
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break;
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case 0x30: // LL
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load_linked<u32>(ADDR(m_r[RSREG], s16(op)),
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@ -1263,6 +1200,128 @@ void r4000_base_device::cpu_sdr(u32 const op)
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store<u64, false>(offset, m_r[RTREG] << shift, ~u64(0) << shift);
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}
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void r4000_base_device::cp0_cache(u32 const op)
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{
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if ((SR & SR_KSU) && !(SR & SR_CU0) && !(SR & (SR_EXL | SR_ERL)))
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{
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cpu_exception(EXCEPTION_CP0);
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return;
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}
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switch ((op >> 16) & 0x1f)
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{
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case 0x00: // index invalidate (I)
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if (ICACHE)
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{
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m_icache_tag[(ADDR(m_r[RSREG], s16(op)) & m_icache_mask_hi) >> m_icache_shift] &= ~ICACHE_V;
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break;
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}
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[[fallthrough]];
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case 0x04: // index load tag (I)
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if (ICACHE)
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{
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u32 const tag = m_icache_tag[(ADDR(m_r[RSREG], s16(op)) & m_icache_mask_hi) >> m_icache_shift];
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m_cp0[CP0_TagLo] = ((tag & ICACHE_PTAG) << 8) | ((tag & ICACHE_V) >> 18) | ((tag & ICACHE_P) >> 25);
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m_cp0[CP0_ECC] = 0; // data ecc or parity
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break;
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}
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[[fallthrough]];
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case 0x08: // index store tag (I)
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if (ICACHE)
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{
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// FIXME: compute parity
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m_icache_tag[(ADDR(m_r[RSREG], s16(op)) & m_icache_mask_hi) >> m_icache_shift] =
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(m_cp0[CP0_TagLo] & TAGLO_PTAGLO) >> 8 | (m_cp0[CP0_TagLo] & TAGLO_PSTATE) << 18;
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break;
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}
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[[fallthrough]];
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case 0x01: // index writeback invalidate (D)
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case 0x02: // index invalidate (SI)
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case 0x03: // index writeback invalidate (SD)
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case 0x05: // index load tag (D)
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//LOGMASKED(LOG_CACHE, "cache 0x%08x unimplemented (%s)\n", op, machine().describe_context());
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break;
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case 0x06: // index load tag (SI)
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case 0x07: // index load tag (SD)
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if (SCACHE)
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{
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// TODO: translation type for CACHE instruction? Read seems reasonable since only the tag is changing here
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u64 physical_address = ADDR(m_r[RSREG], s16(op));
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translate_result const t = translate(TRANSLATE_READ, physical_address);
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if (t == ERROR || t == MISS)
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return;
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u32 const index = (physical_address & m_scache_tag_mask) >> m_scache_line_index;
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if (index < m_scache_tag_size)
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{
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// TODO: Load the ECC register here
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u32 const tag = m_scache_tag[index];
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u32 const cs = (tag & SCACHE_CS) >> 22;
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u32 const stag = tag & SCACHE_STAG;
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u32 const pidx = (tag & SCACHE_PIDX) >> 19;
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m_cp0[CP0_TagLo] = (stag << 13) | (cs << 10) | (pidx << 7);
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}
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else
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fatalerror("r4000 scache load tag index out of range!");
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}
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else
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LOGMASKED(LOG_CACHE, "cache 0x%08x called without scache enabled (%s)\n", op, machine().describe_context());
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break;
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case 0x09: // index store tag (D)
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//LOGMASKED(LOG_CACHE, "cache 0x%08x unimplemented (%s)\n", op, machine().describe_context());
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break;
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case 0x0a: // index store tag (SI)
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case 0x0b: // index store tag (SD)
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if (SCACHE)
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{
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// TODO: translation type for CACHE instruction? Read seems reasonable since only the tag is changing here
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u64 const virtual_address = ADDR(m_r[RSREG], s16(op));
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u64 physical_address = virtual_address;
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translate_result const t = translate(TRANSLATE_READ, physical_address);
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if (t == ERROR || t == MISS)
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return;
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u64 const index = (physical_address & m_scache_tag_mask) >> m_scache_line_index;
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if (index < m_scache_tag_size)
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{
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// TODO: Calculate ECC bits here
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u64 const tag_lo = m_cp0[CP0_TagLo];
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u32 const cs = (tag_lo & TAGLO_CS) >> 10;
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u32 const stag = (tag_lo & TAGLO_STAG) >> 13;
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u32 const pidx = (virtual_address & 0x7000) >> 12;
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m_scache_tag[index] = cs << 22 | pidx << 19 | stag;
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}
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else
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fatalerror("r4000 scache store tag index out of range!");
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}
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else
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LOGMASKED(LOG_CACHE, "cache 0x%08x called without scache enabled (%s)\n", op, machine().describe_context());
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break;
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case 0x0d: // create dirty exclusive (D)
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case 0x0f: // create dirty exclusive (SD)
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case 0x10: // hit invalidate (I)
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case 0x11: // hit invalidate (D)
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case 0x12: // hit invalidate (SI)
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case 0x13: // hit invalidate (SD)
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case 0x14: // fill (I)
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case 0x15: // hit writeback invalidate (D)
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case 0x17: // hit writeback invalidate (SD)
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case 0x18: // hit writeback (I)
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case 0x19: // hit writeback (D)
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case 0x1b: // hit writeback (SD)
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case 0x1e: // hit set virtual (SI)
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case 0x1f: // hit set virtual (SD)
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//LOGMASKED(LOG_CACHE, "cache 0x%08x unimplemented (%s)\n", op, machine().describe_context());
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break;
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}
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}
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void r4000_base_device::cp0_execute(u32 const op)
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{
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if ((SR & SR_KSU) && !(SR & SR_CU0) && !(SR & (SR_EXL | SR_ERL)))
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@ -4021,3 +4080,46 @@ std::string r4000_base_device::debug_unicode_string(u64 unicode_string_pointer)
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return utf8_from_wstring(result);
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}
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void r4000_base_device::configure_scache()
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{
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if (m_scache_size > 0)
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{
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/*
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* Secondary cache tag size depends on the cache line size
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* (how many bytes are transferred with one cache operation) and the
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* size of the cache itself.
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* For example, the Sony NEWS NWS-5000X has a 1MB secondary cache
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* and a cache line size of 16 words. So, the slice of the physical
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* address used to index into the cache is bits 19:6.
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* See chapter 11 of the R4000 user manual for more details.
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*/
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if (m_scache_line_size == 0)
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fatalerror("SCACHE size set but line size was not set!");
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if (m_scache_line_size <= 0x10)
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m_scache_line_index = 4;
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else if (m_scache_line_size <= 0x20)
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{
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m_scache_line_index = 5;
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m_cp0[CP0_Config] |= 1 << 22;
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}
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else if (m_scache_line_size <= 0x40)
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{
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m_scache_line_index = 6;
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m_cp0[CP0_Config] |= 2 << 22;
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}
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else
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{
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m_scache_line_index = 7;
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m_cp0[CP0_Config] |= 3 << 22;
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}
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m_scache_tag_size = m_scache_size >> m_scache_line_index;
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m_scache_tag_mask = m_scache_size - 1;
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m_scache_tag = std::make_unique<u32[]>(m_scache_tag_size);
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}
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else
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m_cp0[CP0_Config] |= CONFIG_SC;
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}
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@ -291,6 +291,8 @@ protected:
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TAGLO_PTAGLO = 0xffffff00, // physical adddress bits 35:12
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TAGLO_PSTATE = 0x000000c0, // primary cache state
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TAGLO_P = 0x00000001, // primary tag even parity
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TAGLO_CS = 0x00001c00, // scache status
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TAGLO_STAG = 0xffffe000, // scache tag
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};
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enum icache_mask : u32
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{
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@ -306,6 +308,12 @@ protected:
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DCACHE_W = 0x02000000, // write-back
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DCACHE_WP = 0x02000000, // even parity for write-back
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};
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enum scache_mask : u32
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{
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SCACHE_CS = 0x01c00000, // cache state
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SCACHE_STAG = 0x0007ffff, // physical tag
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SCACHE_PIDX = 0x00380000, // primary cache index
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};
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// device_t overrides
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virtual void device_start() override;
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@ -342,6 +350,7 @@ protected:
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void cpu_sdr(u32 const op);
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// cp0 implementation
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void cp0_cache(u32 const op);
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void cp0_execute(u32 const op);
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u64 cp0_get(unsigned const reg);
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void cp0_set(unsigned const reg, u64 const data);
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@ -383,6 +392,9 @@ protected:
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std::string debug_string_array(u64 array_pointer);
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std::string debug_unicode_string(u64 unicode_string_pointer);
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// configuration helpers
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void configure_scache();
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// device configuration state
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address_space_config m_program_config_le;
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address_space_config m_program_config_be;
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@ -458,6 +470,14 @@ protected:
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std::unique_ptr<u32[]> m_icache_tag;
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std::unique_ptr<u32[]> m_icache_data;
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// experimental scache state
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u32 m_scache_size; // Size in bytes
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u8 m_scache_line_size;
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u32 m_scache_line_index; // Secondary cache line shift
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u32 m_scache_tag_mask; // Mask for extracting the tag from a physical address
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u32 m_scache_tag_size;
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std::unique_ptr<u32[]> m_scache_tag;
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// statistics
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u64 m_tlb_scans;
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u64 m_tlb_loops;
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@ -485,15 +505,16 @@ public:
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class r4400_device : public r4000_base_device
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{
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public:
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r4400_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock, bool timer_interrupt_disabled)
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r4400_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock, bool timer_interrupt_disabled, u32 scache_size, u8 scache_line_size)
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: r4000_base_device(mconfig, R4400, tag, owner, clock, 0x0440, 0x0500, CACHE_16K, CACHE_16K, 10, 20, 69, 133, timer_interrupt_disabled)
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{
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// no secondary cache
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m_cp0[CP0_Config] |= CONFIG_SC;
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m_scache_size = scache_size;
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m_scache_line_size = scache_line_size;
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configure_scache();
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}
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r4400_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
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: r4400_device(mconfig, tag, owner, clock, false)
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: r4400_device(mconfig, tag, owner, clock, false, 0, 0)
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{
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}
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};
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