diff --git a/src/devices/machine/68561mpcc.cpp b/src/devices/machine/68561mpcc.cpp index 0535d36fb5e..347c0b425e7 100644 --- a/src/devices/machine/68561mpcc.cpp +++ b/src/devices/machine/68561mpcc.cpp @@ -56,7 +56,7 @@ FEATURES #define LOG_SYNC 0x400 #define LOG_CHAR 0x800 -#define VERBOSE 0 // (LOG_PRINTF | LOG_SETUP | LOG_GENERAL) +#define VERBOSE 0 // (LOG_PRINTF | LOG_SETUP) // | LOG_GENERAL) #define LOGMASK(mask, ...) do { if (VERBOSE & mask) logerror(__VA_ARGS__); } while (0) #define LOGLEVEL(mask, level, ...) do { if ((VERBOSE & mask) >= level) logerror(__VA_ARGS__); } while (0) @@ -363,11 +363,9 @@ void mpcc_device::rcv_callback() } } - //------------------------------------------------- // rcv_complete - //------------------------------------------------- - void mpcc_device::rcv_complete() { uint8_t data; @@ -504,31 +502,31 @@ READ8_MEMBER( mpcc_device::read ) switch(offset) { - case 0x00: data = m_rsr; logerror("MPCC: Reg RSR not implemented\n"); break; - case 0x01: data = m_rcr; logerror("MPCC: Reg RCR not implemented\n"); break; + case 0x00: data = do_rsr(); break; + case 0x01: data = do_rcr(); break; case 0x02: data = m_rdr; logerror("MPCC: Reg RDR not implemented\n"); break; case 0x04: data = m_rivnr; logerror("MPCC: Reg RIVNR not implemented\n"); break; - case 0x05: data = m_rier; logerror("MPCC: Reg RIER not implemented\n"); break; + case 0x05: data = do_rier(); break; case 0x08: data = m_tsr; break; logerror("MPCC: Reg TSR not implemented\n"); break; - case 0x09: data = m_tcr; logerror("MPCC: Reg TCR not implemented\n"); break; - //case 0x0a: data = m_tdr; break; - case 0x0c: data = m_tivnr; logerror("MPCC: Reg TIVNR not implemented\n"); break; - case 0x0d: data = m_tier; logerror("MPCC: Reg TIER not implemented\n"); break; + case 0x09: data = do_tcr(); break; + //case 0x0a: data = m_tdr; break; // TDR is a write only register + case 0x0c: data = do_tivnr(); break; + case 0x0d: data = do_tier(); break; case 0x10: data = m_sisr; logerror("MPCC: Reg SISR not implemented\n"); break; - case 0x11: data = m_sicr; logerror("MPCC: Reg SICR not implemented\n"); break; + case 0x11: data = do_sicr(); break; case 0x14: data = m_sivnr; logerror("MPCC: Reg SIVNR not implemented\n"); break; - case 0x15: data = m_sier; logerror("MPCC: Reg SIER not implemented\n"); break; - case 0x18: data = m_psr1; logerror("MPCC: Reg PSR1 not implemented\n"); break; - case 0x19: data = m_psr2; logerror("MPCC: Reg PSR2 not implemented\n"); break; + case 0x15: data = do_sier(); break; + case 0x18: data = do_psr1(); break; + case 0x19: data = do_psr2(); break; case 0x1a: data = m_ar1; logerror("MPCC: Reg AR1 not implemented\n"); break; case 0x1b: data = m_ar2; logerror("MPCC: Reg AR2 not implemented\n"); break; - case 0x1c: data = m_brdr1; logerror("MPCC: Reg BRDR1 not implemented\n"); break; - case 0x1d: data = m_brdr2; logerror("MPCC: Reg BRDR2 not implemented\n"); break; - case 0x1e: data = m_ccr; logerror("MPCC: Reg CCR not implemented\n"); break; - case 0x1f: data = m_ecr; logerror("MPCC: Reg ECR not implemented\n"); break; + case 0x1c: data = do_brdr1(); break; + case 0x1d: data = do_brdr2(); break; + case 0x1e: data = do_ccr(); break; + case 0x1f: data = do_ecr(); break; default: logerror("%s invalid register accessed: %02x\n", m_owner->tag(), offset); } - LOGSETUP(" * %s Reg %02x -> %02x \n", m_owner->tag(), offset, data); + LOGR(" * %s Reg %02x -> %02x \n", m_owner->tag(), offset, data); return data; } @@ -540,34 +538,86 @@ WRITE8_MEMBER( mpcc_device::write ) LOGSETUP(" * %s Reg %02x <- %02x \n", m_owner->tag(), offset, data); switch(offset) { - case 0x00: m_rsr = data; logerror("MPCC: Reg RSR not implemented\n"); break; - case 0x01: m_rcr = data; logerror("MPCC: Reg RCR not implemented\n"); break; - //case 0x02: m_rdr = data; break; + case 0x00: do_rsr(data); break; + case 0x01: do_rcr(data); break; + //case 0x02: m_rdr = data; break; // RDR is a read only register case 0x04: m_rivnr = data; logerror("MPCC: Reg RIVNR not implemented\n"); break; - case 0x05: m_rier = data; logerror("MPCC: Reg RIER not implemented\n"); break; + case 0x05: do_rier(data); break; case 0x08: m_tsr = data; logerror("MPCC: Reg TSR not implemented\n"); break; - case 0x09: m_tcr = data; logerror("MPCC: Reg TCR not implemented\n"); break; - case 0x0a: m_tdr = data; LOGCHAR("*%c", data); do_tdr_w(data); break; - case 0x0c: m_tivnr = data; logerror("MPCC: Reg TIVNR not implemented\n"); break; - case 0x0d: m_tier = data; logerror("MPCC: Reg TIER not implemented\n"); break; + case 0x09: do_tcr(data); break; + case 0x0a: m_tdr = data; LOGCHAR("*%c", data); do_tdr(data); break; + case 0x0c: do_tivnr(data); break; + case 0x0d: do_tier(data); break; case 0x10: m_sisr = data; logerror("MPCC: Reg SISR not implemented\n"); break; - case 0x11: m_sicr = data; logerror("MPCC: Reg SICR not implemented\n"); break; + case 0x11: do_sicr(data); break; case 0x14: m_sivnr = data; logerror("MPCC: Reg SIVNR not implemented\n"); break; - case 0x15: m_sier = data; logerror("MPCC: Reg SIER not implemented\n"); break; - case 0x18: m_psr1 = data; logerror("MPCC: Reg PSR1 not implemented\n"); break; - case 0x19: m_psr2 = data; logerror("MPCC: Reg PSR2 not implemented\n"); break; + case 0x15: do_sier(data); break; + case 0x18: do_psr1(data); break; + case 0x19: do_psr2(data); break; case 0x1a: m_ar1 = data; logerror("MPCC: Reg AR1 not implemented\n"); break; case 0x1b: m_ar2 = data; logerror("MPCC: Reg AR2 not implemented\n"); break; - case 0x1c: m_brdr1 = data; logerror("MPCC: Reg BRDR1 not implemented\n"); break; - case 0x1d: m_brdr2 = data; logerror("MPCC: Reg BRDR2 not implemented\n"); break; - case 0x1e: m_ccr = data; logerror("MPCC: Reg CCR not implemented\n"); break; - case 0x1f: m_ecr = data; logerror("MPCC: Reg ECR not implemented\n"); break; + case 0x1c: do_brdr1(data); break; + case 0x1d: do_brdr2(data); break; + case 0x1e: do_ccr(data); break; + case 0x1f: do_ecr(data); break; default: logerror("%s invalid register accessed: %02x\n", m_owner->tag(), offset); } } -void mpcc_device::do_tdr_w(uint8_t data) +void mpcc_device::do_rsr(uint8_t data) { + LOG("%s -> %02x\n", FUNCNAME, data); + m_rsr = data; +} + +uint8_t mpcc_device::do_rsr() +{ + uint8_t data = m_rsr; + LOG("%s <- %02x\n", FUNCNAME, data); + return data; +} + +void mpcc_device::do_rcr(uint8_t data) +{ + LOG("%s -> %02x\n", FUNCNAME, data); + m_rcr = data; + LOGSETUP(" - Rx DMA : %s\n", (m_rcr & REG_RCR_RDSREN) ? "enabled" : "disabled"); + LOGSETUP(" - Rx DONE out : %s\n", (m_rcr & REG_RCR_DONEEN) ? "enabled" : "disabled"); + LOGSETUP(" - Rx RSYN out : %s\n", (m_rcr & REG_RCR_RSYNEN) ? "enabled" : "disabled"); + LOGSETUP(" - Rx strip SYN: %s\n", (m_rcr & REG_RCR_STRSYN) ? "enabled" : "disabled"); + LOGSETUP(" - Rx Abort : %s\n", (m_rcr & REG_RCR_RABTEN) ? "enabled" : "disabled"); + LOGSETUP(" - Rx Mode : %s\n", (m_rcr & REG_RCR_RRES ) ? "reset" : "normal"); +} + +uint8_t mpcc_device::do_rcr() +{ + uint8_t data = m_rcr; + LOG("%s <- %02x\n", FUNCNAME, data); + return data; +} + +void mpcc_device::do_rier(uint8_t data) +{ + LOG("%s -> %02x\n", FUNCNAME, data); + m_rier = data; + LOGSETUP(" - Rx INT on Rx data available : %s\n", (m_rier & REG_RIER_RDA) ? "enabled" : "disabled"); + LOGSETUP(" - Rx INT on End of Frame : %s\n", (m_rier & REG_RIER_EOF) ? "enabled" : "disabled"); + LOGSETUP(" - Rx INT on CRC/Parity error : %s\n", (m_rier & REG_RIER_CPERR) ? "enabled" : "disabled"); + LOGSETUP(" - Rx INT on Frame error : %s\n", (m_rier & REG_RIER_FRERR) ? "enabled" : "disabled"); + LOGSETUP(" - Rx INT on Receiver overrun : %s\n", (m_rier & REG_RIER_ROVRN) ? "enabled" : "disabled"); + LOGSETUP(" - Rx INT on Abort/Break : %s\n", (m_rier & REG_RIER_RAB) ? "enabled" : "disabled"); +} + +uint8_t mpcc_device::do_rier() +{ + uint8_t data = m_rier; + LOG("%s <- %02x\n", FUNCNAME, data); + return data; +} + +void mpcc_device::do_tdr(uint8_t data) +{ + LOG("%s -> %d [%c]\n", FUNCNAME, data, isprint(data) ? data : ' '); // Check of Tx fifo has room if (m_tx_data_fifo.full()) { @@ -583,3 +633,194 @@ void mpcc_device::do_tdr_w(uint8_t data) } } } + +void mpcc_device::do_tcr(uint8_t data) +{ + LOG("%s -> %02x\n", FUNCNAME, data); + m_tcr = data; + LOGSETUP(" - Tx : %s\n", (m_tcr & REG_TCR_TEN) ? "enabled" : "disabled"); + LOGSETUP(" - Tx DMA : %s\n", (m_tcr & REG_TCR_TDSREN) ? "enabled" : "disabled"); + LOGSETUP(" - Tx Idle character : %s\n", (m_tcr & REG_TCR_TICS) ? "AR2" : "high"); + LOGSETUP(" - Tx Half Word next : %s\n", (m_tcr & REG_TCR_THW) ? "yes" : "no"); + LOGSETUP(" - Tx Last character : %s\n", (m_tcr & REG_TCR_TLAST) ? "yes" : "no"); + LOGSETUP(" - Tx SYN : %s\n", (m_tcr & REG_TCR_TSYN) ? "enabled" : "disabled"); + LOGSETUP(" - Tx Abort command : %s\n", (m_tcr & REG_TCR_TABT) ? "active" : "inactive"); + LOGSETUP(" - Tx Mode : %s\n", (m_tcr & REG_TCR_TRES) ? "reset" : "normal"); +} + +uint8_t mpcc_device::do_tcr() +{ + uint8_t data = m_tcr; + LOG("%s <- %02x\n", FUNCNAME, data); + return data; +} + +void mpcc_device::do_tivnr(uint8_t data) +{ + LOG("%s -> %02x\n", FUNCNAME, data); + m_tivnr = data; + LOGSETUP(" - Tx Int vector: %02x\n", m_tivnr); +} + +uint8_t mpcc_device::do_tivnr() +{ + uint8_t data = m_tivnr; + LOG("%s <- %02x\n", FUNCNAME, data); + return data; +} + +void mpcc_device::do_tier(uint8_t data) +{ + LOG("%s -> %02x\n", FUNCNAME, data); + m_tier = data; + LOGSETUP(" - Tx INT on FIFO slot available : %s\n", (m_tier & REG_TIER_TDRA) ? "enabled" : "disabled"); + LOGSETUP(" - Tx INT on Frame complete : %s\n", (m_tier & REG_TIER_TFC ) ? "enabled" : "disabled"); + LOGSETUP(" - Tx INT on Underrun : %s\n", (m_tier & REG_TIER_TUNRN) ? "enabled" : "disabled"); + LOGSETUP(" - Tx INT on Frame error : %s\n", (m_tier & REG_TIER_TFERR) ? "enabled" : "disabled"); +} + +uint8_t mpcc_device::do_tier() +{ + uint8_t data = m_tier; + LOG("%s <- %02x\n", FUNCNAME, data); + return data; +} + +void mpcc_device::do_sicr(uint8_t data) +{ + LOG("%s -> %02x\n", FUNCNAME, data); + m_sicr = data; + LOGSETUP(" - RTS level : %s\n", (m_sicr & REG_SICR_RTSLVL) ? "high" : "low"); + LOGSETUP(" - DTR level : %s\n", (m_sicr & REG_SICR_DTRLVL) ? "high" : "low"); + LOGSETUP(" - Echo Mode : %s\n", (m_sicr & REG_SICR_ECHO) ? "enabled" : "disabled"); + LOGSETUP(" - Test Mode : %s\n", (m_sicr & REG_SICR_TEST) ? "enabled" : "disabled"); +} + +uint8_t mpcc_device::do_sicr() +{ + uint8_t data = m_sicr; + LOG("%s <- %02x\n", FUNCNAME, data); + return data; +} + +void mpcc_device::do_sier(uint8_t data) +{ + LOG("%s -> %02x\n", FUNCNAME, data); + m_sier = data; + LOGSETUP(" - Serial interface INT on CTS: %s\n", (m_sier & REG_SIER_CTS) ? "enabled" : "disabled"); + LOGSETUP(" - Serial interface INT on DSR: %s\n", (m_sier & REG_SIER_DSR) ? "enabled" : "disabled"); + LOGSETUP(" - Serial interface INT on DCD: %s\n", (m_sier & REG_SIER_DCD) ? "enabled" : "disabled"); +} + +uint8_t mpcc_device::do_sier() +{ + uint8_t data = m_sier; + LOG("%s <- %02x\n", FUNCNAME, data); + return data; +} + +void mpcc_device::do_psr1(uint8_t data) +{ + LOG("%s -> %02x\n", FUNCNAME, data); + m_psr1 = data; + LOGSETUP(" - Zero Address option: %s\n", (m_psr1 & REG_PSR1_ADRZ) ? "enabled" : "disabled" ); + LOGSETUP(" - IPARS option : %s\n", (m_psr1 & REG_PSR1_IPARS) ? "enabled" : "disabled" ); + LOGSETUP(" - Control Field Width: %s\n", (m_psr1 & REG_PSR1_CTLEX) ? "16 bit" : "8 bit" ); + LOGSETUP(" - Address Extend : %s\n", (m_psr1 & REG_PSR1_ADDEX) ? "enabled" : "disabled" ); +} + +uint8_t mpcc_device::do_psr1() +{ + uint8_t data = m_psr1; + LOG("%s <- %02x\n", FUNCNAME, data); + return data; +} + +void mpcc_device::do_psr2(uint8_t data) +{ + LOG("%s -> %02x\n", FUNCNAME, data); + m_psr2 = data; + LOGSETUP(" - %s data bus\n", (m_psr2 & REG_PSR2_WDBYT) ? "16 bit (not implemented)" : "8 bit" ); + LOGSETUP(" - %s stop bits\n",(m_psr2 & REG_PSR2_STP_MSK) == REG_PSR2_STP_1 ? "1" : + ( (m_psr2 & REG_PSR2_STP_MSK) == REG_PSR2_STP_1_5 ? "1.5" : + ( (m_psr2 & REG_PSR2_STP_MSK) == REG_PSR2_STP_2 ? "2" : "Unknown"))); + LOGSETUP(" - %d bit characters\n", 5 + ((m_psr2 & REG_PSR2_CHLN_MSK) >> 3)); + LOGSETUP(" - Protocol %d %s\n", m_psr2 & REG_PSR2_PSEL_MSK, (m_psr2 & REG_PSR2_PSEL_MSK) != REG_PSR2_PSEL_ASCII ? "(not implemented)" : ""); +} + +uint8_t mpcc_device::do_psr2() +{ + uint8_t data = m_psr2; + LOG("%s <- %02x\n", FUNCNAME, data); + return data; +} + +/* + * Clocks and Baud Rates + */ +void mpcc_device::do_brdr1(uint8_t data) +{ + LOG("%s -> %02x\n", FUNCNAME, data); + m_brdr1 = data; + LOGSETUP(" - Baudrate Divider 1: %02x\n", m_brdr1); +} + +uint8_t mpcc_device::do_brdr1() +{ + uint8_t data = m_brdr1; + LOG("%s <- %02x\n", FUNCNAME, data); + return data; +} + +void mpcc_device::do_brdr2(uint8_t data) +{ + LOG("%s -> %02x\n", FUNCNAME, data); + m_brdr2 = data; + LOGSETUP(" - Baudrate Divider 2: %02x\n", m_brdr2); +} + +uint8_t mpcc_device::do_brdr2() +{ + uint8_t data = m_brdr2; + LOG("%s <- %02x\n", FUNCNAME, data); + return data; +} + +void mpcc_device::do_ccr(uint8_t data) +{ + LOG("%s -> %02x\n", FUNCNAME, data); + m_ccr = data; + LOGSETUP(" - Prescaler: x%d\n", (m_ccr & REG_CCR_PSCDIV) ? 3 : 2); + LOGSETUP(" - TxC used as: %s\n", (m_ccr & REG_CCR_TCLO) ? "output" : "input"); + LOGSETUP(" - RxC taken from: %s source, (ASYNC mode only)\n", (m_ccr & REG_CCR_TCLO) ? "internal" : "external"); + LOGSETUP(" - External RxC divisor: x%d\n",(m_ccr & REG_CCR_CLKDIV_MSK) == REG_CCR_CLKDIV_X1 ? 1 : + ( (m_ccr & REG_CCR_CLKDIV_MSK) == REG_CCR_CLKDIV_X16 ? 16 : + ( (m_ccr & REG_CCR_CLKDIV_MSK) == REG_CCR_CLKDIV_X32 ? 32 : 64))); +} + +uint8_t mpcc_device::do_ccr() +{ + uint8_t data = m_ccr; + LOG("%s <- %02x\n", FUNCNAME, data); + return data; +} + +void mpcc_device::do_ecr(uint8_t data) +{ + LOG("%s -> %02x\n", FUNCNAME, data); + m_ecr = data; + LOGSETUP(" - Parity : %s\n", (m_ecr & REG_ECR_PAREN) ? "enabled" : "disabled"); + LOGSETUP(" - Parity : %s\n", (m_ecr & REG_ECR_ODDPAR) ? "odd" : "even"); + LOGSETUP(" - CRC : %s\n", (m_ecr & REG_ECR_CFCRC) ? "enabled" : "disabled"); + LOGSETUP(" - CRC Polynominal: %s\n", (m_ecr & REG_ECR_CRCSEL_MSK) == REG_ECR_CRCSEL_V41 ? "CCITT V.41 (BOP)" : + ( (m_ecr & REG_ECR_CRCSEL_MSK) == REG_ECR_CRCSEL_C16 ? "CRC-16 (BSC)" : + ( (m_ecr & REG_ECR_CRCSEL_MSK) == REG_ECR_CRCSEL_VRC ? "VRC/LRC (BSC, ASCII, non-transp)" : + "Not used"))); +} + +uint8_t mpcc_device::do_ecr() +{ + uint8_t data = m_ecr; + LOG("%s <- %02x\n", FUNCNAME, data); + return data; +} diff --git a/src/devices/machine/68561mpcc.h b/src/devices/machine/68561mpcc.h index da9ef87fca7..5c8a8a0d483 100644 --- a/src/devices/machine/68561mpcc.h +++ b/src/devices/machine/68561mpcc.h @@ -6,30 +6,32 @@ **************************************************************************** _____ _____ - 1|* \_/ |48 - 2| |47 - 3| |46 - 4| |45 _____ _____ - 5| |44 1|* \_/ |40 - 6| |43 2| |39 - 7| |42 3| |38 - 8| |41 4| |37 - 9| |40 5| |36 - 10| |39 6| |35 - 11| |38 7| |34 - 12| |37 8| |33 - 13| SCN26562 |36 9| |32 - 14| SCN26C562 |35 10| |31 - 15| |34 11| Z8530 |30 - 16| |33 12| Z85C30 |29 - 17| |32 13| Z85230 |28 - 18| |31 14| |27 - 19| |30 15| |26 - 20| |29 16| |25 - 21| |28 17| |24 - 22| |27 18| |23 - 23| |26 19| |22 - 24|_____________|25 20|_____________|21 + UDS* 1|* \_/ |48 IACK* + DTACK* 2| |47 LDS* + RxD 3| |46 DTC* + D10 4| |45 D9 _____ _____ + DTR* 5| |44 CS* A0 1|* \_/ |40 IACK* + DSR* 6| |43 DACK* DTACK* 2| |39 DS* + DCD* 7| |42 GND RxD* 3| |38 DTC* + D11 8| |41 D0 DTR* 4| |37 CS* + RDSR* 9| |40 D8 DSR* 5| |36 DACK* + A1 10| |39 D1 DCD* 6| |35 GND + GND 11| |38 D2 RDSR* 7| |34 D0 + A4 12| |37 D3 A1 8| |33 D1 + A2 13| R68561 |36 D4 GND 9| R68560 |32 D2 + A3 14| R68561A |35 D5 A4 10| R68560A |31 D3 + RxC 15| |34 D6 A2 11| |30 D4 + D12 16| |33 D15 A3 12| |29 D5 + TxC 17| |32 D7 RxC 13| |28 D6 + BCLK 18| |31 RESET* TxC 14| |27 D7 + EXTAL 19| |30 CTS* BCLK 15| |26 RESET* + XTAL 20| |29 Vcc EXTAL 16| |25 CTS* + D13 21| |28 D14 XTAL 17| |24 Vcc + R/W* 22| |27 DONE* R/W* 18| |23 DONE* + IRQ* 23| |26 TxD IRQ* 19| |22 TxD + RTS* 24|_____________|25 TDSR* RTS* 20|_____________|21 TDSR* + 16 bit data bus 8 bit data bus + Also in 68 pin PLCE Also in 44 pin PLCE ***************************************************************************/ @@ -205,8 +207,10 @@ protected: /* * Register handling */ - // RSR register + // RSR - Rx Status Register uint8_t m_rsr; + uint8_t do_rsr(); + void do_rsr(uint8_t data); enum { REG_RSR_RDA = 0x80, // Rx Data available @@ -219,8 +223,10 @@ protected: REG_RSR_RIDLE = 0x01, // Rx idle detcted (15+ high consecutive bits accounted for) }; - // RCR register + // RCR - Rx Control Register uint8_t m_rcr; + uint8_t do_rcr(); + void do_rcr(uint8_t data); enum { REG_RCR_RDSREN = 0x40, // Rx Data Service Request Enable (DMA) @@ -237,8 +243,10 @@ protected: uint8_t m_rivnr; - // RIER register + // RIER - Rx Interrupt Enable Register uint8_t m_rier; + uint8_t do_rier(); + void do_rier(uint8_t data); enum { REG_RIER_RDA = 0x80, // Rx interrupt on Receiver Data Available REG_RIER_EOF = 0x40, // Rx interrupt on End of frame @@ -248,8 +256,10 @@ protected: REG_RIER_RAB = 0x02, // Rx interrupt on Abort/Break }; - // TSR register + // TSR - Tx Status Register uint8_t m_tsr; + uint8_t do_tsr(); + void do_tsr(uint8_t data); enum { REG_TSR_TDRA = 0x80, @@ -258,30 +268,37 @@ protected: REG_TSR_TFERR = 0x02, }; - // TCR register + // TCR - Tx Control Register uint8_t m_tcr; + uint8_t do_tcr(); + void do_tcr(uint8_t data); enum { - REG_TCR_TEN = 0x80, // Tx enabled - REG_TCR_TDSREN = 0x40, + REG_TCR_TEN = 0x80, // Tx enable + REG_TCR_TDSREN = 0x40, // DMA enable REG_TCR_TICS = 0x20, // Tx Idle Char Select, 'A' variant differs - REG_TCR_THW = 0x10, - REG_TCR_TLAST = 0x08, - REG_TCR_TSYN = 0x04, - REG_TCR_TABT = 0x02, - REG_TCR_TRES = 0x01, + REG_TCR_THW = 0x10, // Indicates that last 16 bit word has only 8 bits, in 16 bits mode only + REG_TCR_TLAST = 0x08, // Indicates the last byte to be written in to TDR (BOP, BCS or COP) + REG_TCR_TSYN = 0x04, // SYN enable (BCS or COP) + REG_TCR_TABT = 0x02, // Abort command (BOP) + REG_TCR_TRES = 0x01, // Tx Reset command }; - // TDR register + // TDR - Tx Data Register (write only) uint8_t m_tdr; - void do_tdr_w(uint8_t data); + void do_tdr(uint8_t data); // TODO: investigate if 4 x 16 bit wide FIFO is needed for 16 bit mode util::fifo m_tx_data_fifo; + // TIVNR - Tx Interrupt Vector Number Register uint8_t m_tivnr; + uint8_t do_tivnr(); + void do_tivnr(uint8_t data); - // TIER register + // TIER - Tx Interrupt Enable Register uint8_t m_tier; + uint8_t do_tier(); + void do_tier(uint8_t data); enum { REG_TIER_TDRA = 0x80, // TX Character available interrupt @@ -291,17 +308,117 @@ protected: }; uint8_t m_sisr; + + // SICR - Serial Interface Control Register uint8_t m_sicr; + uint8_t do_sicr(); + void do_sicr(uint8_t data); + enum + { + REG_SICR_RTSLVL = 0x80, // RTS level + REG_SICR_DTRLVL = 0x40, // DTR level + REG_SICR_ECHO = 0x04, // Echo Mode + REG_SICR_TEST = 0x02, // Test Mode + }; + uint8_t m_sivnr; + + // SIER - Serial interface Interrupt Enable uint8_t m_sier; + uint8_t do_sier(); + void do_sier(uint8_t data); + enum + { + REG_SIER_CTS = 0x80, + REG_SIER_DSR = 0x40, + REG_SIER_DCD = 0x20, + }; + + // PSR1 Protocol Selection Register 1 uint8_t m_psr1; + uint8_t do_psr1(); + void do_psr1(uint8_t data); + enum + { + REG_PSR1_ADRZ = 0x08, // Zero adress option (BOP) (A models only) + REG_PSR1_IPARS = 0x04, // IPARS option (COP) + REG_PSR1_CTLEX = 0x02, // Control field width 8/16 bit (BOP) (A models only) + REG_PSR1_ADDEX = 0x01, // Address extend option (BOP) (A models only) + }; + + // PSR2 Protocol Selection Register 2 uint8_t m_psr2; + uint8_t do_psr2(); + void do_psr2(uint8_t data); + enum + { + REG_PSR2_WDBYT = 0x80, // 8/16 bit data bus selector + REG_PSR2_STP_MSK = 0x60, // Stop bits selection field + REG_PSR2_STP_1 = 0x00, // 1 Stop bits + REG_PSR2_STP_1_5 = 0x20, // 1.5 Stop bits + REG_PSR2_STP_2 = 0x40, // 2 Stop bits + REG_PSR2_CHLN_MSK = 0x18, // char len selection field + REG_PSR2_CHLN_5 = 0x00, // 5 bit char len + REG_PSR2_CHLN_6 = 0x08, // 6 bit char len + REG_PSR2_CHLN_7 = 0x10, // 7 bit char len + REG_PSR2_CHLN_8 = 0x18, // 8 bit char len + REG_PSR2_PSEL_MSK = 0x07, // Protocol selection field + REG_PSR2_PSEL_BOPP = 0x00, // Protocol selection BOP Primary + REG_PSR2_PSEL_BOPS = 0x01, // Protocol selection BOP Secondary + REG_PSR2_PSEL_RSV = 0x02, // Protocol selection Reserved + REG_PSR2_PSEL_COP = 0x03, // Protocol selection COP + REG_PSR2_PSEL_BCSE = 0x04, // Protocol selection BCS EBCDIC + REG_PSR2_PSEL_BCSA = 0x05, // Protocol selection BCS ASCII + REG_PSR2_PSEL_ASCII = 0x06, // Protocol selection ASYNC + REG_PSR2_PSEL_ISOC = 0x07, // Protocol selection ISOC + }; + uint8_t m_ar1; uint8_t m_ar2; + + + // BRDR1 - Baud Rate Divisor Register 1 (Lo) uint8_t m_brdr1; + uint8_t do_brdr1(); + void do_brdr1(uint8_t data); + + // BRDR2 - Baud Rate Divisor Register 2 (Hi) uint8_t m_brdr2; + uint8_t do_brdr2(); + void do_brdr2(uint8_t data); + + // CCR - Clock Control Register uint8_t m_ccr; + uint8_t do_ccr(); + void do_ccr(uint8_t data); + enum + { + REG_CCR_PSCDIV = 0x10, // Internal prescaler Divider x2 or x3 + REG_CCR_TCLO = 0x08, // TxC input/output selection + REG_CCR_RCLKIN = 0x04, // RxC from internal/external source selection + REG_CCR_CLKDIV_MSK = 0x03, // External RxC prescaler Divider + REG_CCR_CLKDIV_X1 = 0x00, // x1 - ISOC only + REG_CCR_CLKDIV_X16 = 0x01, // x16 - ASYNC only + REG_CCR_CLKDIV_X32 = 0x02, // x32 - ASYNC only + REG_CCR_CLKDIV_X64 = 0x03, // x64 - ASYNC only + }; + + // ECR - Error Control Regsiter uint8_t m_ecr; + uint8_t do_ecr(); + void do_ecr(uint8_t data); + enum + { + REG_ECR_PAREN = 0x80, // Parity Enable + REG_ECR_ODDPAR = 0x40, // Odd/Even Parity + REG_ECR_CFCRC = 0x08, // CRC Enable + REG_ECR_CRCPRE = 0x04, // CRC Preset 0 (BSC) or 1 (BOP) + REG_ECR_CRCSEL_MSK = 0x03, // CRC Polynominal Selection Mask + REG_ECR_CRCSEL_V41 = 0x00, // CCITT V.41 (BOP) CRC Polynomial + REG_ECR_CRCSEL_C16 = 0x01, // CRC-16 (BSC) CRC Polynomial + REG_ECR_CRCSEL_VRC = 0x02, // VRC/LRC (BSC, ASCII, non-transp) CRC Polynomial + }; + }; // device type definition