From 08688e308353b7041cb6208b2782b19e605a57ce Mon Sep 17 00:00:00 2001 From: Aaron Giles Date: Thu, 22 Apr 2021 08:49:31 -0700 Subject: [PATCH] mips3: Ensure there is at least 1 cycle to be counted after reading Count. Without this, some timing loops won't exit to the scheduler until they complete. --- src/devices/cpu/mips/mips3drc.cpp | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/devices/cpu/mips/mips3drc.cpp b/src/devices/cpu/mips/mips3drc.cpp index 9b3396a09f9..24813885088 100644 --- a/src/devices/cpu/mips/mips3drc.cpp +++ b/src/devices/cpu/mips/mips3drc.cpp @@ -2460,6 +2460,11 @@ bool mips3_device::generate_set_cop0_reg(drcuml_block &block, compiler_state &co return true; case COP0_Count: + // don't count the cycle for this instruction yet; we need a non-zero cycle + // count in case we are in a delay slot, otherwise the test for negative cycles + // won't be generated (due to compiler.cycles == 0); see the loop during early + // boot of gauntdl, @BFC01A24 + compiler.cycles--; generate_update_cycles(block, compiler, desc->pc, !in_delay_slot); // UML_MOV(block, CPR032(COP0_Count), I0); // mov [Count],i0 UML_CALLC(block, cfunc_get_cycles, this); // callc cfunc_get_cycles,mips3 @@ -2468,6 +2473,7 @@ bool mips3_device::generate_set_cop0_reg(drcuml_block &block, compiler_state &co UML_DSUB(block, mem(&m_core->count_zero_time), mem(&m_core->numcycles), I0); // dsub [count_zero_time],[m_numcycles],i0 UML_CALLC(block, cfunc_mips3com_update_cycle_counting, this); // callc mips3com_update_cycle_counting,mips.core + compiler.cycles++; return true; case COP0_Compare: @@ -2513,12 +2519,18 @@ bool mips3_device::generate_get_cop0_reg(drcuml_block &block, compiler_state &co switch (reg) { case COP0_Count: + // don't count the cycle for this instruction yet; we need a non-zero cycle + // count in case we are in a delay slot, otherwise the test for negative cycles + // won't be generated (due to compiler.cycles == 0); see the loop during early + // boot of gauntdl, @BFC01A24 + compiler.cycles--; generate_update_cycles(block, compiler, desc->pc, false); // UML_CALLC(block, cfunc_get_cycles, this); // callc cfunc_get_cycles,mips3 UML_DSUB(block, I0, mem(&m_core->numcycles), mem(&m_core->count_zero_time)); // dsub i0,[numcycles],[count_zero_time] UML_DSHR(block, I0, I0, 1); // dshr i0,i0,1 UML_DSEXT(block, I0, I0, SIZE_DWORD); // dsext i0,i0,dword + compiler.cycles++; return true; case COP0_Random: