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https://github.com/holub/mame
synced 2025-04-23 17:00:53 +03:00
sharc: Rewrote DMA handling to use timers.
This commit is contained in:
Ville Linde
parent
b60c2477b5
commit
087fd08912
@ -73,6 +73,21 @@ typedef struct
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UINT32 loop_type;
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} LADDR;
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typedef struct
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{
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UINT32 src;
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UINT32 dst;
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UINT32 chain_ptr;
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INT32 src_modifier;
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INT32 dst_modifier;
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INT32 src_count;
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INT32 dst_count;
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INT32 pmode;
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INT32 chained_direction;
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emu_timer *timer;
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bool active;
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} DMA_OP;
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typedef struct _SHARC_REGS SHARC_REGS;
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struct _SHARC_REGS
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{
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@ -147,17 +162,8 @@ struct _SHARC_REGS
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SHARC_BOOT_MODE boot_mode;
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UINT32 dmaop_src;
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UINT32 dmaop_dst;
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UINT32 dmaop_chain_ptr;
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INT32 dmaop_src_modifier;
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INT32 dmaop_dst_modifier;
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INT32 dmaop_src_count;
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INT32 dmaop_dst_count;
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INT32 dmaop_pmode;
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INT32 dmaop_cycles;
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INT32 dmaop_channel;
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INT32 dmaop_chained_direction;
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DMA_OP dma_op[12];
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UINT32 dma_status;
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INT32 interrupt_active;
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@ -260,12 +266,7 @@ static UINT32 sharc_iop_r(SHARC_REGS *cpustate, UINT32 address)
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case 0x37: // DMA status
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{
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UINT32 r = 0;
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if (cpustate->dmaop_cycles > 0)
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{
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r |= 1 << cpustate->dmaop_channel;
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}
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return r;
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return cpustate->dma_status;
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}
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default: fatalerror("sharc_iop_r: Unimplemented IOP reg %02X at %08X\n", address, cpustate->pc);
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}
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@ -292,7 +293,6 @@ static void sharc_iop_w(SHARC_REGS *cpustate, UINT32 address, UINT32 data)
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case 0x1c:
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{
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cpustate->dma[6].control = data;
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//add_iop_write_latency_effect(cpustate, 0x1c, data, 1);
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sharc_iop_delayed_w(cpustate, 0x1c, data, 1);
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break;
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}
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@ -312,7 +312,6 @@ static void sharc_iop_w(SHARC_REGS *cpustate, UINT32 address, UINT32 data)
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case 0x1d:
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{
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cpustate->dma[7].control = data;
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//add_iop_write_latency_effect(cpustate, 0x1d, data, 30);
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sharc_iop_delayed_w(cpustate, 0x1d, data, 30);
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break;
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}
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@ -438,6 +437,12 @@ static CPU_INIT( sharc )
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cpustate->delayed_iop_timer = device->machine().scheduler().timer_alloc(FUNC(sharc_iop_delayed_write_callback), cpustate);
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for (int i=0; i < 12; i++)
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{
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cpustate->dma_op[i].active = false;
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cpustate->dma_op[i].timer = device->machine().scheduler().timer_alloc(FUNC(sharc_dma_callback), cpustate);
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}
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device->save_item(NAME(cpustate->pc));
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device->save_pointer(NAME(&cpustate->r[0].r), ARRAY_LENGTH(cpustate->r));
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device->save_pointer(NAME(&cpustate->reg_alt[0].r), ARRAY_LENGTH(cpustate->reg_alt));
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@ -523,17 +528,21 @@ static CPU_INIT( sharc )
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device->save_item(NAME(cpustate->irq_active));
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device->save_item(NAME(cpustate->active_irq_num));
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device->save_item(NAME(cpustate->dmaop_src));
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device->save_item(NAME(cpustate->dmaop_dst));
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device->save_item(NAME(cpustate->dmaop_chain_ptr));
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device->save_item(NAME(cpustate->dmaop_src_modifier));
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device->save_item(NAME(cpustate->dmaop_dst_modifier));
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device->save_item(NAME(cpustate->dmaop_src_count));
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device->save_item(NAME(cpustate->dmaop_dst_count));
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device->save_item(NAME(cpustate->dmaop_pmode));
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device->save_item(NAME(cpustate->dmaop_cycles));
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device->save_item(NAME(cpustate->dmaop_channel));
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device->save_item(NAME(cpustate->dmaop_chained_direction));
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for (saveindex = 0; saveindex < ARRAY_LENGTH(cpustate->dma_op); saveindex++)
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{
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device->save_item(NAME(cpustate->dma_op[saveindex].src), saveindex);
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device->save_item(NAME(cpustate->dma_op[saveindex].dst), saveindex);
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device->save_item(NAME(cpustate->dma_op[saveindex].chain_ptr), saveindex);
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device->save_item(NAME(cpustate->dma_op[saveindex].src_modifier), saveindex);
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device->save_item(NAME(cpustate->dma_op[saveindex].dst_modifier), saveindex);
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device->save_item(NAME(cpustate->dma_op[saveindex].src_count), saveindex);
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device->save_item(NAME(cpustate->dma_op[saveindex].dst_count), saveindex);
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device->save_item(NAME(cpustate->dma_op[saveindex].pmode), saveindex);
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device->save_item(NAME(cpustate->dma_op[saveindex].chained_direction), saveindex);
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device->save_item(NAME(cpustate->dma_op[saveindex].active), saveindex);
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}
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device->save_item(NAME(cpustate->dma_status));
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device->save_item(NAME(cpustate->interrupt_active));
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@ -571,10 +580,9 @@ static CPU_RESET( sharc )
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cpustate->dma[6].control = 0x2a1;
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sharc_dma_exec(cpustate, 6);
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dma_op(cpustate, cpustate->dmaop_src, cpustate->dmaop_dst, cpustate->dmaop_src_modifier, cpustate->dmaop_dst_modifier,
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cpustate->dmaop_src_count, cpustate->dmaop_dst_count, cpustate->dmaop_pmode);
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cpustate->dmaop_cycles = 0;
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dma_op(cpustate, 6);
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cpustate->dma_op[6].timer->adjust(attotime::never, 0);
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break;
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}
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@ -679,21 +687,6 @@ static CPU_EXECUTE( sharc )
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if (cpustate->idle && cpustate->irq_active == 0)
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{
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// handle pending DMA transfers
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if (cpustate->dmaop_cycles > 0)
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{
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cpustate->dmaop_cycles -= cpustate->icount;
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if (cpustate->dmaop_cycles <= 0)
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{
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cpustate->dmaop_cycles = 0;
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dma_op(cpustate, cpustate->dmaop_src, cpustate->dmaop_dst, cpustate->dmaop_src_modifier, cpustate->dmaop_dst_modifier, cpustate->dmaop_src_count, cpustate->dmaop_dst_count, cpustate->dmaop_pmode);
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if (cpustate->dmaop_chain_ptr != 0)
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{
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schedule_chained_dma_op(cpustate, cpustate->dmaop_channel, cpustate->dmaop_chain_ptr, cpustate->dmaop_chained_direction);
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}
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}
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}
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cpustate->icount = 0;
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debugger_instruction_hook(device, cpustate->daddr);
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}
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@ -790,28 +783,6 @@ static CPU_EXECUTE( sharc )
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}
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}
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// DMA transfer
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if (cpustate->dmaop_cycles > 0)
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{
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--cpustate->dmaop_cycles;
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if (cpustate->dmaop_cycles <= 0)
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{
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cpustate->irptl |= (1 << (cpustate->dmaop_channel+10));
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/* DMA interrupt */
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if (cpustate->imask & (1 << (cpustate->dmaop_channel+10)))
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{
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cpustate->irq_active |= 1 << (cpustate->dmaop_channel+10);
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}
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dma_op(cpustate, cpustate->dmaop_src, cpustate->dmaop_dst, cpustate->dmaop_src_modifier, cpustate->dmaop_dst_modifier, cpustate->dmaop_src_count, cpustate->dmaop_dst_count, cpustate->dmaop_pmode);
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if (cpustate->dmaop_chain_ptr != 0)
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{
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schedule_chained_dma_op(cpustate, cpustate->dmaop_channel, cpustate->dmaop_chain_ptr, cpustate->dmaop_chained_direction);
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}
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}
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}
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--cpustate->icount;
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};
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}
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@ -19,59 +19,79 @@ static void schedule_chained_dma_op(SHARC_REGS *cpustate, int channel, UINT32 dm
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UINT32 ext_modifier = dm_read32(cpustate, op_ptr - 6);
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UINT32 ext_count = dm_read32(cpustate, op_ptr - 7);
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if (cpustate->dmaop_cycles > 0)
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if (cpustate->dma_op[channel].active)
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{
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fatalerror("schedule_chained_dma_op: DMA operation already scheduled at %08X!\n", cpustate->pc);
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}
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if (chained_direction) // Transmit to external
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{
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cpustate->dmaop_dst = ext_index;
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cpustate->dmaop_dst_modifier = ext_modifier;
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cpustate->dmaop_dst_count = ext_count;
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cpustate->dmaop_src = int_index;
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cpustate->dmaop_src_modifier = int_modifier;
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cpustate->dmaop_src_count = int_count;
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cpustate->dma_op[channel].dst = ext_index;
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cpustate->dma_op[channel].dst_modifier = ext_modifier;
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cpustate->dma_op[channel].dst_count = ext_count;
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cpustate->dma_op[channel].src = int_index;
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cpustate->dma_op[channel].src_modifier = int_modifier;
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cpustate->dma_op[channel].src_count = int_count;
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}
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else // Receive from external
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else // Receive from external
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{
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cpustate->dmaop_src = ext_index;
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cpustate->dmaop_src_modifier = ext_modifier;
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cpustate->dmaop_src_count = ext_count;
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cpustate->dmaop_dst = int_index;
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cpustate->dmaop_dst_modifier = int_modifier;
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cpustate->dmaop_dst_count = int_count;
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cpustate->dma_op[channel].src = ext_index;
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cpustate->dma_op[channel].src_modifier = ext_modifier;
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cpustate->dma_op[channel].src_count = ext_count;
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cpustate->dma_op[channel].dst = int_index;
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cpustate->dma_op[channel].dst_modifier = int_modifier;
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cpustate->dma_op[channel].dst_count = int_count;
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}
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cpustate->dmaop_pmode = 0;
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cpustate->dmaop_channel = channel;
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cpustate->dmaop_cycles = cpustate->dmaop_src_count / 4;
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cpustate->dmaop_chain_ptr = chain_ptr;
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cpustate->dmaop_chained_direction = chained_direction;
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cpustate->dma_op[channel].pmode = 0;
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cpustate->dma_op[channel].chain_ptr = chain_ptr;
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cpustate->dma_op[channel].chained_direction = chained_direction;
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cpustate->dma_op[channel].active = true;
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int cycles = cpustate->dma_op[channel].src_count / 4;
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cpustate->dma_op[channel].timer->adjust(cpustate->device->cycles_to_attotime(cycles), channel);
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// enable busy flag
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cpustate->dma_status |= (1 << channel);
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}
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static void schedule_dma_op(SHARC_REGS *cpustate, int channel, UINT32 src, UINT32 dst, int src_modifier, int dst_modifier, int src_count, int dst_count, int pmode)
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{
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if (cpustate->dmaop_cycles > 0)
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if (cpustate->dma_op[channel].active)
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{
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fatalerror("schedule_dma_op: DMA operation already scheduled at %08X!\n", cpustate->pc);
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}
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cpustate->dmaop_channel = channel;
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cpustate->dmaop_src = src;
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cpustate->dmaop_dst = dst;
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cpustate->dmaop_src_modifier = src_modifier;
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cpustate->dmaop_dst_modifier = dst_modifier;
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cpustate->dmaop_src_count = src_count;
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cpustate->dmaop_dst_count = dst_count;
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cpustate->dmaop_pmode = pmode;
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cpustate->dmaop_chain_ptr = 0;
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cpustate->dmaop_cycles = src_count / 4;
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cpustate->dma_op[channel].src = src;
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cpustate->dma_op[channel].dst = dst;
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cpustate->dma_op[channel].src_modifier = src_modifier;
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cpustate->dma_op[channel].dst_modifier = dst_modifier;
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cpustate->dma_op[channel].src_count = src_count;
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cpustate->dma_op[channel].dst_count = dst_count;
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cpustate->dma_op[channel].pmode = pmode;
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cpustate->dma_op[channel].chain_ptr = 0;
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cpustate->dma_op[channel].active = true;
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int cycles = src_count / 4;
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cpustate->dma_op[channel].timer->adjust(cpustate->device->cycles_to_attotime(cycles), channel);
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// enable busy flag
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cpustate->dma_status |= (1 << channel);
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}
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static void dma_op(SHARC_REGS *cpustate, UINT32 src, UINT32 dst, int src_modifier, int dst_modifier, int src_count, int dst_count, int pmode)
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static void dma_op(SHARC_REGS *cpustate, int channel)
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{
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int i;
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UINT32 src = cpustate->dma_op[channel].src;
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UINT32 dst = cpustate->dma_op[channel].dst;
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int src_modifier = cpustate->dma_op[channel].src_modifier;
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int dst_modifier = cpustate->dma_op[channel].dst_modifier;
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int src_count = cpustate->dma_op[channel].src_count;
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//int dst_count = cpustate->dma_op[channel].dst_count;
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int pmode = cpustate->dma_op[channel].pmode;
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//printf("dma_op: %08X, %08X, %08X, %08X, %08X, %08X, %d\n", src, dst, src_modifier, dst_modifier, src_count, dst_count, pmode);
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switch (pmode)
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@ -124,16 +144,21 @@ static void dma_op(SHARC_REGS *cpustate, UINT32 src, UINT32 dst, int src_modifie
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}
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}
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if (cpustate->dmaop_channel == 6)
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if (channel == 6)
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{
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cpustate->irptl |= (1 << (cpustate->dmaop_channel+10));
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cpustate->irptl |= (1 << (channel+10));
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/* DMA interrupt */
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if (cpustate->imask & (1 << (cpustate->dmaop_channel+10)))
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if (cpustate->imask & (1 << (channel+10)))
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{
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cpustate->irq_active |= 1 << (cpustate->dmaop_channel+10);
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cpustate->irq_active |= 1 << (channel+10);
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}
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}
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// clear busy flag
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cpustate->dma_status &= ~(1 << channel);
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cpustate->dma_op[channel].active = false;
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}
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static void sharc_dma_exec(SHARC_REGS *cpustate, int channel)
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@ -202,3 +227,25 @@ static void sharc_dma_exec(SHARC_REGS *cpustate, int channel)
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schedule_dma_op(cpustate, channel, src, dst, src_modifier, dst_modifier, src_count, dst_count, pmode);
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}
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}
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static TIMER_CALLBACK(sharc_dma_callback)
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{
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SHARC_REGS *cpustate = (SHARC_REGS *)ptr;
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int channel = param;
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cpustate->dma_op[channel].timer->adjust(attotime::never, 0);
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cpustate->irptl |= (1 << (channel+10));
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// DMA interrupt
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if (cpustate->imask & (1 << (channel+10)))
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{
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cpustate->irq_active |= 1 << (channel+10);
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}
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dma_op(cpustate, channel);
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if (cpustate->dma_op[channel].chain_ptr != 0)
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{
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schedule_chained_dma_op(cpustate, channel, cpustate->dma_op[channel].chain_ptr, cpustate->dma_op[channel].chained_direction);
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}
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}
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