From 0946c173cb1717bb5ec12b0ee7aa58e070f19e1e Mon Sep 17 00:00:00 2001 From: Andrew Gardner Date: Sat, 7 Aug 2010 18:42:59 +0000 Subject: [PATCH] dsp56k : Hooked up new execution engine. [Andrew Gardner] --- .gitattributes | 2 + src/emu/cpu/cpu.mak | 27 +- src/emu/cpu/dsp56k/dsp56def.h | 385 +------------- src/emu/cpu/dsp56k/dsp56k.c | 80 +-- src/emu/cpu/dsp56k/dsp56k.h | 9 + src/emu/cpu/dsp56k/dsp56mem.c | 977 +++++++++++++++++----------------- src/emu/cpu/dsp56k/dsp56mem.h | 243 +++++++++ src/emu/cpu/dsp56k/dsp56ops.c | 3 +- src/emu/cpu/dsp56k/dsp56pcu.c | 121 +++-- src/emu/cpu/dsp56k/dsp56pcu.h | 149 ++++++ src/emu/cpu/dsp56k/inst.c | 4 +- src/emu/cpu/dsp56k/inst.h | 298 ++++++----- src/emu/cpu/dsp56k/opcode.c | 14 +- src/emu/cpu/dsp56k/opcode.h | 5 +- src/emu/cpu/dsp56k/pmove.h | 6 +- 15 files changed, 1221 insertions(+), 1102 deletions(-) create mode 100644 src/emu/cpu/dsp56k/dsp56mem.h create mode 100644 src/emu/cpu/dsp56k/dsp56pcu.h diff --git a/.gitattributes b/.gitattributes index a3370c345ad..1f8d4f93eab 100644 --- a/.gitattributes +++ b/.gitattributes @@ -92,8 +92,10 @@ src/emu/cpu/dsp56k/dsp56dsm.c svneol=native#text/plain src/emu/cpu/dsp56k/dsp56k.c svneol=native#text/plain src/emu/cpu/dsp56k/dsp56k.h svneol=native#text/plain src/emu/cpu/dsp56k/dsp56mem.c svneol=native#text/plain +src/emu/cpu/dsp56k/dsp56mem.h svneol=native#text/plain src/emu/cpu/dsp56k/dsp56ops.c svneol=native#text/plain src/emu/cpu/dsp56k/dsp56pcu.c svneol=native#text/plain +src/emu/cpu/dsp56k/dsp56pcu.h svneol=native#text/plain src/emu/cpu/dsp56k/inst.c svneol=native#text/plain src/emu/cpu/dsp56k/inst.h svneol=native#text/plain src/emu/cpu/dsp56k/opcode.c svneol=native#text/plain diff --git a/src/emu/cpu/cpu.mak b/src/emu/cpu/cpu.mak index 28b92f1d338..f45727ca916 100644 --- a/src/emu/cpu/cpu.mak +++ b/src/emu/cpu/cpu.mak @@ -1053,6 +1053,8 @@ $(CPUOBJ)/m68000/m68kcpu.o: $(CPUOBJ)/m68000/m68kops.c \ ifneq ($(filter DSP56156,$(CPUS)),) OBJDIRS += $(CPUOBJ)/dsp56k CPUOBJS += $(CPUOBJ)/dsp56k/dsp56k.o +CPUOBJS += $(CPUOBJ)/dsp56k/dsp56mem.o +CPUOBJS += $(CPUOBJ)/dsp56k/dsp56pcu.o DASMOBJS += $(CPUOBJ)/dsp56k/dsp56dsm.o DASMOBJS += $(CPUOBJ)/dsp56k/opcode.o DASMOBJS += $(CPUOBJ)/dsp56k/inst.o @@ -1060,16 +1062,27 @@ DASMOBJS += $(CPUOBJ)/dsp56k/pmove.o DASMOBJS += $(CPUOBJ)/dsp56k/tables.o endif +$(CPUOBJ)/dsp56k/dsp56mem.o: $(CPUSRC)/dsp56k/dsp56mem.c \ + $(CPUSRC)/dsp56k/dsp56mem.h + +$(CPUOBJ)/dsp56k/dsp56pcu.o: $(CPUSRC)/dsp56k/dsp56pcu.c \ + $(CPUSRC)/dsp56k/dsp56pcu.h + $(CPUOBJ)/dsp56k/dsp56k.o: $(CPUSRC)/dsp56k/dsp56k.c \ - $(CPUSRC)/dsp56k/opcode.c \ - $(CPUSRC)/dsp56k/inst.c \ - $(CPUSRC)/dsp56k/pmove.c \ - $(CPUSRC)/dsp56k/tables.c \ - $(CPUSRC)/dsp56k/dsp56ops.c \ - $(CPUSRC)/dsp56k/dsp56mem.c \ - $(CPUSRC)/dsp56k/dsp56pcu.c \ $(CPUSRC)/dsp56k/dsp56k.h +$(CPUOBJ)/dsp56k/opcode.o: $(CPUSRC)/dsp56k/opcode.c \ + $(CPUSRC)/dsp56k/opcode.h + +$(CPUOBJ)/dsp56k/inst.o: $(CPUSRC)/dsp56k/inst.c \ + $(CPUSRC)/dsp56k/inst.h + +$(CPUOBJ)/dsp56k/pmove.o: $(CPUSRC)/dsp56k/pmove.c \ + $(CPUSRC)/dsp56k/pmove.h + +$(CPUOBJ)/dsp56k/tables.o: $(CPUSRC)/dsp56k/tables.c \ + $(CPUSRC)/dsp56k/tables.h + $(CPUOBJ)/dsp56k/dsp56dsm.o: $(CPUSRC)/dsp56k/opcode.c \ $(CPUSRC)/dsp56k/opcode.h \ $(CPUSRC)/dsp56k/inst.c \ diff --git a/src/emu/cpu/dsp56k/dsp56def.h b/src/emu/cpu/dsp56k/dsp56def.h index 7bc38d31bc9..416653e7cd9 100644 --- a/src/emu/cpu/dsp56k/dsp56def.h +++ b/src/emu/cpu/dsp56k/dsp56def.h @@ -2,6 +2,14 @@ // All the macros that are fit to print. // /////////////////////////////////////////// +#ifndef __DSP56_DEF_H__ +#define __DSP56_DEF_H__ + +#include "dsp56k.h" + +namespace DSP56K +{ + /*************************************************************************** ALU ***************************************************************************/ @@ -42,379 +50,6 @@ #define TEMP cpustate->AGU.temp +} // namespace DSP56K -/*************************************************************************** - PCU -***************************************************************************/ -static void pcu_reset(dsp56k_core* cpustate); -#define PC (cpustate->PCU.pc) -#define LA (cpustate->PCU.la) -#define LC (cpustate->PCU.lc) -#define SR (cpustate->PCU.sr) -#define OMR (cpustate->PCU.omr) -#define SP (cpustate->PCU.sp) -#define SS (cpustate->PCU.ss) - -#define SSH (SS[SP].w.h) -#define SSL (SS[SP].w.l) - -#define ST0 (SS[0].d) -#define ST1 (SS[1].d) -#define ST2 (SS[2].d) -#define ST3 (SS[3].d) -#define ST4 (SS[4].d) -#define ST5 (SS[5].d) -#define ST6 (SS[6].d) -#define ST7 (SS[7].d) -#define ST8 (SS[8].d) -#define ST9 (SS[9].d) -#define ST10 (SS[10].d) -#define ST11 (SS[11].d) -#define ST12 (SS[12].d) -#define ST13 (SS[13].d) -#define ST14 (SS[14].d) -#define ST15 (SS[15].d) - -/* STATUS REGISTER (SR) BITS (1-25) */ -/* MR */ -static UINT8 LF_bit(dsp56k_core* cpustate); -static UINT8 FV_bit(dsp56k_core* cpustate); -//static UINT8 S_bits(dsp56k_core* cpustate); -static UINT8 I_bits(dsp56k_core* cpustate); - -/* CCR - with macros for easy access */ -#define S() (S_bit(cpustate)) -static UINT8 S_bit(dsp56k_core* cpustate); -#define L() (L_bit(cpustate)) -static UINT8 L_bit(dsp56k_core* cpustate); -#define E() (E_bit(cpustate)) -static UINT8 E_bit(dsp56k_core* cpustate); -#define U() (U_bit(cpustate)) -static UINT8 U_bit(dsp56k_core* cpustate); -#define N() (N_bit(cpustate)) -static UINT8 N_bit(dsp56k_core* cpustate); -#define Z() (Z_bit(cpustate)) -static UINT8 Z_bit(dsp56k_core* cpustate); -#define V() (V_bit(cpustate)) -static UINT8 V_bit(dsp56k_core* cpustate); -#define C() (C_bit(cpustate)) -static UINT8 C_bit(dsp56k_core* cpustate); - -/* MR setters */ -static void LF_bit_set(dsp56k_core* cpustate, UINT8 value); -static void FV_bit_set(dsp56k_core* cpustate, UINT8 value); -static void S_bits_set(dsp56k_core* cpustate, UINT8 value); -static void I_bits_set(dsp56k_core* cpustate, UINT8 value); - -/* CCR setters - with macros for easy access */ -#define DSP56K_S_SET() (S_bit_set(cpustate, 1)) -#define DSP56K_S_CLEAR() (S_bit_set(cpustate, 0)) -static void S_bit_set(dsp56k_core* cpustate, UINT8 value); -#define DSP56K_L_SET() (L_bit_set(cpustate, 1)) -#define DSP56K_L_CLEAR() (L_bit_set(cpustate, 0)) -static void L_bit_set(dsp56k_core* cpustate, UINT8 value); -#define DSP56K_E_SET() (E_bit_set(cpustate, 1)) -#define DSP56K_E_CLEAR() (E_bit_set(cpustate, 0)) -static void E_bit_set(dsp56k_core* cpustate, UINT8 value); -#define DSP56K_U_SET() (U_bit_set(cpustate, 1)) -#define DSP56K_U_CLEAR() (U_bit_set(cpustate, 0)) -static void U_bit_set(dsp56k_core* cpustate, UINT8 value); -#define DSP56K_N_SET() (N_bit_set(cpustate, 1)) -#define DSP56K_N_CLEAR() (N_bit_set(cpustate, 0)) -static void N_bit_set(dsp56k_core* cpustate, UINT8 value); -#define DSP56K_Z_SET() (Z_bit_set(cpustate, 1)) -#define DSP56K_Z_CLEAR() (Z_bit_set(cpustate, 0)) -static void Z_bit_set(dsp56k_core* cpustate, UINT8 value); -#define DSP56K_V_SET() (V_bit_set(cpustate, 1)) -#define DSP56K_V_CLEAR() (V_bit_set(cpustate, 0)) -static void V_bit_set(dsp56k_core* cpustate, UINT8 value); -#define DSP56K_C_SET() (C_bit_set(cpustate, 1)) -#define DSP56K_C_CLEAR() (C_bit_set(cpustate, 0)) -static void C_bit_set(dsp56k_core* cpustate, UINT8 value); - -// TODO: Maybe some functions for Interrupt Mask and Scaling Mode go here? - - -/* 1-28 OPERATING MODE REGISTER (OMR) BITS */ -//static UINT8 CD_bit(dsp56k_core* cpustate); -//static UINT8 SD_bit(dsp56k_core* cpustate); -//static UINT8 R_bit(dsp56k_core* cpustate); -//static UINT8 SA_bit(dsp56k_core* cpustate); -//static UINT8 MC_bit(dsp56k_core* cpustate); -static UINT8 MB_bit(dsp56k_core* cpustate); -static UINT8 MA_bit(dsp56k_core* cpustate); - -static void CD_bit_set(dsp56k_core* cpustate, UINT8 value); -static void SD_bit_set(dsp56k_core* cpustate, UINT8 value); -static void R_bit_set(dsp56k_core* cpustate, UINT8 value); -static void SA_bit_set(dsp56k_core* cpustate, UINT8 value); -static void MC_bit_set(dsp56k_core* cpustate, UINT8 value); -static void MB_bit_set(dsp56k_core* cpustate, UINT8 value); -static void MA_bit_set(dsp56k_core* cpustate, UINT8 value); - -/* 1-27 STACK POINTER (SP) BITS */ -static UINT8 UF_bit(dsp56k_core* cpustate); -static UINT8 SE_bit(dsp56k_core* cpustate); - -//static void UF_bit_set(dsp56k_core* cpustate, UINT8 value) {}; -//static void SE_bit_set(dsp56k_core* cpustate, UINT8 value) {}; - - -// HACK - Bootstrap modes -#define BOOTSTRAP_OFF (0) -#define BOOTSTRAP_SSIX (1) -#define BOOTSTRAP_HI (2) - - -/* PCU IRQ goodies */ -static void pcu_service_interrupts(dsp56k_core* cpustate); - -static void dsp56k_irq_table_init(void); -static void dsp56k_set_irq_source(UINT8 irq_num, UINT16 iv, const char* source); -static int dsp56k_get_irq_index_by_tag(const char* tag); - -static void dsp56k_add_pending_interrupt(dsp56k_core* cpustate, const char* name); // Call me to add an interrupt to the queue - -static void dsp56k_clear_pending_interrupts(dsp56k_core* cpustate); -static int dsp56k_count_pending_interrupts(dsp56k_core* cpustate); -static void dsp56k_sort_pending_interrupts(dsp56k_core* cpustate, int num); -static INT8 dsp56k_get_irq_priority(dsp56k_core* cpustate, int index); - - - - -/*************************************************************************** - MEMORY -***************************************************************************/ - -// Adjusts the documented address to match the offset in peripheral RAM -#define A2O(a) (a-0xffc0) - -// Adjusts the offset in peripheral RAM to match the documented address -#define O2A(a) (a+0xffc0) - -// The memory 'registers' -#define PBC (dsp56k_peripheral_ram[A2O(0xffc0)]) -#define PCC (dsp56k_peripheral_ram[A2O(0xffc1)]) -#define PBDDR (dsp56k_peripheral_ram[A2O(0xffc2)]) -#define PCDDR (dsp56k_peripheral_ram[A2O(0xffc3)]) -#define HCR (dsp56k_peripheral_ram[A2O(0xffc4)]) -#define COCR (dsp56k_peripheral_ram[A2O(0xffc8)]) -#define CRASSI0 (dsp56k_peripheral_ram[A2O(0xffd0)]) -#define CRBSSI0 (dsp56k_peripheral_ram[A2O(0xffd1)]) -#define CRASSI1 (dsp56k_peripheral_ram[A2O(0xffd8)]) -#define CRBSSI1 (dsp56k_peripheral_ram[A2O(0xffd9)]) -#define PLCR (dsp56k_peripheral_ram[A2O(0xffdc)]) -#define BCR (dsp56k_peripheral_ram[A2O(0xffde)]) -#define IPR (dsp56k_peripheral_ram[A2O(0xffdf)]) -#define PBD (dsp56k_peripheral_ram[A2O(0xffe2)]) -#define PCD (dsp56k_peripheral_ram[A2O(0xffe3)]) -#define HSR (dsp56k_peripheral_ram[A2O(0xffe4)]) -#define HTXHRX (dsp56k_peripheral_ram[A2O(0xffe5)]) -#define COSR (dsp56k_peripheral_ram[A2O(0xffe8)]) -#define CRXCTX (dsp56k_peripheral_ram[A2O(0xffe9)]) -#define TCR (dsp56k_peripheral_ram[A2O(0xffec)]) -#define TCTR (dsp56k_peripheral_ram[A2O(0xffed)]) -#define TCPR (dsp56k_peripheral_ram[A2O(0xffee)]) -#define TPR (dsp56k_peripheral_ram[A2O(0xffef)]) -#define TSRSSI0 (dsp56k_peripheral_ram[A2O(0xfff0)]) -#define TRXSSI0 (dsp56k_peripheral_ram[A2O(0xfff1)]) -#define RSMA0 (dsp56k_peripheral_ram[A2O(0xfff2)]) -#define RSMB0 (dsp56k_peripheral_ram[A2O(0xfff3)]) -#define TSMA0 (dsp56k_peripheral_ram[A2O(0xfff4)]) -#define TSMB0 (dsp56k_peripheral_ram[A2O(0xfff5)]) -#define TSRSSI1 (dsp56k_peripheral_ram[A2O(0xfff8)]) -#define TRXSSI1 (dsp56k_peripheral_ram[A2O(0xfff9)]) -#define RSMA1 (dsp56k_peripheral_ram[A2O(0xfffa)]) -#define RSMB1 (dsp56k_peripheral_ram[A2O(0xfffb)]) -#define TSMA1 (dsp56k_peripheral_ram[A2O(0xfffc)]) -#define TSMB1 (dsp56k_peripheral_ram[A2O(0xfffd)]) - -/* Interrupt priority register (IPR) bits */ -static void IPR_set(dsp56k_core* cpustate, UINT16 value); - -/* A return value of -1 means disabled */ -static INT8 irqa_ipl(dsp56k_core* cpustate); -static INT8 irqb_ipl(dsp56k_core* cpustate); -static UINT8 irqa_trigger(dsp56k_core* cpustate); -static UINT8 irqb_trigger(dsp56k_core* cpustate); - -static INT8 codec_ipl(dsp56k_core* cpustate); -static INT8 host_ipl(dsp56k_core* cpustate); -static INT8 ssi0_ipl(dsp56k_core* cpustate); -static INT8 ssi1_ipl(dsp56k_core* cpustate); -static INT8 tm_ipl(dsp56k_core* cpustate); - - -/*************************************************************************** - HOST INTERFACE -***************************************************************************/ -static void dsp56k_host_interface_reset(dsp56k_core* cpustate); -#define HTX (HTXHRX) -#define HRX (HTXHRX) - -#define ICR (cpustate->HI.icr) -#define CVR (cpustate->HI.cvr) -#define ISR (cpustate->HI.isr) -#define IVR (cpustate->HI.ivr) -#define TXH (cpustate->HI.trxh) -#define TXL (cpustate->HI.trxl) -#define RXH (cpustate->HI.trxh) -#define RXL (cpustate->HI.trxl) - -/***************/ -/* DSP56k SIDE */ -/***************/ -/* Host Control Register (HCR) Bits */ -static void HCR_set(dsp56k_core* cpustate, UINT16 value); - -//static UINT16 HF3_bit(dsp56k_core* cpustate); #define hf3BIT ((HCR & 0x0010) != 0) -//static UINT16 HF2_bit(dsp56k_core* cpustate); #define hf2BIT ((HCR & 0x0008) != 0) -static UINT16 HCIE_bit(dsp56k_core* cpustate); -static UINT16 HTIE_bit(dsp56k_core* cpustate); -static UINT16 HRIE_bit(dsp56k_core* cpustate); - -static void HF3_bit_set(dsp56k_core* cpustate, UINT16 value); -static void HF2_bit_set(dsp56k_core* cpustate, UINT16 value); -static void HCIE_bit_set(dsp56k_core* cpustate, UINT16 value); -static void HTIE_bit_set(dsp56k_core* cpustate, UINT16 value); -static void HRIE_bit_set(dsp56k_core* cpustate, UINT16 value); - -/* Host Status Register (HSR) Bits */ -//static void HSR_set(dsp56k_core* cpustate, UINT16 value); - -//static UINT16 DMA_bit(dsp56k_core* cpustate); #define dmaBIT ((HSR & 0x0080) != 0) -//static UINT16 HF1_bit(dsp56k_core* cpustate); #define hf1BIT ((HSR & 0x0010) != 0) -//static UINT16 HF0_bit(dsp56k_core* cpustate); #define hf0BIT ((HSR & 0x0008) != 0) -//static UINT16 HCP_bit(dsp56k_core* cpustate); #define hcpBIT ((HSR & 0x0004) != 0) -static UINT16 HTDE_bit(dsp56k_core* cpustate); -static UINT16 HRDF_bit(dsp56k_core* cpustate); - -static void DMA_bit_set(dsp56k_core* cpustate, UINT16 value); -static void HF1_bit_set(dsp56k_core* cpustate, UINT16 value); -static void HF0_bit_set(dsp56k_core* cpustate, UINT16 value); -static void HCP_bit_set(dsp56k_core* cpustate, UINT16 value); -static void HTDE_bit_set(dsp56k_core* cpustate, UINT16 value); -static void HRDF_bit_set(dsp56k_core* cpustate, UINT16 value); - -/*************/ -/* HOST SIDE */ -/*************/ -/* Interrupt Control Register (ICR) Bits */ -static void ICR_set(dsp56k_core* cpustate, UINT8 value); - -//static UINT8 INIT_bit(dsp56k_core* cpustate); #define x_initBIT ((dsp56k.HI.ICR & 0x0080) != 0) -//static UINT8 HM1_bit(dsp56k_core* cpustate); #define x_hm1BIT ((dsp56k.HI.ICR & 0x0040) != 0) -//static UINT8 HM0_bit(dsp56k_core* cpustate); #define x_hm0BIT ((dsp56k.HI.ICR & 0x0020) != 0) -//static UINT8 HF1_bit_host(dsp56k_core* cpustate); #define x_hf1BIT ((dsp56k.HI.ICR & 0x0010) != 0) -//static UINT8 HF0_bit_host(dsp56k_core* cpustate); #define x_hf0BIT ((dsp56k.HI.ICR & 0x0008) != 0) -//static UINT8 TREQ_bit(dsp56k_core* cpustate); #define x_treqBIT ((dsp56k.HI.ICR & 0x0002) != 0) -//static UINT8 RREQ_bit(dsp56k_core* cpustate); #define x_rreqBIT ((dsp56k.HI.ICR & 0x0001) != 0) - -//static void INIT_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_initBIT() (dsp56k.HI.ICR &= (~0x0080)) -//static void HM1_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_hm1BIT() (dsp56k.HI.ICR &= (~0x0040)) -//static void HM0_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_hm0BIT() (dsp56k.HI.ICR &= (~0x0020)) -static void HF1_bit_host_set(dsp56k_core* cpustate, UINT8 value); -static void HF0_bit_host_set(dsp56k_core* cpustate, UINT8 value); -static void TREQ_bit_set(dsp56k_core* cpustate, UINT8 value); -static void RREQ_bit_set(dsp56k_core* cpustate, UINT8 value); - -/* Command Vector Register (CVR) Bits */ -static void CVR_set(dsp56k_core* cpustate, UINT8 value); - -//static UINT8 HC_bit(); -static UINT8 HV_bits(dsp56k_core* cpustate); - -static void HC_bit_set(dsp56k_core* cpustate, UINT8 value); -static void HV_bits_set(dsp56k_core* cpustate, UINT8 value); - -/* Interrupt Status Register (ISR) Bits */ -// static void ISR_set(dsp56k_core* cpustate, UINT8 value); - -//static UINT8 HREQ_bit(dsp56k_core* cpustate); #define x_hreqBIT ((dsp56k.HI.ISR & 0x0080) != 0) -//static UINT8 DMA_bit(dsp56k_core* cpustate); #define x_dmaBIT ((dsp56k.HI.ISR & 0x0040) != 0) -//static UINT8 HF3_bit_host(dsp56k_core* cpustate); #define x_hf3BIT ((dsp56k.HI.ISR & 0x0010) != 0) -//static UINT8 HF2_bit_host(dsp56k_core* cpustate); #define x_hf2BIT ((dsp56k.HI.ISR & 0x0008) != 0) -//static UINT8 TRDY_bit(dsp56k_core* cpustate); #define x_trdyBIT ((dsp56k.HI.ISR & 0x0004) != 0) -static UINT8 TXDE_bit(dsp56k_core* cpustate); -static UINT8 RXDF_bit(dsp56k_core* cpustate); - -//static void HREQ_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_hreqBIT() (dsp56k.HI.ISR &= (~0x0080)) -//static void DMA_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_dmaBIT() (dsp56k.HI.ISR &= (~0x0040)) -static void HF3_bit_host_set(dsp56k_core* cpustate, UINT8 value); -static void HF2_bit_host_set(dsp56k_core* cpustate, UINT8 value); -//static void TRDY_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_trdyBIT() (dsp56k.HI.ISR &= (~0x0004)) -static void TXDE_bit_set(dsp56k_core* cpustate, UINT8 value); -static void RXDF_bit_set(dsp56k_core* cpustate, UINT8 value); - -/* Interrupt Vector Register (IVR) Bits */ -//static void IVR_set(dsp56k_core* cpustate, UINT8 value); - -//static UINT8 IV7_bit(dsp56k_core* cpustate); -//static UINT8 IV6_bit(dsp56k_core* cpustate); -//static UINT8 IV5_bit(dsp56k_core* cpustate); -//static UINT8 IV4_bit(dsp56k_core* cpustate); -//static UINT8 IV3_bit(dsp56k_core* cpustate); -//static UINT8 IV2_bit(dsp56k_core* cpustate); -//static UINT8 IV1_bit(dsp56k_core* cpustate); -//static UINT8 IV0_bit(dsp56k_core* cpustate); - -//static void IV7_bit_set(dsp56k_core* cpustate, UINT8 value); -//static void IV6_bit_set(dsp56k_core* cpustate, UINT8 value); -//static void IV5_bit_set(dsp56k_core* cpustate, UINT8 value); -//static void IV4_bit_set(dsp56k_core* cpustate, UINT8 value); -//static void IV3_bit_set(dsp56k_core* cpustate, UINT8 value); -//static void IV2_bit_set(dsp56k_core* cpustate, UINT8 value); -//static void IV1_bit_set(dsp56k_core* cpustate, UINT8 value); -//static void IV0_bit_set(dsp56k_core* cpustate, UINT8 value); - - -/* PROTOTYPES */ -static void dsp56k_host_interface_HTX_to_host(dsp56k_core* cpustate); -static void dsp56k_host_interface_host_to_HTX(dsp56k_core* cpustate); - - -/*************************************************************************** - I/O INTERFACE -***************************************************************************/ -static void dsp56k_io_reset(dsp56k_core* cpustate); - -/* Port A Bus Control Register (BCR) */ -static void BCR_set(dsp56k_core* cpustate, UINT16 value); - -//static UINT16 RH_bit(dsp56k_core* cpustate); -//static UINT16 BS_bit(dsp56k_core* cpustate); -//static UINT16 external_x_wait_states(dsp56k_core* cpustate); -//static UINT16 external_p_wait_states(dsp56k_core* cpustate); - -static void RH_bit_set(dsp56k_core* cpustate, UINT16 value); -static void BS_bit_set(dsp56k_core* cpustate, UINT16 value); -static void external_x_wait_states_set(dsp56k_core* cpustate, UINT16 value); -static void external_p_wait_states_set(dsp56k_core* cpustate, UINT16 value); - -/* Port B Control Register (PBC) */ -static void PBC_set(dsp56k_core* cpustate, UINT16 value); -//static int host_interface_active(dsp56k_core* cpustate); - -/* Port B Data Direction Register (PBDDR) */ -static void PBDDR_set(dsp56k_core* cpustate, UINT16 value); - -/* Port B Data Register (PBD) */ -static void PBD_set(dsp56k_core* cpustate, UINT16 value); - -/* Port C Control Register (PCC) */ -static void PCC_set(dsp56k_core* cpustate, UINT16 value); - -/* Port C Data Direction Register (PCDDR) */ -static void PCDDR_set(dsp56k_core* cpustate, UINT16 value); - -/* Port C Dtaa Register (PCD) */ -static void PCD_set(dsp56k_core* cpustate, UINT16 value); - - -INLINE dsp56k_core *get_safe_token(running_device *device) -{ - assert(device != NULL); - assert(device->type() == DSP56156); - return (dsp56k_core *)downcast(device)->token(); -} +#endif diff --git a/src/emu/cpu/dsp56k/dsp56k.c b/src/emu/cpu/dsp56k/dsp56k.c index 9e498a74558..9c690b3e4a7 100644 --- a/src/emu/cpu/dsp56k/dsp56k.c +++ b/src/emu/cpu/dsp56k/dsp56k.c @@ -21,7 +21,7 @@ - 1-9 For fractional arithmetic, the 31-bit product is added to the 40-bit contents of A or B. No pipeline! - 1-10 Two types of rounding: convergent rounding and two's complement rounding. See status register bit R. - 1-10 Logic unit is 16-bits wide and works on MSP portion of accum register - - 1-10 The AGU can implement three types of arithmetic: linear, modulo, and reverse carry. + - 1-10 The AGU can implement three types of arithmetic: linear, modulo, and reverse carry. - 1-12 "Two external interrupt pins!!!" - 1-12 Take care of all interrupt priority (IPR) stuff! - 1-19 Memory WAIT states @@ -29,12 +29,16 @@ - 1-21 Vectored exception requests on the Host Interface! ***************************************************************************/ +#include "opcode.h" + #include "emu.h" #include "debugger.h" #include "dsp56k.h" #include "dsp56def.h" +using namespace DSP56K; + /*************************************************************************** FUNCTION PROTOTYPES ***************************************************************************/ @@ -42,30 +46,29 @@ static CPU_RESET( dsp56k ); /*************************************************************************** - ONBOARD MEMORY ALLOCATION + ONBOARD MEMORY ***************************************************************************/ -// TODO: Put these in the cpustate!!! -static UINT16 *dsp56k_peripheral_ram; -static UINT16 *dsp56k_program_ram; +UINT16 *dsp56k_peripheral_ram; +UINT16 *dsp56k_program_ram; /*************************************************************************** COMPONENT FUNCTIONALITY ***************************************************************************/ /* 1-9 ALU */ -// #include "dsp56alu.c" +// #include "dsp56alu.h" /* 1-10 Address Generation Unit (AGU) */ -// #include "dsp56agu.c" +// #include "dsp56agu.h" /* 1-11 Program Control Unit (PCU) */ -#include "dsp56pcu.c" +#include "dsp56pcu.h" /* 5-1 Host Interface (HI) */ -//#include "dsp56hi.c" +//#include "dsp56hi.h" /* 4-8 Memory handlers for on-chip peripheral memory. */ -#include "dsp56mem.c" +#include "dsp56mem.h" /*************************************************************************** @@ -306,13 +309,30 @@ static CPU_EXIT( dsp56k ) /*************************************************************************** CORE INCLUDE ***************************************************************************/ -#define OP (cpustate->op) #include "dsp56ops.c" /*************************************************************************** CORE EXECUTION LOOP ***************************************************************************/ +// Execute a single opcode and return how many cycles it took. +static size_t execute_one_new(dsp56k_core* cpustate) +{ + // For MAME + cpustate->op = ROPCODE(ADDRESS(PC)); + debugger_instruction_hook(cpustate->device, PC); + + UINT16 w0 = ROPCODE(ADDRESS(PC)); + UINT16 w1 = ROPCODE(ADDRESS(PC) + ADDRESS(1)); + + Opcode op(w0, w1); + op.evaluate(cpustate); + PC += op.evalSize(); // Special size function needed to handle jmps, etc. + + // TODO: Currently all operations take up 4 cycles (inst->cycles()). + return 4; +} + static CPU_EXECUTE( dsp56k ) { dsp56k_core* cpustate = get_safe_token(device); @@ -331,17 +351,15 @@ static CPU_EXECUTE( dsp56k ) return; } - cpustate->icount -= cpustate->interrupt_cycles; - cpustate->interrupt_cycles = 0; + //cpustate->icount -= cpustate->interrupt_cycles; + //cpustate->interrupt_cycles = 0; while(cpustate->icount > 0) { execute_one(cpustate); - pcu_service_interrupts(cpustate); /* TODO: There is definitely something un-right about this */ + if (0) cpustate->icount -= execute_one_new(cpustate); + pcu_service_interrupts(cpustate); // TODO: Is it incorrect to service after each instruction? } - - cpustate->icount -= cpustate->interrupt_cycles; - cpustate->interrupt_cycles = 0; } @@ -452,18 +470,18 @@ CPU_GET_INFO( dsp56k ) case CPUINFO_INT_CLOCK_DIVIDER: info->i = 2; break; case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break; case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; // ? - case CPUINFO_INT_MAX_CYCLES: info->i = 8; break; // ? + case CPUINFO_INT_MIN_CYCLES: info->i = 1; // ? break; + case CPUINFO_INT_MAX_CYCLES: info->i = 8; // ? break; - case DEVINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 16; break; /* 1-5 */ - case DEVINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 16; break; /* 1-5 */ - case DEVINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_PROGRAM: info->i = -1; break; - case DEVINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 16; break; - case DEVINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 16; break; - case DEVINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_DATA: info->i = -1; break; - case DEVINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break; - case DEVINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break; - case DEVINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break; + case DEVINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 16; break; + case DEVINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 16; break; + case DEVINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_PROGRAM: info->i = -1; break; + case DEVINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 16; break; + case DEVINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 16; break; + case DEVINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_DATA: info->i = -1; break; + case DEVINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break; + case DEVINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break; + case DEVINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break; case CPUINFO_INT_INPUT_STATE + DSP56K_IRQ_MODA: info->i = DSP56K_IRQ_MODA; break; case CPUINFO_INT_INPUT_STATE + DSP56K_IRQ_MODB: info->i = DSP56K_IRQ_MODB; break; @@ -503,8 +521,8 @@ CPU_GET_INFO( dsp56k ) case CPUINFO_INT_REGISTER + DSP56K_M2: info->i = M2; break; case CPUINFO_INT_REGISTER + DSP56K_M3: info->i = M3; break; - /* case CPUINFO_INT_REGISTER + DSP56K_TEMP: info->i = TEMP; break; */ - /* case CPUINFO_INT_REGISTER + DSP56K_STATUS: info->i = STATUS; break; */ + /* case CPUINFO_INT_REGISTER + DSP56K_TEMP: info->i = TEMP; break; */ + /* case CPUINFO_INT_REGISTER + DSP56K_STATUS: info->i = STATUS; break; */ /* The CPU stack */ case CPUINFO_INT_REGISTER + DSP56K_ST0: info->i = ST0; break; @@ -568,7 +586,7 @@ CPU_GET_INFO( dsp56k ) /* Stack Pointer */ UF_bit(cpustate) ? "U" : ".", SE_bit(cpustate) ? "S" : "."); - break; + break; case CPUINFO_STR_REGISTER + DSP56K_PC: sprintf(info->s, "PC : %04x", PC); break; case CPUINFO_STR_REGISTER + DSP56K_SR: sprintf(info->s, "SR : %04x", SR); break; diff --git a/src/emu/cpu/dsp56k/dsp56k.h b/src/emu/cpu/dsp56k/dsp56k.h index e1629d8f814..2fad1167395 100644 --- a/src/emu/cpu/dsp56k/dsp56k.h +++ b/src/emu/cpu/dsp56k/dsp56k.h @@ -12,6 +12,7 @@ #ifndef __DSP56K_H__ #define __DSP56K_H__ +#include "emu.h" /*************************************************************************** REGISTER ENUMERATION @@ -237,6 +238,14 @@ typedef struct } dsp56k_core; +INLINE dsp56k_core *get_safe_token(running_device *device) +{ + assert(device != NULL); + assert(device->type() == DSP56156); + return (dsp56k_core *)downcast(device)->token(); +} + + /*************************************************************************** PUBLIC FUNCTIONS - ACCESSIBLE TO DRIVERS ***************************************************************************/ diff --git a/src/emu/cpu/dsp56k/dsp56mem.c b/src/emu/cpu/dsp56k/dsp56mem.c index c25f746c1cd..c5fcdd630c3 100644 --- a/src/emu/cpu/dsp56k/dsp56mem.c +++ b/src/emu/cpu/dsp56k/dsp56mem.c @@ -1,25 +1,33 @@ // This file contains functions which handle the On-Chip peripheral Memory Map // as well as the Host Interface and the SSI0/SSI1 Serial Interfaces. +#include "dsp56mem.h" +#include "dsp56pcu.h" + +extern UINT16 *dsp56k_peripheral_ram; +extern UINT16 *dsp56k_program_ram; + +namespace DSP56K +{ /* IPR Accessor Implementations */ -static void IPR_set(dsp56k_core* cpustate, UINT16 value) +void IPR_set(dsp56k_core* cpustate, UINT16 value) { /* TODO: Is there anything else? */ IPR = value; } -static INT8 irqa_ipl(dsp56k_core* cpustate) { return ((IPR & 0x0003) >> 0) - 1; } -static UINT8 irqa_trigger(dsp56k_core* cpustate){ return (IPR & 0x0004) >> 2; } -static INT8 irqb_ipl(dsp56k_core* cpustate) { return ((IPR & 0x0018) >> 3) - 1; } -static UINT8 irqb_trigger(dsp56k_core* cpustate){ return (IPR & 0x0002) >> 5; } -static INT8 codec_ipl(dsp56k_core* cpustate) { return ((IPR & 0x00c0) >> 6) - 1; } -static INT8 host_ipl(dsp56k_core* cpustate) { return ((IPR & 0x0300) >> 8) - 1; } -static INT8 ssi0_ipl(dsp56k_core* cpustate) { return ((IPR & 0x0c00) >> 10) - 1; } -static INT8 ssi1_ipl(dsp56k_core* cpustate) { return ((IPR & 0x3000) >> 12) - 1; } -static INT8 tm_ipl(dsp56k_core* cpustate) { return ((IPR & 0xc000) >> 14) - 1; } +INT8 irqa_ipl(dsp56k_core* cpustate) { return ((IPR & 0x0003) >> 0) - 1; } +UINT8 irqa_trigger(dsp56k_core* cpustate){ return (IPR & 0x0004) >> 2; } +INT8 irqb_ipl(dsp56k_core* cpustate) { return ((IPR & 0x0018) >> 3) - 1; } +UINT8 irqb_trigger(dsp56k_core* cpustate){ return (IPR & 0x0002) >> 5; } +INT8 codec_ipl(dsp56k_core* cpustate) { return ((IPR & 0x00c0) >> 6) - 1; } +INT8 host_ipl(dsp56k_core* cpustate) { return ((IPR & 0x0300) >> 8) - 1; } +INT8 ssi0_ipl(dsp56k_core* cpustate) { return ((IPR & 0x0c00) >> 10) - 1; } +INT8 ssi1_ipl(dsp56k_core* cpustate) { return ((IPR & 0x3000) >> 12) - 1; } +INT8 tm_ipl(dsp56k_core* cpustate) { return ((IPR & 0xc000) >> 14) - 1; } -static void mem_reset(dsp56k_core* cpustate) +void mem_reset(dsp56k_core* cpustate) { // Reset the HI registers dsp56k_host_interface_reset(cpustate); @@ -28,8 +36,460 @@ static void mem_reset(dsp56k_core* cpustate) dsp56k_io_reset(cpustate); } + +/*************************************************************************** + HOST INTERFACE +***************************************************************************/ +/***************/ +/* DSP56k SIDE */ +/***************/ +/************************************/ +/* Host Control Register (HCR) Bits */ +/************************************/ +void HCR_set(dsp56k_core* cpustate, UINT16 value) +{ + HF3_bit_set (cpustate, (value & 0x0010) >> 4); + HF2_bit_set (cpustate, (value & 0x0008) >> 3); + HCIE_bit_set(cpustate, (value & 0x0004) >> 2); + HTIE_bit_set(cpustate, (value & 0x0002) >> 1); + HRIE_bit_set(cpustate, (value & 0x0001) >> 0); +} +//UINT16 HF3_bit(dsp56k_core* cpustate) { return ((HCR & 0x0010) != 0); } +//UINT16 HF2_bit(dsp56k_core* cpustate) { return ((HCR & 0x0008) != 0); } +UINT16 HCIE_bit(dsp56k_core* cpustate) { return ((HCR & 0x0004) != 0); } +UINT16 HTIE_bit(dsp56k_core* cpustate) { return ((HCR & 0x0002) != 0); } +UINT16 HRIE_bit(dsp56k_core* cpustate) { return ((HCR & 0x0001) != 0); } + +void HF3_bit_set(dsp56k_core* cpustate, UINT16 value) +{ + value = value & 0x01; + HCR &= ~(0x0010); + HCR |= (value << 4); + + HF3_bit_host_set(cpustate, value); +} +void HF2_bit_set(dsp56k_core* cpustate, UINT16 value) +{ + value = value & 0x01; + HCR &= ~(0x0008); + HCR |= (value << 3); + + HF2_bit_host_set(cpustate, value); +} +void HCIE_bit_set(dsp56k_core* cpustate, UINT16 value) +{ + value = value & 0x01; + HCR &= ~(0x0004); + HCR |= (value << 2); +} +void HTIE_bit_set(dsp56k_core* cpustate, UINT16 value) +{ + value = value & 0x01; + HCR &= ~(0x0002); + HCR |= (value << 1); +} +void HRIE_bit_set(dsp56k_core* cpustate, UINT16 value) +{ + value = value & 0x01; + HCR &= ~(0x0001); + HCR |= (value << 0); +} + +/***********************************/ +/* Host Status Register (HSR) Bits */ +/***********************************/ +//UINT16 DMA_bit(dsp56k_core* cpustate) { return ((HSR & 0x0080) != 0); } +//UINT16 HF1_bit(dsp56k_core* cpustate) { return ((HSR & 0x0010) != 0); } +//UINT16 HF0_bit(dsp56k_core* cpustate) { return ((HSR & 0x0008) != 0); } +//UINT16 HCP_bit(dsp56k_core* cpustate) { return ((HSR & 0x0004) != 0); } +UINT16 HTDE_bit(dsp56k_core* cpustate) { return ((HSR & 0x0002) != 0); } +UINT16 HRDF_bit(dsp56k_core* cpustate) { return ((HSR & 0x0001) != 0); } + +void DMA_bit_set(dsp56k_core* cpustate, UINT16 value) +{ + value = value & 0x01; + HSR &= ~(0x0080); + HSR |= (value << 7); + // TODO: 5-12 When the DMA bit is set, the DMA mode is enabled by the Host Mode bits HM0 & HM1 +} +void HF1_bit_set(dsp56k_core* cpustate, UINT16 value) +{ + value = value & 0x01; + HSR &= ~(0x0010); + HSR |= (value << 4); +} +void HF0_bit_set(dsp56k_core* cpustate, UINT16 value) +{ + value = value & 0x01; + HSR &= ~(0x0008); + HSR |= (value << 3); +} +void HCP_bit_set(dsp56k_core* cpustate, UINT16 value) +{ + value = value & 0x01; + HSR &= ~(0x0004); + HSR |= (value << 2); + + if (value && HCIE_bit(cpustate)) + dsp56k_add_pending_interrupt(cpustate, "Host Command"); +} +void HTDE_bit_set(dsp56k_core* cpustate, UINT16 value) +{ + value = value & 0x01; + HSR &= ~(0x0002); + HSR |= (value << 1); + + // 5-10 If HTIE bit is set, whip out a Host Transmit Data interrupt + if (value && HTIE_bit(cpustate)) + dsp56k_add_pending_interrupt(cpustate, "Host Transmit Data"); + + // 5-5 If both me and RXDF are cleared, transmit data to the host + if (!value && !RXDF_bit(cpustate)) + dsp56k_host_interface_HTX_to_host(cpustate); +} +void HRDF_bit_set(dsp56k_core* cpustate, UINT16 value) +{ + value = value & 0x01; + HSR &= ~(0x0001); + HSR |= (value << 0); + + // 5-10 If HRIE is set, whip out a Host Receive Data interrupt + if (value && HRIE_bit(cpustate)) + dsp56k_add_pending_interrupt(cpustate, "Host Receive Data"); + + // 5-5 If both me and TXDE are cleared, transmit data to the dsp56k + if (!value && !TXDE_bit(cpustate)) + dsp56k_host_interface_host_to_HTX(cpustate); +} + + + +/*************/ +/* HOST SIDE */ +/*************/ +/*****************************************/ +/* Interrupt Control Register (ICR) Bits */ +/*****************************************/ +void ICR_set(dsp56k_core* cpustate, UINT8 value) +{ + HF1_bit_host_set(cpustate, (value & 0x10) >> 4); + HF0_bit_host_set(cpustate, (value & 0x08) >> 3); + TREQ_bit_set(cpustate, (value & 0x02) >> 1); + RREQ_bit_set(cpustate, (value & 0x01) >> 0); +} + +//UINT8 INIT_bit(dsp56k_core* cpustate); #define x_initBIT ((dsp56k.HI.ICR & 0x0080) != 0) +//UINT8 HM1_bit(dsp56k_core* cpustate); #define x_hm1BIT ((dsp56k.HI.ICR & 0x0040) != 0) +//UINT8 HM0_bit(dsp56k_core* cpustate); #define x_hm0BIT ((dsp56k.HI.ICR & 0x0020) != 0) +//UINT8 HF1_bit_host(dsp56k_core* cpustate); #define x_hf1BIT ((dsp56k.HI.ICR & 0x0010) != 0) +//UINT8 HF0_bit_host(dsp56k_core* cpustate); #define x_hf0BIT ((dsp56k.HI.ICR & 0x0008) != 0) +//UINT8 TREQ_bit(dsp56k_core* cpustate); #define x_treqBIT ((dsp56k.HI.ICR & 0x0002) != 0) +//UINT8 RREQ_bit(dsp56k_core* cpustate); #define x_rreqBIT ((dsp56k.HI.ICR & 0x0001) != 0) + +//void INIT_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_initBIT() (dsp56k.HI.ICR &= (~0x0080)) +//void HM1_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_hm1BIT() (dsp56k.HI.ICR &= (~0x0040)) +//void HM0_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_hm0BIT() (dsp56k.HI.ICR &= (~0x0020)) +void HF1_bit_host_set(dsp56k_core* cpustate, UINT8 value) +{ + value = value & 0x01; + ICR &= ~(0x10); + ICR |= (value << 4); + + HF1_bit_set(cpustate, value); // 5-14 +} +void HF0_bit_host_set(dsp56k_core* cpustate, UINT8 value) +{ + value = value & 0x01; + ICR &= ~(0x08); + ICR |= (value << 3); + + HF0_bit_set(cpustate, value); // 5-13 +} +void TREQ_bit_set(dsp56k_core* cpustate, UINT8 value) +{ + value = value & 0x01; + ICR &= ~(0x02); + ICR |= (value << 1); +} +void RREQ_bit_set(dsp56k_core* cpustate, UINT8 value) +{ + value = value & 0x01; + ICR &= ~(0x01); + ICR |= (value << 0); + + // 5-12 + if (value) + { + // TODO : HREQ_assert(); + } +} + + + +/**************************************/ +/* Command Vector Register (CVR) Bits */ +/**************************************/ +UINT8 HV_bits(dsp56k_core* cpustate) { return (CVR & 0x1f); } + +void CVR_set(dsp56k_core* cpustate, UINT8 value) +{ + /* A single, unified place to run all callbacks for each of the bits */ + HC_bit_set(cpustate, (value & 0x80) >> 7); + HV_bits_set(cpustate, (value & 0x1f)); +} + +void HC_bit_set(dsp56k_core* cpustate, UINT8 value) +{ + value = value & 0x01; + CVR &= ~(0x80); + CVR |= (value << 7); + + HCP_bit_set(cpustate, value); // 5-9 & 5-11 +} +void HV_bits_set(dsp56k_core* cpustate, UINT8 value) +{ + value = value & 0x1f; + CVR &= ~(0x1f); + CVR |= (value << 0); +} + + +/****************************************/ +/* Interrupt Status Register (ISR) Bits */ +/****************************************/ +UINT8 TXDE_bit(dsp56k_core* cpustate) { return ((ISR & 0x0002) != 0); } +UINT8 RXDF_bit(dsp56k_core* cpustate) { return ((ISR & 0x0001) != 0); } + +void HF3_bit_host_set(dsp56k_core* cpustate, UINT8 value) +{ + value = value & 0x01; + ISR &= ~(0x0010); + ISR |= (value << 4); +} +void HF2_bit_host_set(dsp56k_core* cpustate, UINT8 value) +{ + value = value & 0x01; + ISR &= ~(0x0008); + ISR |= (value << 3); +} + +void TXDE_bit_set(dsp56k_core* cpustate, UINT8 value) +{ + value = value & 0x01; + ISR &= ~(0x0002); + ISR |= (value << 1); + + // If both me and the HRDF are cleared, transmit data to the dsp56k + if (!value && !HRDF_bit(cpustate)) + dsp56k_host_interface_host_to_HTX(cpustate); +} + +void RXDF_bit_set(dsp56k_core* cpustate, UINT8 value) +{ + value = value & 0x01; + ISR &= ~(0x0001); + ISR |= (value << 0); + + // If both me and HTDE are cleared, transmit data to the host + if (!value && !HTDE_bit(cpustate)) + dsp56k_host_interface_HTX_to_host(cpustate); +} + + +// TODO: 5-11 What is the host processor Initialize function? + +void dsp56k_host_interface_reset(dsp56k_core* cpustate) +{ + // Hook up the CPU-side pointers properly. + cpustate->HI.hcr = &dsp56k_peripheral_ram[A2O(0xffc4)]; + cpustate->HI.hsr = &dsp56k_peripheral_ram[A2O(0xffe4)]; + cpustate->HI.htrx = &dsp56k_peripheral_ram[A2O(0xffe5)]; + + // The Bootstrap hack is initialized to write to address 0x0000 + cpustate->HI.bootstrap_offset = 0x0000; + + /* HCR */ + HCR_set(cpustate, 0x0000); // 5-10 + + /* HSR */ + HRDF_bit_set(cpustate, 0); // 5-11 + HTDE_bit_set(cpustate, 1); // 5-11 + HCP_bit_set(cpustate, 0); // 5-11 + HF0_bit_set(cpustate, 0); // 5-12 + HF1_bit_set(cpustate, 0); // 5-12 + DMA_bit_set(cpustate, 0); // 5-12 + + /* CVR*/ + HV_bits_set(cpustate, 0x16); // 5-7 + HC_bit_set(cpustate, 0); // 5-9 + + /* TODO: ISR (at least) */ +} + +void dsp56k_host_interface_HTX_to_host(dsp56k_core* cpustate) +{ + RXH = ((HTX & 0xff00) >> 8); + RXL = ((HTX & 0x00ff)); + RXDF_bit_set(cpustate, 1); + HTDE_bit_set(cpustate, 1); +} + +void dsp56k_host_interface_host_to_HTX(dsp56k_core* cpustate) +{ + HRX &= 0x00ff; + HRX |= (TXH << 8); + HRX &= 0xff00; + HRX |= TXL; + TXDE_bit_set(cpustate, 1); + HRDF_bit_set(cpustate, 1); +} + + +/*************************************************************************** + I/O INTERFACE +***************************************************************************/ +/* BCR */ +void BCR_set(dsp56k_core* cpustate, UINT16 value) +{ + RH_bit_set(cpustate, (value & 0x8000) >> 15); + BS_bit_set(cpustate, (value & 0x4000) >> 14); + external_x_wait_states_set(cpustate, (value & 0x03e0) >> 5); + external_p_wait_states_set(cpustate, (value & 0x001f) >> 0); +} + +//UINT16 RH_bit(dsp56k_core* cpustate); +//UINT16 BS_bit(dsp56k_core* cpustate); +//UINT16 external_x_wait_states(dsp56k_core* cpustate); +//UINT16 external_p_wait_states(dsp56k_core* cpustate); + +void RH_bit_set(dsp56k_core* cpustate, UINT16 value) +{ + value = value & 0x0001; + BCR &= ~(0x8000); + BCR |= (value << 15); + + // TODO: 4-6 Assert BR pin? +} +void BS_bit_set(dsp56k_core* cpustate, UINT16 value) +{ + value = value & 0x0001; + BCR &= ~(0x4000); + BCR |= (value << 14); + + // TODO: 4-6 Respond to BR pin? +} +void external_x_wait_states_set(dsp56k_core* cpustate, UINT16 value) +{ + value = value & 0x001f; + BCR &= ~(0x03e0); + BCR |= (value << 5); +} +void external_p_wait_states_set(dsp56k_core* cpustate, UINT16 value) +{ + value = value & 0x001f; + BCR &= ~(0x001f); + BCR |= (value << 0); +} + + +/* Port B Control Register PBC */ +void PBC_set(dsp56k_core* cpustate, UINT16 value) +{ + if (value & 0xfffe) + logerror("Dsp56k : Attempting to set reserved bits in the PBC. Ignoring.\n"); + + value = value & 0x0001; + PBC &= ~(0x0001); + PBC |= (value << 0); +} + +#ifdef UNUSED_FUNCTION +int host_interface_active(dsp56k_core* cpustate) +{ + /* The host interface is active if the 0th bit in the PBC is set */ + return PBC & 0x0001; +} +#endif + +/* Port B Data Direction Register (PBDDR) */ +void PBDDR_set(dsp56k_core* cpustate, UINT16 value) +{ + if (value & 0x8000) + logerror("Dsp56k : Attempting to set reserved bits in the PBDDR. Ignoring.\n"); + + value = value & 0x7fff; + PBDDR &= ~(0x7fff); + PBDDR |= (value << 0); + + /* TODO: Implement dsp56k io restrictions, etc. */ +} + +/* Port B Data Register (PBD) */ +void PBD_set(dsp56k_core* cpustate, UINT16 value) +{ + if (value & 0x8000) + logerror("Dsp56k : Attempting to set reserved bits in the PBD. Ignoring.\n"); + + value = value & 0x7fff; + PBD &= ~(0x7fff); + PBD |= (value << 0); + + /* TODO: Implement dsp56k io restrictions, etc. */ +} + +/* Port C Control Register (PCC) */ +void PCC_set(dsp56k_core* cpustate, UINT16 value) +{ + if (value & 0xf000) + logerror("Dsp56k : Attempting to set reserved bits in the PCC. Ignoring.\n"); + + value = value & 0x0fff; + PCC &= ~(0x0fff); + PCC |= (value << 0); + + /* TODO: Implement dsp56k timer and control glue */ +} + +/* Port C Data Direction Register (PCDDR) */ +void PCDDR_set(dsp56k_core* cpustate, UINT16 value) +{ + if (value & 0xf000) + logerror("Dsp56k : Attempting to set reserved bits in the PCDDR. Ignoring.\n"); + + value = value & 0x0fff; + PCDDR &= ~(0x0fff); + PCDDR |= (value << 0); + + /* TODO: Implement dsp56k io restrictions, etc. */ +} + +/* Port C Data Register (PCD) */ +void PCD_set(dsp56k_core* cpustate, UINT16 value) +{ + if (value & 0xf000) + logerror("Dsp56k : Attempting to set reserved bits in the PCD. Ignoring.\n"); + + /* TODO: Temporary */ + logerror("Dsp56k : Setting general output port C data to 0x%04x\n", value); + + value = value & 0x0fff; + PCD &= ~(0x0fff); + PCD |= (value << 0); +} + +void dsp56k_io_reset(dsp56k_core* cpustate) +{ + /* The BCR = 0x43ff */ + RH_bit_set(cpustate, 0); + BS_bit_set(cpustate, 1); + external_x_wait_states_set(cpustate, 0x1f); + external_p_wait_states_set(cpustate, 0x1f); +} + +} // namespace DSP56K + /* Work */ -static READ16_HANDLER( peripheral_register_r ) +READ16_HANDLER( peripheral_register_r ) { dsp56k_core* cpustate = get_safe_token(space->cpu); // (printf) logerror("Peripheral read 0x%04x\n", O2A(offset)); @@ -93,12 +553,12 @@ static READ16_HANDLER( peripheral_register_r ) // HTX/HRX: Host TX/RX Register case 0xffe5: // 5-5 - if (!HRDF_bit(cpustate)) + if (!DSP56K::HRDF_bit(cpustate)) return 0xbeef; else { UINT16 value = HRX; // TODO: Maybe not exactly right? Just being safe. - HRDF_bit_set(cpustate, 0); + DSP56K::HRDF_bit_set(cpustate, 0); return value; } break; @@ -164,7 +624,7 @@ static READ16_HANDLER( peripheral_register_r ) return dsp56k_peripheral_ram[offset]; } -static WRITE16_HANDLER( peripheral_register_w ) +WRITE16_HANDLER( peripheral_register_w ) { dsp56k_core* cpustate = get_safe_token(space->cpu); @@ -178,27 +638,27 @@ static WRITE16_HANDLER( peripheral_register_w ) { // Port B Control Register (PBC) case 0xffc0: - PBC_set(cpustate, data); + DSP56K::PBC_set(cpustate, data); break; // Port C Control Register (PCC) case 0xffc1: - PCC_set(cpustate, data); + DSP56K::PCC_set(cpustate, data); break; // Port B Data Direction Register (PBDDR) case 0xffc2: - PBDDR_set(cpustate, data); + DSP56K::PBDDR_set(cpustate, data); break; // Port C Data Direction Register (PCDDR) case 0xffc3: - PCDDR_set(cpustate, data); + DSP56K::PCDDR_set(cpustate, data); break; // HCR: Host Control Register case 0xffc4: - HCR_set(cpustate, data); + DSP56K::HCR_set(cpustate, data); break; // COCR @@ -231,22 +691,22 @@ static WRITE16_HANDLER( peripheral_register_w ) // BCR: Bus Control Register case 0xffde: - BCR_set(cpustate, data); + DSP56K::BCR_set(cpustate, data); break; // IPR: Interrupt Priority Register case 0xffdf: - IPR_set(cpustate, data); + DSP56K::IPR_set(cpustate, data); break; // Port B Data Register (PBD) case 0xffe2: - PBD_set(cpustate, data); + DSP56K::PBD_set(cpustate, data); break; // Port C Data Register (PCD) case 0xffe3: - PCD_set(cpustate, data); + DSP56K::PCD_set(cpustate, data); break; // HSR: Host Status Register @@ -255,7 +715,7 @@ static WRITE16_HANDLER( peripheral_register_w ) // HTX/HRX: Host TX/RX Register case 0xffe5: HTX = data; - HTDE_bit_set(cpustate, 0); // 5-5 + DSP56K::HTDE_bit_set(cpustate, 0); // 5-5 break; // COSR @@ -319,294 +779,6 @@ static WRITE16_HANDLER( peripheral_register_w ) } } -/*************************************************************************** - HOST INTERFACE -***************************************************************************/ -/***************/ -/* DSP56k SIDE */ -/***************/ -/************************************/ -/* Host Control Register (HCR) Bits */ -/************************************/ -static void HCR_set(dsp56k_core* cpustate, UINT16 value) -{ - HF3_bit_set (cpustate, (value & 0x0010) >> 4); - HF2_bit_set (cpustate, (value & 0x0008) >> 3); - HCIE_bit_set(cpustate, (value & 0x0004) >> 2); - HTIE_bit_set(cpustate, (value & 0x0002) >> 1); - HRIE_bit_set(cpustate, (value & 0x0001) >> 0); -} -//static UINT16 HF3_bit(dsp56k_core* cpustate) { return ((HCR & 0x0010) != 0); } -//static UINT16 HF2_bit(dsp56k_core* cpustate) { return ((HCR & 0x0008) != 0); } -static UINT16 HCIE_bit(dsp56k_core* cpustate) { return ((HCR & 0x0004) != 0); } -static UINT16 HTIE_bit(dsp56k_core* cpustate) { return ((HCR & 0x0002) != 0); } -static UINT16 HRIE_bit(dsp56k_core* cpustate) { return ((HCR & 0x0001) != 0); } - -static void HF3_bit_set(dsp56k_core* cpustate, UINT16 value) -{ - value = value & 0x01; - HCR &= ~(0x0010); - HCR |= (value << 4); - - HF3_bit_host_set(cpustate, value); -} -static void HF2_bit_set(dsp56k_core* cpustate, UINT16 value) -{ - value = value & 0x01; - HCR &= ~(0x0008); - HCR |= (value << 3); - - HF2_bit_host_set(cpustate, value); -} -static void HCIE_bit_set(dsp56k_core* cpustate, UINT16 value) -{ - value = value & 0x01; - HCR &= ~(0x0004); - HCR |= (value << 2); -} -static void HTIE_bit_set(dsp56k_core* cpustate, UINT16 value) -{ - value = value & 0x01; - HCR &= ~(0x0002); - HCR |= (value << 1); -} -static void HRIE_bit_set(dsp56k_core* cpustate, UINT16 value) -{ - value = value & 0x01; - HCR &= ~(0x0001); - HCR |= (value << 0); -} - -/***********************************/ -/* Host Status Register (HSR) Bits */ -/***********************************/ -//static UINT16 DMA_bit(dsp56k_core* cpustate) { return ((HSR & 0x0080) != 0); } -//static UINT16 HF1_bit(dsp56k_core* cpustate) { return ((HSR & 0x0010) != 0); } -//static UINT16 HF0_bit(dsp56k_core* cpustate) { return ((HSR & 0x0008) != 0); } -//static UINT16 HCP_bit(dsp56k_core* cpustate) { return ((HSR & 0x0004) != 0); } -static UINT16 HTDE_bit(dsp56k_core* cpustate) { return ((HSR & 0x0002) != 0); } -static UINT16 HRDF_bit(dsp56k_core* cpustate) { return ((HSR & 0x0001) != 0); } - -static void DMA_bit_set(dsp56k_core* cpustate, UINT16 value) -{ - value = value & 0x01; - HSR &= ~(0x0080); - HSR |= (value << 7); - // TODO: 5-12 When the DMA bit is set, the DMA mode is enabled by the Host Mode bits HM0 & HM1 -} -static void HF1_bit_set(dsp56k_core* cpustate, UINT16 value) -{ - value = value & 0x01; - HSR &= ~(0x0010); - HSR |= (value << 4); -} -static void HF0_bit_set(dsp56k_core* cpustate, UINT16 value) -{ - value = value & 0x01; - HSR &= ~(0x0008); - HSR |= (value << 3); -} -static void HCP_bit_set(dsp56k_core* cpustate, UINT16 value) -{ - value = value & 0x01; - HSR &= ~(0x0004); - HSR |= (value << 2); - - if (value && HCIE_bit(cpustate)) - dsp56k_add_pending_interrupt(cpustate, "Host Command"); -} -static void HTDE_bit_set(dsp56k_core* cpustate, UINT16 value) -{ - value = value & 0x01; - HSR &= ~(0x0002); - HSR |= (value << 1); - - // 5-10 If HTIE bit is set, whip out a Host Transmit Data interrupt - if (value && HTIE_bit(cpustate)) - dsp56k_add_pending_interrupt(cpustate, "Host Transmit Data"); - - // 5-5 If both me and RXDF are cleared, transmit data to the host - if (!value && !RXDF_bit(cpustate)) - dsp56k_host_interface_HTX_to_host(cpustate); -} -static void HRDF_bit_set(dsp56k_core* cpustate, UINT16 value) -{ - value = value & 0x01; - HSR &= ~(0x0001); - HSR |= (value << 0); - - // 5-10 If HRIE is set, whip out a Host Receive Data interrupt - if (value && HRIE_bit(cpustate)) - dsp56k_add_pending_interrupt(cpustate, "Host Receive Data"); - - // 5-5 If both me and TXDE are cleared, transmit data to the dsp56k - if (!value && !TXDE_bit(cpustate)) - dsp56k_host_interface_host_to_HTX(cpustate); -} - - - -/*************/ -/* HOST SIDE */ -/*************/ -/*****************************************/ -/* Interrupt Control Register (ICR) Bits */ -/*****************************************/ -static void ICR_set(dsp56k_core* cpustate, UINT8 value) -{ - HF1_bit_host_set(cpustate, (value & 0x10) >> 4); - HF0_bit_host_set(cpustate, (value & 0x08) >> 3); - TREQ_bit_set(cpustate, (value & 0x02) >> 1); - RREQ_bit_set(cpustate, (value & 0x01) >> 0); -} - -//static UINT8 INIT_bit(dsp56k_core* cpustate); #define x_initBIT ((dsp56k.HI.ICR & 0x0080) != 0) -//static UINT8 HM1_bit(dsp56k_core* cpustate); #define x_hm1BIT ((dsp56k.HI.ICR & 0x0040) != 0) -//static UINT8 HM0_bit(dsp56k_core* cpustate); #define x_hm0BIT ((dsp56k.HI.ICR & 0x0020) != 0) -//static UINT8 HF1_bit_host(dsp56k_core* cpustate); #define x_hf1BIT ((dsp56k.HI.ICR & 0x0010) != 0) -//static UINT8 HF0_bit_host(dsp56k_core* cpustate); #define x_hf0BIT ((dsp56k.HI.ICR & 0x0008) != 0) -//static UINT8 TREQ_bit(dsp56k_core* cpustate); #define x_treqBIT ((dsp56k.HI.ICR & 0x0002) != 0) -//static UINT8 RREQ_bit(dsp56k_core* cpustate); #define x_rreqBIT ((dsp56k.HI.ICR & 0x0001) != 0) - -//static void INIT_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_initBIT() (dsp56k.HI.ICR &= (~0x0080)) -//static void HM1_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_hm1BIT() (dsp56k.HI.ICR &= (~0x0040)) -//static void HM0_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_hm0BIT() (dsp56k.HI.ICR &= (~0x0020)) -static void HF1_bit_host_set(dsp56k_core* cpustate, UINT8 value) -{ - value = value & 0x01; - ICR &= ~(0x10); - ICR |= (value << 4); - - HF1_bit_set(cpustate, value); // 5-14 -} -static void HF0_bit_host_set(dsp56k_core* cpustate, UINT8 value) -{ - value = value & 0x01; - ICR &= ~(0x08); - ICR |= (value << 3); - - HF0_bit_set(cpustate, value); // 5-13 -} -static void TREQ_bit_set(dsp56k_core* cpustate, UINT8 value) -{ - value = value & 0x01; - ICR &= ~(0x02); - ICR |= (value << 1); -} -static void RREQ_bit_set(dsp56k_core* cpustate, UINT8 value) -{ - value = value & 0x01; - ICR &= ~(0x01); - ICR |= (value << 0); - - // 5-12 - if (value) - { - // TODO : HREQ_assert(); - } -} - - - -/**************************************/ -/* Command Vector Register (CVR) Bits */ -/**************************************/ -static UINT8 HV_bits(dsp56k_core* cpustate) { return (CVR & 0x1f); } - -static void CVR_set(dsp56k_core* cpustate, UINT8 value) -{ - /* A single, unified place to run all callbacks for each of the bits */ - HC_bit_set(cpustate, (value & 0x80) >> 7); - HV_bits_set(cpustate, (value & 0x1f)); -} - -static void HC_bit_set(dsp56k_core* cpustate, UINT8 value) -{ - value = value & 0x01; - CVR &= ~(0x80); - CVR |= (value << 7); - - HCP_bit_set(cpustate, value); // 5-9 & 5-11 -} -static void HV_bits_set(dsp56k_core* cpustate, UINT8 value) -{ - value = value & 0x1f; - CVR &= ~(0x1f); - CVR |= (value << 0); -} - - -/****************************************/ -/* Interrupt Status Register (ISR) Bits */ -/****************************************/ -static UINT8 TXDE_bit(dsp56k_core* cpustate) { return ((ISR & 0x0002) != 0); } -static UINT8 RXDF_bit(dsp56k_core* cpustate) { return ((ISR & 0x0001) != 0); } - -static void HF3_bit_host_set(dsp56k_core* cpustate, UINT8 value) -{ - value = value & 0x01; - ISR &= ~(0x0010); - ISR |= (value << 4); -} -static void HF2_bit_host_set(dsp56k_core* cpustate, UINT8 value) -{ - value = value & 0x01; - ISR &= ~(0x0008); - ISR |= (value << 3); -} - -static void TXDE_bit_set(dsp56k_core* cpustate, UINT8 value) -{ - value = value & 0x01; - ISR &= ~(0x0002); - ISR |= (value << 1); - - // If both me and the HRDF are cleared, transmit data to the dsp56k - if (!value && !HRDF_bit(cpustate)) - dsp56k_host_interface_host_to_HTX(cpustate); -} - -static void RXDF_bit_set(dsp56k_core* cpustate, UINT8 value) -{ - value = value & 0x01; - ISR &= ~(0x0001); - ISR |= (value << 0); - - // If both me and HTDE are cleared, transmit data to the host - if (!value && !HTDE_bit(cpustate)) - dsp56k_host_interface_HTX_to_host(cpustate); -} - - -// TODO: 5-11 What is the host processor Initialize function? - -static void dsp56k_host_interface_reset(dsp56k_core* cpustate) -{ - // Hook up the CPU-side pointers properly. - cpustate->HI.hcr = &dsp56k_peripheral_ram[A2O(0xffc4)]; - cpustate->HI.hsr = &dsp56k_peripheral_ram[A2O(0xffe4)]; - cpustate->HI.htrx = &dsp56k_peripheral_ram[A2O(0xffe5)]; - - // The Bootstrap hack is initialized to write to address 0x0000 - cpustate->HI.bootstrap_offset = 0x0000; - - /* HCR */ - HCR_set(cpustate, 0x0000); // 5-10 - - /* HSR */ - HRDF_bit_set(cpustate, 0); // 5-11 - HTDE_bit_set(cpustate, 1); // 5-11 - HCP_bit_set(cpustate, 0); // 5-11 - HF0_bit_set(cpustate, 0); // 5-12 - HF1_bit_set(cpustate, 0); // 5-12 - DMA_bit_set(cpustate, 0); // 5-12 - - /* CVR*/ - HV_bits_set(cpustate, 0x16); // 5-7 - HC_bit_set(cpustate, 0); // 5-9 - - /* TODO: ISR (at least) */ -} /* These two functions are exposed to the outside world */ /* They represent the host side of the dsp56k's host interface */ @@ -637,12 +809,12 @@ void dsp56k_host_interface_write(running_device* device, UINT8 offset, UINT8 dat break; } } - ICR_set(cpustate, data); + DSP56K::ICR_set(cpustate, data); break; // Command Vector Register (CVR) case 0x01: - CVR_set(cpustate, data); + DSP56K::CVR_set(cpustate, data); break; // Interrupt status register (ISR) - Read only! @@ -673,7 +845,7 @@ void dsp56k_host_interface_write(running_device* device, UINT8 offset, UINT8 dat break; /* Probably the right thing to do, given this is a hack */ } - if (TXDE_bit(cpustate)) // 5-5 + if (DSP56K::TXDE_bit(cpustate)) // 5-5 { TXH = data; } @@ -695,10 +867,10 @@ void dsp56k_host_interface_write(running_device* device, UINT8 offset, UINT8 dat break; /* Probably the right thing to do, given this is a hack */ } - if (TXDE_bit(cpustate)) // 5-5 + if (DSP56K::TXDE_bit(cpustate)) // 5-5 { TXL = data; - TXDE_bit_set(cpustate, 0); + DSP56K::TXDE_bit_set(cpustate, 0); } break; @@ -746,7 +918,7 @@ UINT8 dsp56k_host_interface_read(running_device* device, UINT8 offset) // Receive byte register - high byte (RXH) case 0x06: // 5-5 - if (!RXDF_bit(cpustate)) + if (!DSP56K::RXDF_bit(cpustate)) return 0xbf; else return RXH; @@ -755,12 +927,12 @@ UINT8 dsp56k_host_interface_read(running_device* device, UINT8 offset) // Receive byte register - low byte (RXL) case 0x07: // 5-5 - if (!RXDF_bit(cpustate)) + if (!DSP56K::RXDF_bit(cpustate)) return 0xbf; else { UINT8 value = RXL; // TODO: Maybe not exactly right? I'm just being safe. - RXDF_bit_set(cpustate, 0); + DSP56K::RXDF_bit_set(cpustate, 0); return value; } break; @@ -772,170 +944,11 @@ UINT8 dsp56k_host_interface_read(running_device* device, UINT8 offset) return 0xff; } -static void dsp56k_host_interface_HTX_to_host(dsp56k_core* cpustate) -{ - RXH = ((HTX & 0xff00) >> 8); - RXL = ((HTX & 0x00ff)); - RXDF_bit_set(cpustate, 1); - HTDE_bit_set(cpustate, 1); -} - -static void dsp56k_host_interface_host_to_HTX(dsp56k_core* cpustate) -{ - HRX &= 0x00ff; - HRX |= (TXH << 8); - HRX &= 0xff00; - HRX |= TXL; - TXDE_bit_set(cpustate, 1); - HRDF_bit_set(cpustate, 1); -} - - -/*************************************************************************** - I/O INTERFACE -***************************************************************************/ -/* BCR */ -static void BCR_set(dsp56k_core* cpustate, UINT16 value) -{ - RH_bit_set(cpustate, (value & 0x8000) >> 15); - BS_bit_set(cpustate, (value & 0x4000) >> 14); - external_x_wait_states_set(cpustate, (value & 0x03e0) >> 5); - external_p_wait_states_set(cpustate, (value & 0x001f) >> 0); -} - -//static UINT16 RH_bit(dsp56k_core* cpustate); -//static UINT16 BS_bit(dsp56k_core* cpustate); -//static UINT16 external_x_wait_states(dsp56k_core* cpustate); -//static UINT16 external_p_wait_states(dsp56k_core* cpustate); - -static void RH_bit_set(dsp56k_core* cpustate, UINT16 value) -{ - value = value & 0x0001; - BCR &= ~(0x8000); - BCR |= (value << 15); - - // TODO: 4-6 Assert BR pin? -} -static void BS_bit_set(dsp56k_core* cpustate, UINT16 value) -{ - value = value & 0x0001; - BCR &= ~(0x4000); - BCR |= (value << 14); - - // TODO: 4-6 Respond to BR pin? -} -static void external_x_wait_states_set(dsp56k_core* cpustate, UINT16 value) -{ - value = value & 0x001f; - BCR &= ~(0x03e0); - BCR |= (value << 5); -} -static void external_p_wait_states_set(dsp56k_core* cpustate, UINT16 value) -{ - value = value & 0x001f; - BCR &= ~(0x001f); - BCR |= (value << 0); -} - - -/* Port B Control Register PBC */ -static void PBC_set(dsp56k_core* cpustate, UINT16 value) -{ - if (value & 0xfffe) - logerror("Dsp56k : Attempting to set reserved bits in the PBC. Ignoring.\n"); - - value = value & 0x0001; - PBC &= ~(0x0001); - PBC |= (value << 0); -} - -#ifdef UNUSED_FUNCTION -static int host_interface_active(dsp56k_core* cpustate) -{ - /* The host interface is active if the 0th bit in the PBC is set */ - return PBC & 0x0001; -} -#endif - -/* Port B Data Direction Register (PBDDR) */ -static void PBDDR_set(dsp56k_core* cpustate, UINT16 value) -{ - if (value & 0x8000) - logerror("Dsp56k : Attempting to set reserved bits in the PBDDR. Ignoring.\n"); - - value = value & 0x7fff; - PBDDR &= ~(0x7fff); - PBDDR |= (value << 0); - - /* TODO: Implement dsp56k io restrictions, etc. */ -} - -/* Port B Data Register (PBD) */ -static void PBD_set(dsp56k_core* cpustate, UINT16 value) -{ - if (value & 0x8000) - logerror("Dsp56k : Attempting to set reserved bits in the PBD. Ignoring.\n"); - - value = value & 0x7fff; - PBD &= ~(0x7fff); - PBD |= (value << 0); - - /* TODO: Implement dsp56k io restrictions, etc. */ -} - -/* Port C Control Register (PCC) */ -static void PCC_set(dsp56k_core* cpustate, UINT16 value) -{ - if (value & 0xf000) - logerror("Dsp56k : Attempting to set reserved bits in the PCC. Ignoring.\n"); - - value = value & 0x0fff; - PCC &= ~(0x0fff); - PCC |= (value << 0); - - /* TODO: Implement dsp56k timer and control glue */ -} - -/* Port C Data Direction Register (PCDDR) */ -static void PCDDR_set(dsp56k_core* cpustate, UINT16 value) -{ - if (value & 0xf000) - logerror("Dsp56k : Attempting to set reserved bits in the PCDDR. Ignoring.\n"); - - value = value & 0x0fff; - PCDDR &= ~(0x0fff); - PCDDR |= (value << 0); - - /* TODO: Implement dsp56k io restrictions, etc. */ -} - -/* Port C Data Register (PCD) */ -static void PCD_set(dsp56k_core* cpustate, UINT16 value) -{ - if (value & 0xf000) - logerror("Dsp56k : Attempting to set reserved bits in the PCD. Ignoring.\n"); - - /* TODO: Temporary */ - logerror("Dsp56k : Setting general output port C data to 0x%04x\n", value); - - value = value & 0x0fff; - PCD &= ~(0x0fff); - PCD |= (value << 0); -} - -static void dsp56k_io_reset(dsp56k_core* cpustate) -{ - /* The BCR = 0x43ff */ - RH_bit_set(cpustate, 0); - BS_bit_set(cpustate, 1); - external_x_wait_states_set(cpustate, 0x1f); - external_p_wait_states_set(cpustate, 0x1f); -} - - /* MISC*/ UINT16 dsp56k_get_peripheral_memory(running_device* device, UINT16 addr) { // TODO // THIS COMES BACK dsp56k_core* cpustate = get_safe_token(device); return dsp56k_peripheral_ram[A2O(addr)]; } + + diff --git a/src/emu/cpu/dsp56k/dsp56mem.h b/src/emu/cpu/dsp56k/dsp56mem.h new file mode 100644 index 00000000000..6cd6d65b3ef --- /dev/null +++ b/src/emu/cpu/dsp56k/dsp56mem.h @@ -0,0 +1,243 @@ +#ifndef __DSP56_MEM_H__ +#define __DSP56_MEM_H__ + +#include "dsp56k.h" + +namespace DSP56K +{ + +/*************************************************************************** + MEMORY +***************************************************************************/ +void mem_reset(dsp56k_core* cpustate); + +// Adjusts the documented address to match the offset in peripheral RAM +#define A2O(a) (a-0xffc0) + +// Adjusts the offset in peripheral RAM to match the documented address +#define O2A(a) (a+0xffc0) + +// The memory 'registers' +#define PBC (dsp56k_peripheral_ram[A2O(0xffc0)]) +#define PCC (dsp56k_peripheral_ram[A2O(0xffc1)]) +#define PBDDR (dsp56k_peripheral_ram[A2O(0xffc2)]) +#define PCDDR (dsp56k_peripheral_ram[A2O(0xffc3)]) +#define HCR (dsp56k_peripheral_ram[A2O(0xffc4)]) +#define COCR (dsp56k_peripheral_ram[A2O(0xffc8)]) +#define CRASSI0 (dsp56k_peripheral_ram[A2O(0xffd0)]) +#define CRBSSI0 (dsp56k_peripheral_ram[A2O(0xffd1)]) +#define CRASSI1 (dsp56k_peripheral_ram[A2O(0xffd8)]) +#define CRBSSI1 (dsp56k_peripheral_ram[A2O(0xffd9)]) +#define PLCR (dsp56k_peripheral_ram[A2O(0xffdc)]) +#define BCR (dsp56k_peripheral_ram[A2O(0xffde)]) +#define IPR (dsp56k_peripheral_ram[A2O(0xffdf)]) +#define PBD (dsp56k_peripheral_ram[A2O(0xffe2)]) +#define PCD (dsp56k_peripheral_ram[A2O(0xffe3)]) +#define HSR (dsp56k_peripheral_ram[A2O(0xffe4)]) +#define HTXHRX (dsp56k_peripheral_ram[A2O(0xffe5)]) +#define COSR (dsp56k_peripheral_ram[A2O(0xffe8)]) +#define CRXCTX (dsp56k_peripheral_ram[A2O(0xffe9)]) +#define TCR (dsp56k_peripheral_ram[A2O(0xffec)]) +#define TCTR (dsp56k_peripheral_ram[A2O(0xffed)]) +#define TCPR (dsp56k_peripheral_ram[A2O(0xffee)]) +#define TPR (dsp56k_peripheral_ram[A2O(0xffef)]) +#define TSRSSI0 (dsp56k_peripheral_ram[A2O(0xfff0)]) +#define TRXSSI0 (dsp56k_peripheral_ram[A2O(0xfff1)]) +#define RSMA0 (dsp56k_peripheral_ram[A2O(0xfff2)]) +#define RSMB0 (dsp56k_peripheral_ram[A2O(0xfff3)]) +#define TSMA0 (dsp56k_peripheral_ram[A2O(0xfff4)]) +#define TSMB0 (dsp56k_peripheral_ram[A2O(0xfff5)]) +#define TSRSSI1 (dsp56k_peripheral_ram[A2O(0xfff8)]) +#define TRXSSI1 (dsp56k_peripheral_ram[A2O(0xfff9)]) +#define RSMA1 (dsp56k_peripheral_ram[A2O(0xfffa)]) +#define RSMB1 (dsp56k_peripheral_ram[A2O(0xfffb)]) +#define TSMA1 (dsp56k_peripheral_ram[A2O(0xfffc)]) +#define TSMB1 (dsp56k_peripheral_ram[A2O(0xfffd)]) + +/* Interrupt priority register (IPR) bits */ +void IPR_set(dsp56k_core* cpustate, UINT16 value); + +/* A return value of -1 means disabled */ +INT8 irqa_ipl(dsp56k_core* cpustate); +INT8 irqb_ipl(dsp56k_core* cpustate); +UINT8 irqa_trigger(dsp56k_core* cpustate); +UINT8 irqb_trigger(dsp56k_core* cpustate); + +INT8 codec_ipl(dsp56k_core* cpustate); +INT8 host_ipl(dsp56k_core* cpustate); +INT8 ssi0_ipl(dsp56k_core* cpustate); +INT8 ssi1_ipl(dsp56k_core* cpustate); +INT8 tm_ipl(dsp56k_core* cpustate); + + +/*************************************************************************** + HOST INTERFACE +***************************************************************************/ +void dsp56k_host_interface_reset(dsp56k_core* cpustate); +#define HTX (HTXHRX) +#define HRX (HTXHRX) + +#define ICR (cpustate->HI.icr) +#define CVR (cpustate->HI.cvr) +#define ISR (cpustate->HI.isr) +#define IVR (cpustate->HI.ivr) +#define TXH (cpustate->HI.trxh) +#define TXL (cpustate->HI.trxl) +#define RXH (cpustate->HI.trxh) +#define RXL (cpustate->HI.trxl) + +/***************/ +/* DSP56k SIDE */ +/***************/ +/* Host Control Register (HCR) Bits */ +void HCR_set(dsp56k_core* cpustate, UINT16 value); + +//UINT16 HF3_bit(dsp56k_core* cpustate); #define hf3BIT ((HCR & 0x0010) != 0) +//UINT16 HF2_bit(dsp56k_core* cpustate); #define hf2BIT ((HCR & 0x0008) != 0) +UINT16 HCIE_bit(dsp56k_core* cpustate); +UINT16 HTIE_bit(dsp56k_core* cpustate); +UINT16 HRIE_bit(dsp56k_core* cpustate); + +void HF3_bit_set(dsp56k_core* cpustate, UINT16 value); +void HF2_bit_set(dsp56k_core* cpustate, UINT16 value); +void HCIE_bit_set(dsp56k_core* cpustate, UINT16 value); +void HTIE_bit_set(dsp56k_core* cpustate, UINT16 value); +void HRIE_bit_set(dsp56k_core* cpustate, UINT16 value); + +/* Host Status Register (HSR) Bits */ +//void HSR_set(dsp56k_core* cpustate, UINT16 value); + +//UINT16 DMA_bit(dsp56k_core* cpustate); #define dmaBIT ((HSR & 0x0080) != 0) +//UINT16 HF1_bit(dsp56k_core* cpustate); #define hf1BIT ((HSR & 0x0010) != 0) +//UINT16 HF0_bit(dsp56k_core* cpustate); #define hf0BIT ((HSR & 0x0008) != 0) +//UINT16 HCP_bit(dsp56k_core* cpustate); #define hcpBIT ((HSR & 0x0004) != 0) +UINT16 HTDE_bit(dsp56k_core* cpustate); +UINT16 HRDF_bit(dsp56k_core* cpustate); + +void DMA_bit_set(dsp56k_core* cpustate, UINT16 value); +void HF1_bit_set(dsp56k_core* cpustate, UINT16 value); +void HF0_bit_set(dsp56k_core* cpustate, UINT16 value); +void HCP_bit_set(dsp56k_core* cpustate, UINT16 value); +void HTDE_bit_set(dsp56k_core* cpustate, UINT16 value); +void HRDF_bit_set(dsp56k_core* cpustate, UINT16 value); + +/*************/ +/* HOST SIDE */ +/*************/ +/* Interrupt Control Register (ICR) Bits */ +void ICR_set(dsp56k_core* cpustate, UINT8 value); + +//UINT8 INIT_bit(dsp56k_core* cpustate); #define x_initBIT ((dsp56k.HI.ICR & 0x0080) != 0) +//UINT8 HM1_bit(dsp56k_core* cpustate); #define x_hm1BIT ((dsp56k.HI.ICR & 0x0040) != 0) +//UINT8 HM0_bit(dsp56k_core* cpustate); #define x_hm0BIT ((dsp56k.HI.ICR & 0x0020) != 0) +//UINT8 HF1_bit_host(dsp56k_core* cpustate); #define x_hf1BIT ((dsp56k.HI.ICR & 0x0010) != 0) +//UINT8 HF0_bit_host(dsp56k_core* cpustate); #define x_hf0BIT ((dsp56k.HI.ICR & 0x0008) != 0) +//UINT8 TREQ_bit(dsp56k_core* cpustate); #define x_treqBIT ((dsp56k.HI.ICR & 0x0002) != 0) +//UINT8 RREQ_bit(dsp56k_core* cpustate); #define x_rreqBIT ((dsp56k.HI.ICR & 0x0001) != 0) + +//void INIT_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_initBIT() (dsp56k.HI.ICR &= (~0x0080)) +//void HM1_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_hm1BIT() (dsp56k.HI.ICR &= (~0x0040)) +//void HM0_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_hm0BIT() (dsp56k.HI.ICR &= (~0x0020)) +void HF1_bit_host_set(dsp56k_core* cpustate, UINT8 value); +void HF0_bit_host_set(dsp56k_core* cpustate, UINT8 value); +void TREQ_bit_set(dsp56k_core* cpustate, UINT8 value); +void RREQ_bit_set(dsp56k_core* cpustate, UINT8 value); + +/* Command Vector Register (CVR) Bits */ +void CVR_set(dsp56k_core* cpustate, UINT8 value); + +//UINT8 HC_bit(); +UINT8 HV_bits(dsp56k_core* cpustate); + +void HC_bit_set(dsp56k_core* cpustate, UINT8 value); +void HV_bits_set(dsp56k_core* cpustate, UINT8 value); + +/* Interrupt Status Register (ISR) Bits */ +// void ISR_set(dsp56k_core* cpustate, UINT8 value); + +//UINT8 HREQ_bit(dsp56k_core* cpustate); #define x_hreqBIT ((dsp56k.HI.ISR & 0x0080) != 0) +//UINT8 DMA_bit(dsp56k_core* cpustate); #define x_dmaBIT ((dsp56k.HI.ISR & 0x0040) != 0) +//UINT8 HF3_bit_host(dsp56k_core* cpustate); #define x_hf3BIT ((dsp56k.HI.ISR & 0x0010) != 0) +//UINT8 HF2_bit_host(dsp56k_core* cpustate); #define x_hf2BIT ((dsp56k.HI.ISR & 0x0008) != 0) +//UINT8 TRDY_bit(dsp56k_core* cpustate); #define x_trdyBIT ((dsp56k.HI.ISR & 0x0004) != 0) +UINT8 TXDE_bit(dsp56k_core* cpustate); +UINT8 RXDF_bit(dsp56k_core* cpustate); + +//void HREQ_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_hreqBIT() (dsp56k.HI.ISR &= (~0x0080)) +//void DMA_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_dmaBIT() (dsp56k.HI.ISR &= (~0x0040)) +void HF3_bit_host_set(dsp56k_core* cpustate, UINT8 value); +void HF2_bit_host_set(dsp56k_core* cpustate, UINT8 value); +//void TRDY_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_trdyBIT() (dsp56k.HI.ISR &= (~0x0004)) +void TXDE_bit_set(dsp56k_core* cpustate, UINT8 value); +void RXDF_bit_set(dsp56k_core* cpustate, UINT8 value); + +/* Interrupt Vector Register (IVR) Bits */ +//void IVR_set(dsp56k_core* cpustate, UINT8 value); + +//UINT8 IV7_bit(dsp56k_core* cpustate); +//UINT8 IV6_bit(dsp56k_core* cpustate); +//UINT8 IV5_bit(dsp56k_core* cpustate); +//UINT8 IV4_bit(dsp56k_core* cpustate); +//UINT8 IV3_bit(dsp56k_core* cpustate); +//UINT8 IV2_bit(dsp56k_core* cpustate); +//UINT8 IV1_bit(dsp56k_core* cpustate); +//UINT8 IV0_bit(dsp56k_core* cpustate); + +//void IV7_bit_set(dsp56k_core* cpustate, UINT8 value); +//void IV6_bit_set(dsp56k_core* cpustate, UINT8 value); +//void IV5_bit_set(dsp56k_core* cpustate, UINT8 value); +//void IV4_bit_set(dsp56k_core* cpustate, UINT8 value); +//void IV3_bit_set(dsp56k_core* cpustate, UINT8 value); +//void IV2_bit_set(dsp56k_core* cpustate, UINT8 value); +//void IV1_bit_set(dsp56k_core* cpustate, UINT8 value); +//void IV0_bit_set(dsp56k_core* cpustate, UINT8 value); + + +/* PROTOTYPES */ +void dsp56k_host_interface_HTX_to_host(dsp56k_core* cpustate); +void dsp56k_host_interface_host_to_HTX(dsp56k_core* cpustate); + + +/*************************************************************************** + I/O INTERFACE +***************************************************************************/ +void dsp56k_io_reset(dsp56k_core* cpustate); + +/* Port A Bus Control Register (BCR) */ +void BCR_set(dsp56k_core* cpustate, UINT16 value); + +//UINT16 RH_bit(dsp56k_core* cpustate); +//UINT16 BS_bit(dsp56k_core* cpustate); +//UINT16 external_x_wait_states(dsp56k_core* cpustate); +//UINT16 external_p_wait_states(dsp56k_core* cpustate); + +void RH_bit_set(dsp56k_core* cpustate, UINT16 value); +void BS_bit_set(dsp56k_core* cpustate, UINT16 value); +void external_x_wait_states_set(dsp56k_core* cpustate, UINT16 value); +void external_p_wait_states_set(dsp56k_core* cpustate, UINT16 value); + +/* Port B Control Register (PBC) */ +void PBC_set(dsp56k_core* cpustate, UINT16 value); +//int host_interface_active(dsp56k_core* cpustate); + +/* Port B Data Direction Register (PBDDR) */ +void PBDDR_set(dsp56k_core* cpustate, UINT16 value); + +/* Port B Data Register (PBD) */ +void PBD_set(dsp56k_core* cpustate, UINT16 value); + +/* Port C Control Register (PCC) */ +void PCC_set(dsp56k_core* cpustate, UINT16 value); + +/* Port C Data Direction Register (PCDDR) */ +void PCDDR_set(dsp56k_core* cpustate, UINT16 value); + +/* Port C Dtaa Register (PCD) */ +void PCD_set(dsp56k_core* cpustate, UINT16 value); + +} // namespace DSP56K + +READ16_HANDLER( peripheral_register_r ); +WRITE16_HANDLER( peripheral_register_w ); + +#endif diff --git a/src/emu/cpu/dsp56k/dsp56ops.c b/src/emu/cpu/dsp56k/dsp56ops.c index a3dd9202a95..3139cf934b6 100644 --- a/src/emu/cpu/dsp56k/dsp56ops.c +++ b/src/emu/cpu/dsp56k/dsp56ops.c @@ -44,7 +44,6 @@ typedef struct _typed_pointer typed_pointer; #define ADDRESS(X) (X<<1) #define BITS(CUR,MASK) (Dsp56kOpMask(CUR,MASK)) - /*********************/ /* Opcode prototypes */ /*********************/ @@ -240,8 +239,8 @@ static void execute_one(dsp56k_core* cpustate) UINT8 cycle_count = 0; /* For MAME */ + cpustate->op = ROPCODE(ADDRESS(PC)); debugger_instruction_hook(cpustate->device, PC); - OP = ROPCODE(ADDRESS(PC)); /* The words we're going to be working with */ op = ROPCODE(ADDRESS(PC)); diff --git a/src/emu/cpu/dsp56k/dsp56pcu.c b/src/emu/cpu/dsp56k/dsp56pcu.c index 48011b35042..3ae235ed0ad 100644 --- a/src/emu/cpu/dsp56k/dsp56pcu.c +++ b/src/emu/cpu/dsp56k/dsp56pcu.c @@ -1,3 +1,12 @@ +#include "dsp56pcu.h" +#include "dsp56mem.h" + +extern UINT16 *dsp56k_peripheral_ram; +extern UINT16 *dsp56k_program_ram; + +namespace DSP56K +{ + /* ************************************************************************* */ /* Status Register */ /* ************************************************************************* */ @@ -7,34 +16,34 @@ /* |-------------------------------------| |-------------------------------| */ /* */ /* ************************************************************************* */ -static UINT8 LF_bit(dsp56k_core* cpustate) { return (SR & 0x8000) >> 15; } -static UINT8 FV_bit(dsp56k_core* cpustate) { return (SR & 0x4000) >> 14; } -// static UINT8 S_bits(dsp56k_core* cpustate) { return (SR & 0x0c00) >> 10; } -static UINT8 I_bits(dsp56k_core* cpustate) { return (SR & 0x0300) >> 8; } -static UINT8 S_bit (dsp56k_core* cpustate) { return (SR & 0x0080) >> 7; } -static UINT8 L_bit (dsp56k_core* cpustate) { return (SR & 0x0040) >> 6; } -static UINT8 E_bit (dsp56k_core* cpustate) { return (SR & 0x0020) >> 5; } -static UINT8 U_bit (dsp56k_core* cpustate) { return (SR & 0x0010) >> 4; } -static UINT8 N_bit (dsp56k_core* cpustate) { return (SR & 0x0008) >> 3; } -static UINT8 Z_bit (dsp56k_core* cpustate) { return (SR & 0x0004) >> 2; } -static UINT8 V_bit (dsp56k_core* cpustate) { return (SR & 0x0002) >> 1; } -static UINT8 C_bit (dsp56k_core* cpustate) { return (SR & 0x0001) >> 0; } +UINT8 LF_bit(dsp56k_core* cpustate) { return (SR & 0x8000) >> 15; } +UINT8 FV_bit(dsp56k_core* cpustate) { return (SR & 0x4000) >> 14; } +// UINT8 S_bits(dsp56k_core* cpustate) { return (SR & 0x0c00) >> 10; } +UINT8 I_bits(dsp56k_core* cpustate) { return (SR & 0x0300) >> 8; } +UINT8 S_bit (dsp56k_core* cpustate) { return (SR & 0x0080) >> 7; } +UINT8 L_bit (dsp56k_core* cpustate) { return (SR & 0x0040) >> 6; } +UINT8 E_bit (dsp56k_core* cpustate) { return (SR & 0x0020) >> 5; } +UINT8 U_bit (dsp56k_core* cpustate) { return (SR & 0x0010) >> 4; } +UINT8 N_bit (dsp56k_core* cpustate) { return (SR & 0x0008) >> 3; } +UINT8 Z_bit (dsp56k_core* cpustate) { return (SR & 0x0004) >> 2; } +UINT8 V_bit (dsp56k_core* cpustate) { return (SR & 0x0002) >> 1; } +UINT8 C_bit (dsp56k_core* cpustate) { return (SR & 0x0001) >> 0; } /* MR setters */ -static void LF_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x8000); else (SR &= (~0x8000)); } -static void FV_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x4000); else (SR &= (~0x4000)); } -static void S_bits_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x03; SR &= ~(0x0c00); SR |= (value << 10); } -static void I_bits_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x03; SR &= ~(0x0300); SR |= (value << 8); } +void LF_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x8000); else (SR &= (~0x8000)); } +void FV_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x4000); else (SR &= (~0x4000)); } +void S_bits_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x03; SR &= ~(0x0c00); SR |= (value << 10); } +void I_bits_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x03; SR &= ~(0x0300); SR |= (value << 8); } /* CCR setters */ -static void S_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0080); else (SR &= (~0x0080)); } -static void L_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0040); else (SR &= (~0x0040)); } -static void E_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0020); else (SR &= (~0x0020)); } -static void U_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0010); else (SR &= (~0x0010)); } -static void N_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0008); else (SR &= (~0x0008)); } -static void Z_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0004); else (SR &= (~0x0004)); } -static void V_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0002); else (SR &= (~0x0002)); } -static void C_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0001); else (SR &= (~0x0001)); } +void S_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0080); else (SR &= (~0x0080)); } +void L_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0040); else (SR &= (~0x0040)); } +void E_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0020); else (SR &= (~0x0020)); } +void U_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0010); else (SR &= (~0x0010)); } +void N_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0008); else (SR &= (~0x0008)); } +void Z_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0004); else (SR &= (~0x0004)); } +void V_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0002); else (SR &= (~0x0002)); } +void C_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0001); else (SR &= (~0x0001)); } @@ -47,23 +56,23 @@ static void C_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x /* |---------------------------------------------------------------------| */ /* */ /* ************************************************************************* */ -// static UINT8 CD_bit(dsp56k_core* cpustate) { return ((OMR & 0x0080) != 0); } -// static UINT8 SD_bit(dsp56k_core* cpustate) { return ((OMR & 0x0040) != 0); } -// static UINT8 R_bit(dsp56k_core* cpustate) { return ((OMR & 0x0020) != 0); } -// static UINT8 SA_bit(dsp56k_core* cpustate) { return ((OMR & 0x0010) != 0); } -// static UINT8 MC_bit(dsp56k_core* cpustate) { return ((OMR & 0x0004) != 0); } -static UINT8 MB_bit(dsp56k_core* cpustate) { return ((OMR & 0x0002) != 0); } -static UINT8 MA_bit(dsp56k_core* cpustate) { return ((OMR & 0x0001) != 0); } +// UINT8 CD_bit(dsp56k_core* cpustate) { return ((OMR & 0x0080) != 0); } +// UINT8 SD_bit(dsp56k_core* cpustate) { return ((OMR & 0x0040) != 0); } +// UINT8 R_bit(dsp56k_core* cpustate) { return ((OMR & 0x0020) != 0); } +// UINT8 SA_bit(dsp56k_core* cpustate) { return ((OMR & 0x0010) != 0); } +// UINT8 MC_bit(dsp56k_core* cpustate) { return ((OMR & 0x0004) != 0); } +UINT8 MB_bit(dsp56k_core* cpustate) { return ((OMR & 0x0002) != 0); } +UINT8 MA_bit(dsp56k_core* cpustate) { return ((OMR & 0x0001) != 0); } -static void CD_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0080); else (OMR &= (~0x0080)); } -static void SD_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0040); else (OMR &= (~0x0040)); } -static void R_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0020); else (OMR &= (~0x0020)); } -static void SA_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0010); else (OMR &= (~0x0010)); } -static void MC_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0004); else (OMR &= (~0x0004)); } -static void MB_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0002); else (OMR &= (~0x0002)); } -static void MA_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0001); else (OMR &= (~0x0001)); } +void CD_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0080); else (OMR &= (~0x0080)); } +void SD_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0040); else (OMR &= (~0x0040)); } +void R_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0020); else (OMR &= (~0x0020)); } +void SA_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0010); else (OMR &= (~0x0010)); } +void MC_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0004); else (OMR &= (~0x0004)); } +void MB_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0002); else (OMR &= (~0x0002)); } +void MA_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0001); else (OMR &= (~0x0001)); } -static UINT8 dsp56k_operating_mode(dsp56k_core* cpustate) +UINT8 dsp56k_operating_mode(dsp56k_core* cpustate) { return ((MB_bit(cpustate) << 1) | MA_bit(cpustate)); } @@ -79,18 +88,18 @@ static UINT8 dsp56k_operating_mode(dsp56k_core* cpustate) /* |---------------------------------------------------------------------| */ /* */ /* ************************************************************************* */ -static UINT8 UF_bit(dsp56k_core* cpustate) { return ((SP & 0x0020) != 0); } -static UINT8 SE_bit(dsp56k_core* cpustate) { return ((SP & 0x0010) != 0); } +UINT8 UF_bit(dsp56k_core* cpustate) { return ((SP & 0x0020) != 0); } +UINT8 SE_bit(dsp56k_core* cpustate) { return ((SP & 0x0010) != 0); } -//static void UF_bit_set(dsp56k_core* cpustate, UINT8 value) {}; -//static void SE_bit_set(dsp56k_core* cpustate, UINT8 value) {}; +//void UF_bit_set(dsp56k_core* cpustate, UINT8 value) {}; +//void SE_bit_set(dsp56k_core* cpustate, UINT8 value) {}; /*************************************************************************** INITIALIZATION AND RESET ***************************************************************************/ -static void pcu_init(dsp56k_core* cpustate, running_device *device) +void pcu_init(dsp56k_core* cpustate, running_device *device) { /* Init the irq table */ dsp56k_irq_table_init(); @@ -107,7 +116,7 @@ static void pcu_init(dsp56k_core* cpustate, running_device *device) state_save_register_device_item(device, 0, cpustate->PCU.reset_vector); } -static void pcu_reset(dsp56k_core* cpustate) +void pcu_reset(dsp56k_core* cpustate) { int i; @@ -236,10 +245,10 @@ typedef struct char irq_source[128]; } dsp56k_irq_data; -static dsp56k_irq_data dsp56k_interrupt_sources[32]; +dsp56k_irq_data dsp56k_interrupt_sources[32]; /* TODO: Figure out how to switch on level versus edge-triggered. */ -static void pcu_service_interrupts(dsp56k_core* cpustate) +void pcu_service_interrupts(dsp56k_core* cpustate) { int i; @@ -292,7 +301,7 @@ static void pcu_service_interrupts(dsp56k_core* cpustate) /* Register an interrupt */ -static void dsp56k_add_pending_interrupt(dsp56k_core* cpustate, const char* name) +void dsp56k_add_pending_interrupt(dsp56k_core* cpustate, const char* name) { int i; int irq_index = dsp56k_get_irq_index_by_tag(name); @@ -308,14 +317,14 @@ static void dsp56k_add_pending_interrupt(dsp56k_core* cpustate, const char* name } /* Utility function to construct IRQ table */ -static void dsp56k_set_irq_source(UINT8 irq_num, UINT16 iv, const char* source) +void dsp56k_set_irq_source(UINT8 irq_num, UINT16 iv, const char* source) { dsp56k_interrupt_sources[irq_num].irq_vector = iv; strcpy(dsp56k_interrupt_sources[irq_num].irq_source, source); } /* Construct a table containing pertient IRQ information */ -static void dsp56k_irq_table_init(void) +void dsp56k_irq_table_init(void) { /* 1-14 + 1-18 */ /* TODO: Cull host command stuff appropriately */ @@ -355,7 +364,7 @@ static void dsp56k_irq_table_init(void) } /* Clear all entries from the pending table */ -static void dsp56k_clear_pending_interrupts(dsp56k_core* cpustate) +void dsp56k_clear_pending_interrupts(dsp56k_core* cpustate) { int i; for (i = 0; i < 32; i++) @@ -365,7 +374,7 @@ static void dsp56k_clear_pending_interrupts(dsp56k_core* cpustate) } /* Recover number of pending irqs */ -static int dsp56k_count_pending_interrupts(dsp56k_core* cpustate) +int dsp56k_count_pending_interrupts(dsp56k_core* cpustate) { int numI = 0; while (cpustate->PCU.pending_interrupts[numI] != -1) @@ -377,7 +386,7 @@ static int dsp56k_count_pending_interrupts(dsp56k_core* cpustate) } /* Sort the pending irqs by priority */ -static void dsp56k_sort_pending_interrupts(dsp56k_core* cpustate, int num) +void dsp56k_sort_pending_interrupts(dsp56k_core* cpustate, int num) { int i, j; @@ -414,7 +423,7 @@ static void dsp56k_sort_pending_interrupts(dsp56k_core* cpustate, int num) } /* Given an index into the irq table, return the interrupt's current priority */ -static INT8 dsp56k_get_irq_priority(dsp56k_core* cpustate, int index) +INT8 dsp56k_get_irq_priority(dsp56k_core* cpustate, int index) { /* 1-12 */ switch (index) @@ -462,7 +471,7 @@ static INT8 dsp56k_get_irq_priority(dsp56k_core* cpustate, int index) } /* Given an IRQ name, return its index in the irq table */ -static int dsp56k_get_irq_index_by_tag(const char* tag) +int dsp56k_get_irq_index_by_tag(const char* tag) { int i; for (i = 0; i < 32; i++) @@ -476,3 +485,5 @@ static int dsp56k_get_irq_index_by_tag(const char* tag) fatalerror("DSP56K ERROR : IRQ TAG specified incorrectly (get_vector_by_tag) : %s.\n", tag); return -1; } + +} // namespace DSP56K diff --git a/src/emu/cpu/dsp56k/dsp56pcu.h b/src/emu/cpu/dsp56k/dsp56pcu.h new file mode 100644 index 00000000000..ed9eca416fa --- /dev/null +++ b/src/emu/cpu/dsp56k/dsp56pcu.h @@ -0,0 +1,149 @@ +#ifndef __DSP56_PCU_H__ +#define __DSP56_PCU_H__ + +#include "dsp56k.h" + +namespace DSP56K +{ + +/*************************************************************************** + PCU +***************************************************************************/ +void pcu_reset(dsp56k_core* cpustate); +void pcu_init(dsp56k_core* cpustate, running_device *device); +#define PC (cpustate->PCU.pc) +#define LA (cpustate->PCU.la) +#define LC (cpustate->PCU.lc) +#define SR (cpustate->PCU.sr) +#define OMR (cpustate->PCU.omr) +#define SP (cpustate->PCU.sp) +#define SS (cpustate->PCU.ss) + +#define SSH (SS[SP].w.h) +#define SSL (SS[SP].w.l) + +#define ST0 (SS[0].d) +#define ST1 (SS[1].d) +#define ST2 (SS[2].d) +#define ST3 (SS[3].d) +#define ST4 (SS[4].d) +#define ST5 (SS[5].d) +#define ST6 (SS[6].d) +#define ST7 (SS[7].d) +#define ST8 (SS[8].d) +#define ST9 (SS[9].d) +#define ST10 (SS[10].d) +#define ST11 (SS[11].d) +#define ST12 (SS[12].d) +#define ST13 (SS[13].d) +#define ST14 (SS[14].d) +#define ST15 (SS[15].d) + +/* STATUS REGISTER (SR) BITS (1-25) */ +/* MR */ +UINT8 LF_bit(dsp56k_core* cpustate); +UINT8 FV_bit(dsp56k_core* cpustate); +//UINT8 S_bits(dsp56k_core* cpustate); +UINT8 I_bits(dsp56k_core* cpustate); + +/* CCR - with macros for easy access */ +#define S() (S_bit(cpustate)) +UINT8 S_bit(dsp56k_core* cpustate); +#define L() (L_bit(cpustate)) +UINT8 L_bit(dsp56k_core* cpustate); +#define E() (E_bit(cpustate)) +UINT8 E_bit(dsp56k_core* cpustate); +#define U() (U_bit(cpustate)) +UINT8 U_bit(dsp56k_core* cpustate); +#define N() (N_bit(cpustate)) +UINT8 N_bit(dsp56k_core* cpustate); +#define Z() (Z_bit(cpustate)) +UINT8 Z_bit(dsp56k_core* cpustate); +#define V() (V_bit(cpustate)) +UINT8 V_bit(dsp56k_core* cpustate); +#define C() (C_bit(cpustate)) +UINT8 C_bit(dsp56k_core* cpustate); + +/* MR setters */ +void LF_bit_set(dsp56k_core* cpustate, UINT8 value); +void FV_bit_set(dsp56k_core* cpustate, UINT8 value); +void S_bits_set(dsp56k_core* cpustate, UINT8 value); +void I_bits_set(dsp56k_core* cpustate, UINT8 value); + +/* CCR setters - with macros for easy access */ +#define DSP56K_S_SET() (S_bit_set(cpustate, 1)) +#define DSP56K_S_CLEAR() (S_bit_set(cpustate, 0)) +void S_bit_set(dsp56k_core* cpustate, UINT8 value); +#define DSP56K_L_SET() (L_bit_set(cpustate, 1)) +#define DSP56K_L_CLEAR() (L_bit_set(cpustate, 0)) +void L_bit_set(dsp56k_core* cpustate, UINT8 value); +#define DSP56K_E_SET() (E_bit_set(cpustate, 1)) +#define DSP56K_E_CLEAR() (E_bit_set(cpustate, 0)) +void E_bit_set(dsp56k_core* cpustate, UINT8 value); +#define DSP56K_U_SET() (U_bit_set(cpustate, 1)) +#define DSP56K_U_CLEAR() (U_bit_set(cpustate, 0)) +void U_bit_set(dsp56k_core* cpustate, UINT8 value); +#define DSP56K_N_SET() (N_bit_set(cpustate, 1)) +#define DSP56K_N_CLEAR() (N_bit_set(cpustate, 0)) +void N_bit_set(dsp56k_core* cpustate, UINT8 value); +#define DSP56K_Z_SET() (Z_bit_set(cpustate, 1)) +#define DSP56K_Z_CLEAR() (Z_bit_set(cpustate, 0)) +void Z_bit_set(dsp56k_core* cpustate, UINT8 value); +#define DSP56K_V_SET() (V_bit_set(cpustate, 1)) +#define DSP56K_V_CLEAR() (V_bit_set(cpustate, 0)) +void V_bit_set(dsp56k_core* cpustate, UINT8 value); +#define DSP56K_C_SET() (C_bit_set(cpustate, 1)) +#define DSP56K_C_CLEAR() (C_bit_set(cpustate, 0)) +void C_bit_set(dsp56k_core* cpustate, UINT8 value); + +// TODO: Maybe some functions for Interrupt Mask and Scaling Mode go here? + + +/* 1-28 OPERATING MODE REGISTER (OMR) BITS */ +//UINT8 CD_bit(dsp56k_core* cpustate); +//UINT8 SD_bit(dsp56k_core* cpustate); +//UINT8 R_bit(dsp56k_core* cpustate); +//UINT8 SA_bit(dsp56k_core* cpustate); +//UINT8 MC_bit(dsp56k_core* cpustate); +UINT8 MB_bit(dsp56k_core* cpustate); +UINT8 MA_bit(dsp56k_core* cpustate); + +void CD_bit_set(dsp56k_core* cpustate, UINT8 value); +void SD_bit_set(dsp56k_core* cpustate, UINT8 value); +void R_bit_set(dsp56k_core* cpustate, UINT8 value); +void SA_bit_set(dsp56k_core* cpustate, UINT8 value); +void MC_bit_set(dsp56k_core* cpustate, UINT8 value); +void MB_bit_set(dsp56k_core* cpustate, UINT8 value); +void MA_bit_set(dsp56k_core* cpustate, UINT8 value); + +/* 1-27 STACK POINTER (SP) BITS */ +UINT8 UF_bit(dsp56k_core* cpustate); +UINT8 SE_bit(dsp56k_core* cpustate); + +//void UF_bit_set(dsp56k_core* cpustate, UINT8 value) {}; +//void SE_bit_set(dsp56k_core* cpustate, UINT8 value) {}; + + +// HACK - Bootstrap modes +#define BOOTSTRAP_OFF (0) +#define BOOTSTRAP_SSIX (1) +#define BOOTSTRAP_HI (2) + + +/* PCU IRQ goodies */ +void pcu_service_interrupts(dsp56k_core* cpustate); + +void dsp56k_irq_table_init(void); +void dsp56k_set_irq_source(UINT8 irq_num, UINT16 iv, const char* source); +int dsp56k_get_irq_index_by_tag(const char* tag); + +void dsp56k_add_pending_interrupt(dsp56k_core* cpustate, const char* name); // Call me to add an interrupt to the queue + +void dsp56k_clear_pending_interrupts(dsp56k_core* cpustate); +int dsp56k_count_pending_interrupts(dsp56k_core* cpustate); +void dsp56k_sort_pending_interrupts(dsp56k_core* cpustate, int num); +INT8 dsp56k_get_irq_priority(dsp56k_core* cpustate, int index); + +} // namespace DSP56K + +#endif diff --git a/src/emu/cpu/dsp56k/inst.c b/src/emu/cpu/dsp56k/inst.c index dcc6b53747a..c775724853f 100644 --- a/src/emu/cpu/dsp56k/inst.c +++ b/src/emu/cpu/dsp56k/inst.c @@ -40,7 +40,8 @@ Instruction* Instruction::decodeInstruction(const Opcode* opc, dynamic_cast(op) || dynamic_cast(op) || dynamic_cast(op) || - dynamic_cast(op)) + dynamic_cast(op) + /* TODO: More? */) { op->m_sizeIncrement = 1; return op; @@ -48,7 +49,6 @@ Instruction* Instruction::decodeInstruction(const Opcode* opc, } global_free(op); - //return NULL; } diff --git a/src/emu/cpu/dsp56k/inst.h b/src/emu/cpu/dsp56k/inst.h index f20e37532df..aad7bdc3578 100644 --- a/src/emu/cpu/dsp56k/inst.h +++ b/src/emu/cpu/dsp56k/inst.h @@ -6,6 +6,9 @@ #include "opcode.h" #include "tables.h" +#include "dsp56k.h" +#include "dsp56pcu.h" + // // An Instruction is the base class all regular ops inherit from. // @@ -27,16 +30,17 @@ public: virtual bool decode(const UINT16 word0, const UINT16 word1) = 0; virtual void disassemble(std::string& retString) const = 0; - virtual void evaluate() = 0; + virtual void evaluate(dsp56k_core* cpustate) = 0; virtual size_t size() const = 0; + virtual size_t evalSize() const { return size(); } virtual size_t accumulatorBitsModified() const = 0; // Potentially make this always return ALL (like flags) virtual size_t flags() const { return 0; } static Instruction* decodeInstruction(const Opcode* opc, - const UINT16 word0, - const UINT16 word1, - bool shifted=false); + const UINT16 word0, + const UINT16 word1, + bool shifted=false); const bool valid() const { return m_valid; } @@ -80,7 +84,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -104,7 +108,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -128,7 +132,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -154,7 +158,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -181,7 +185,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE; } }; @@ -210,7 +214,7 @@ public: sprintf(temp, "#$%x,%s", m_immediate, m_destination.c_str()); retString = m_opcode + " " + std::string(temp); } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -236,7 +240,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -259,7 +263,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -282,7 +286,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -305,7 +309,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -328,7 +332,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -412,7 +416,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 2; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -443,7 +447,7 @@ public: // NEW // sprintf(temp, "$%04x (%d)", pc + 2 + (INT16)word1, (INT16)word1); retString = m_opcode + " " + std::string(temp); } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 2; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -477,7 +481,7 @@ public: // NEW // sprintf(temp, "$%04x (%d)", pc + 1 + relativeInt, relativeInt); retString = m_opcode + " " + std::string(temp); } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -511,7 +515,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -539,7 +543,7 @@ public: // NEW // sprintf(temp, "$%04x (%d)", pc + 2 + word1, (INT16)word1); retString = m_opcode + " " + std::string(temp); } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 2; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -570,7 +574,7 @@ public: // NEW // sprintf(temp, "$%04x (%d)", pc + 1 + iVal, iVal); retString = m_opcode + " " + std::string(temp); } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -601,7 +605,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -626,7 +630,7 @@ public: { retString = m_opcode; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -659,7 +663,7 @@ public: // NEW // sprintf(temp, "$%04x (%d)", pc + 2 + (INT16)word1, (INT16)word1); retString = m_opcode + " " + std::string(temp); } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 2; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } size_t flags() { return DASMFLAG_STEP_OVER; } @@ -695,7 +699,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } size_t flags() { return DASMFLAG_STEP_OVER; } @@ -725,7 +729,7 @@ public: // NEW // sprintf(temp, "$%04x (%d)", pc + 2 + (INT16)word1, (INT16)word1); retString = m_opcode + " " + std::string(temp); } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 2; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } size_t flags() { return DASMFLAG_STEP_OVER; } @@ -757,7 +761,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } size_t flags() { return DASMFLAG_STEP_OVER; } @@ -780,7 +784,7 @@ public: { retString = m_opcode; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -803,7 +807,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -826,7 +830,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE; } }; @@ -852,7 +856,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_NONE; } }; @@ -878,7 +882,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_NONE; } }; @@ -900,7 +904,7 @@ public: { retString = m_opcode; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -925,7 +929,7 @@ public: { retString = m_opcode; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -948,7 +952,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -971,7 +975,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE; } }; @@ -995,7 +999,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -1014,11 +1018,11 @@ public: decode_QQF_special_table(BITSn(word0,0x0003), BITSn(word0,0x0008), m_source, m_source2, m_destination); - std::string A; - decode_ss_table(BITSn(word0,0x0024), A); - if (A == "!!") return false; + std::string a; + decode_ss_table(BITSn(word0,0x0024), a); + if (a == "!!") return false; - m_opcode = "dmac" + A; + m_opcode = "dmac" + a; // NEW // sprintf(opcode_str, "dmac(%s)", A); return true; } @@ -1028,7 +1032,7 @@ public: m_source + "," + m_source2 + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -1065,7 +1069,7 @@ public: // NEW // sprintf(temp, "X:(R%d),$%02x", Rnum, pc + 2 + word1); retString = m_opcode + " " + m_source + "," + std::string(temp); } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 2; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -1098,7 +1102,7 @@ public: // NEW // sprintf(temp, "#$%02x,$%04x", BITSn(word0,0x00ff), pc + 2 + word1); retString = m_opcode + " " + std::string(temp); } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 2; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -1133,7 +1137,7 @@ public: // NEW // sprintf(temp, "%s,$%04x", S1, pc + 2 + word1); retString = m_opcode + " " + m_source + "," + std::string(temp); } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 2; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -1164,7 +1168,7 @@ public: // NEW // sprintf(temp, "$%04x", pc + 2 + word1); retString = m_opcode + ", " + std::string(temp); } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 2; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -1189,7 +1193,7 @@ public: { retString = m_opcode; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -1213,7 +1217,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE; } }; @@ -1236,7 +1240,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -1258,7 +1262,7 @@ public: { retString = m_opcode; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -1285,7 +1289,7 @@ public: m_source + "," + m_source2 + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -1315,7 +1319,7 @@ public: m_source + "," + m_source2 + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -1341,7 +1345,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -1364,7 +1368,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE; } }; @@ -1395,7 +1399,7 @@ public: // NEW // sprintf(temp, "$%04x", word1); retString = m_opcode + " " + std::string(temp); } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 2; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -1429,7 +1433,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -1457,7 +1461,7 @@ public: // NEW // sprintf(temp, "$%04x", word1); retString = m_opcode + " " + std::string(temp); } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 2; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -1488,8 +1492,18 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) + { + // Get value from source + + // Set the PC + PC = 0; + + /* S L E U N Z V C */ + /* - - - - - - - - */ + } size_t size() const { return 1; } + size_t evalSize() const { return 0; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -1519,7 +1533,7 @@ public: // NEW // sprintf(temp, "$%04x", word1); retString = m_opcode + " " + std::string(temp); } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 2; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } size_t flags() { return DASMFLAG_STEP_OVER; } @@ -1554,7 +1568,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } size_t flags() { return DASMFLAG_STEP_OVER; } @@ -1583,7 +1597,7 @@ public: // NEW // sprintf(temp, "$%04x", word1); retString = m_opcode + " " + std::string(temp); } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 2; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } size_t flags() { return DASMFLAG_STEP_OVER; } @@ -1615,7 +1629,7 @@ public: // NEW // sprintf(temp, "#$%02x", BITSn(word0,0x00ff)); retString = m_opcode + " " + std::string(temp); } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } size_t flags() { return DASMFLAG_STEP_OVER; } @@ -1647,7 +1661,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } size_t flags() { return DASMFLAG_STEP_OVER; } @@ -1685,7 +1699,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -1723,7 +1737,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -1746,7 +1760,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE; } }; @@ -1769,7 +1783,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE; } }; @@ -1802,7 +1816,7 @@ public: m_source + "," + m_source2 + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -1833,7 +1847,7 @@ public: m_source + "," + m_source2 + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -1863,7 +1877,7 @@ public: m_source + "," + m_source2 + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -1899,7 +1913,7 @@ public: m_source + "," + m_source2 + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -1929,7 +1943,7 @@ public: m_source + "," + m_source2 + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -1952,9 +1966,9 @@ public: decode_QQF_special_table(BITSn(word0,0x0003), BITSn(word0,0x0008), m_source, m_source2, m_destination); - std::string A; - decode_s_table(BITSn(word0,0x0004), A); - m_opcode = "mac" + A; + std::string a; + decode_s_table(BITSn(word0,0x0004), a); + m_opcode = "mac" + a; // NEW // sprintf(opcode_str, "mac(%s)", A); return true; } @@ -1964,7 +1978,7 @@ public: m_source + "," + m_source2 + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -2007,7 +2021,7 @@ public: else retString = m_opcode; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_NONE; } @@ -2039,7 +2053,7 @@ public: { retString = m_opcode; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -2069,7 +2083,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 2; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -2107,7 +2121,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -2142,7 +2156,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -2175,7 +2189,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -2217,7 +2231,7 @@ public: { retString = m_opcode + " " + m_args; // TODO } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 2; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -2249,7 +2263,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -2280,7 +2294,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 2; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -2317,7 +2331,7 @@ public: retString = m_opcode + " " + std::string(temp) + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -2353,7 +2367,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -2390,7 +2404,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -2405,12 +2419,12 @@ public: } bool decode(const UINT16 word0, const UINT16 word1) { - INT8 B; - B = BITSn(word0,0x00ff); + INT8 b; + b = BITSn(word0,0x00ff); std::string SD; decode_HHH_table(BITSn(word1,0x0007), SD); - assemble_reg_from_W_table(BITSn(word1,0x0100), 'P', SD, B, + assemble_reg_from_W_table(BITSn(word1,0x0100), 'P', SD, b, m_source, m_destination); m_opcode = "move"; @@ -2421,7 +2435,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 2; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -2454,7 +2468,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -2493,7 +2507,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -2512,11 +2526,11 @@ public: decode_HH_table(BITSn(word0,0x00c0), SD); char temp[32]; - std::string A; + std::string a; sprintf(temp, "<$%x", BITSn(word0,0x001f)); - A = temp; + a = temp; - assemble_arguments_from_W_table(BITSn(word0,0x0100), 'X', SD, A, + assemble_arguments_from_W_table(BITSn(word0,0x0100), 'X', SD, a, m_source, m_destination); m_opcode = "moves"; @@ -2527,7 +2541,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -2562,7 +2576,7 @@ public: m_source + "," + m_source2 + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -2593,7 +2607,7 @@ public: m_source + "," + m_source2 + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -2624,7 +2638,7 @@ public: m_source + "," + m_source2 + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -2662,7 +2676,7 @@ public: m_source + "," + m_source2 + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -2693,7 +2707,7 @@ public: m_source + "," + m_source2 + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -2715,9 +2729,9 @@ public: decode_QQF_special_table(BITSn(word0,0x0003), BITSn(word0,0x0008), m_source, m_source2, m_destination); - std::string A; - decode_s_table(BITSn(word0,0x0004), A); - m_opcode = "mpy" + A; + std::string a; + decode_s_table(BITSn(word0,0x0004), a); + m_opcode = "mpy" + a; // NEW // sprintf(opcode_str, "mpy(%s)", A); return true; } @@ -2727,7 +2741,7 @@ public: m_source + "," + m_source2 + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -2754,7 +2768,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -2777,7 +2791,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -2799,7 +2813,7 @@ public: { retString = m_opcode; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -2829,7 +2843,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -2853,7 +2867,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE; } }; @@ -2877,7 +2891,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE; } }; @@ -2907,7 +2921,7 @@ public: // NEW // sprintf(temp, "#$%02x", BITSn(word0,0x00ff)); retString = m_opcode + " " + std::string(temp) + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -2940,7 +2954,7 @@ public: sprintf(temp, "X:(%s)", m_source.c_str()); retString = m_opcode + " " + std::string(temp); } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -2967,7 +2981,7 @@ public: // NEW // sprintf(temp, "#$%02x (%d)", BITSn(word0,0x00ff), BITSn(word0,0x00ff)); retString = m_opcode + " " + std::string(temp); } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -2995,7 +3009,7 @@ public: { retString = m_opcode + " " + m_source; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -3020,7 +3034,7 @@ public: { retString = m_opcode; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -3042,7 +3056,7 @@ public: { retString = m_opcode; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -3066,7 +3080,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -3090,7 +3104,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE; } }; @@ -3114,7 +3128,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE; } }; @@ -3136,7 +3150,7 @@ public: { retString = m_opcode; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } size_t flags() { return DASMFLAG_STEP_OUT; } @@ -3159,7 +3173,7 @@ public: { retString = m_opcode; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } size_t flags() { return DASMFLAG_STEP_OUT; } @@ -3185,7 +3199,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -3207,7 +3221,7 @@ public: { retString = m_opcode; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -3231,7 +3245,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -3256,7 +3270,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -3290,7 +3304,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -3314,7 +3328,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -3336,7 +3350,7 @@ public: { retString = m_opcode; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -3381,7 +3395,7 @@ public: if (m_destination2 != "R0") retString += std::string(" R0,") + m_destination2; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -3409,7 +3423,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -3434,7 +3448,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -3459,7 +3473,7 @@ public: { retString = m_opcode + " " + m_source + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -3503,7 +3517,7 @@ public: m_destination + " " + m_source2 + "," + m_destination2; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -3531,7 +3545,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_NONE; } }; @@ -3555,7 +3569,7 @@ public: { retString = m_opcode + " " + m_source; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -3577,7 +3591,7 @@ public: { retString = m_opcode; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -3601,7 +3615,7 @@ public: { retString = m_opcode + " " + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } }; @@ -3644,7 +3658,7 @@ public: m_source + "," + m_source2 + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } @@ -3690,7 +3704,7 @@ public: m_source + "," + m_source2 + "," + m_destination; } - void evaluate() {} + void evaluate(dsp56k_core* cpustate) {} size_t size() const { return 1; } size_t accumulatorBitsModified() const { return BM_HIGH | BM_MIDDLE | BM_LOW; } diff --git a/src/emu/cpu/dsp56k/opcode.c b/src/emu/cpu/dsp56k/opcode.c index 398673becb5..597caae7ae6 100644 --- a/src/emu/cpu/dsp56k/opcode.c +++ b/src/emu/cpu/dsp56k/opcode.c @@ -41,9 +41,9 @@ std::string Opcode::disassemble() const } -void Opcode::evaluate() const +void Opcode::evaluate(dsp56k_core* cpustate) const { - if (m_instruction) m_instruction->evaluate(); + if (m_instruction) m_instruction->evaluate(cpustate); if (m_parallelMove) m_parallelMove->evaluate(); } @@ -57,6 +57,16 @@ size_t Opcode::size() const return 1; } +size_t Opcode::evalSize() const +{ + if (m_instruction && m_instruction->valid()) + return m_instruction->evalSize(); // Probably doesn't matter : + m_instruction->sizeIncrement(); + + // Opcode failed to decode, so push it past dc + return 1; +} + + const std::string& Opcode::instSource() const { return m_instruction->source(); } const std::string& Opcode::instDestination() const { return m_instruction->destination(); } const size_t Opcode::instAccumulatorBitsModified() const { return m_instruction->accumulatorBitsModified(); } diff --git a/src/emu/cpu/dsp56k/opcode.h b/src/emu/cpu/dsp56k/opcode.h index a5feaf4f45f..e26f544958b 100644 --- a/src/emu/cpu/dsp56k/opcode.h +++ b/src/emu/cpu/dsp56k/opcode.h @@ -7,6 +7,8 @@ #include "inst.h" #include "pmove.h" +#include "dsp56k.h" + // // An Opcode contains an instruction and a parallel move operation. // @@ -23,8 +25,9 @@ public: virtual ~Opcode(); std::string disassemble() const; - void evaluate() const; + void evaluate(dsp56k_core* cpustate) const; size_t size() const; + size_t evalSize() const; // Peek through to the instruction const std::string& instSource() const; diff --git a/src/emu/cpu/dsp56k/pmove.h b/src/emu/cpu/dsp56k/pmove.h index 1a3d83c8133..d5a723fb609 100644 --- a/src/emu/cpu/dsp56k/pmove.h +++ b/src/emu/cpu/dsp56k/pmove.h @@ -314,13 +314,13 @@ public: } bool decode(const UINT16 word0, const UINT16 word1) { - INT8 B; + INT8 b; std::string SD; std::string args; - B = (char)(word0 & 0x00ff); + b = (char)(word0 & 0x00ff); decode_HHH_table(BITSn(word1,0x0e00), SD); - assemble_reg_from_W_table(BITSn(word1,0x0100), 'X', SD, B, m_source, m_destination); + assemble_reg_from_W_table(BITSn(word1,0x0100), 'X', SD, b, m_source, m_destination); return true; }