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Added setup sequence for the keyboard SCC

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This commit is contained in:
Joakim Larsson Edstrom 2016-07-19 21:32:40 +02:00
parent e7defcb712
commit 0982f2a337
1 changed files with 53 additions and 0 deletions
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53
src/mame/drivers/sun4.cpp
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@ -1853,6 +1853,59 @@ ROM_START( sun4_65 )
ROM_END
// SPARCstation 2 (Sun 4/75)
/* SCC init 1 for the keyboard
*----------------------------
* :scc1 A Reg 09 <- c0 Master Interrupt Control - Device reset c0 A&B: RTS=1 DTR=1 INT=0
* :scc1 int: 0
* :scc1 A Reg 04 <- 46 Setting up asynchronous frame format and clock, Parity Enable=0, Even Parity, Stop Bits 1, Clock Mode 16X * :scc1 A Reg 03 <- c0 Setting up the receiver, Receiver Enable 0, Auto Enables 0, Receiver Bits/Character 8
* :scc1 A Reg 05 <- e2 Setting up the transmitter, Transmitter Enable 0, Transmitter Bits/Character 8, Send Break 0, RTS=1 DTR=1
* :scc1 A Reg 09 <- 02 Master Interrupt Control - No reset 02 A&B: RTS=1 DTR=1 INT=0
* :scc1 A Reg 0b <- 55 Clock Mode Control 55 Clock type TTL level on RTxC pin, RCV CLK=BRG, TRA CLK=BRG, TRxC pin is Output, TRxC CLK=TRA CLK - not_implemented
* :scc1 A Reg 0c <- 7e Low byte of Time Constant for Baudrate generator
* :scc1 A Reg 0d <- 00 High byte of Time Constant for Baudrate generator
* :scc1 A Reg 0e <- 82 Misc Control Bits Baudrate Generator Input DPLL Command - not implemented
* :scc1 A Reg 03 <- c1 Setting up the receiver, Receiver Enable 1, Auto Enables 0, Receiver Bits/Character 8
* :scc1 A Reg 05 <- ea Setting up the transmitter, Transmitter Enable 1, Transmitter Bits/Character 8, Send Break 0, RTS=1, DTR=1
* :scc1 A Reg 0e <- 83 Misc Control Bits DPLL SRC=BRG Command - not implemented, BRG enabled SRC=PCLK, BRG SRC bps=38400=PCLK 4915200/128, BRG OUT 1200=38400/16
* :scc1 A Reg 00 <- 10 Reset External/Status Interrupt
* :scc1 A Reg 00 <- 10 Reset External/Status Interrupt
* SCC init 2 for the keyboard
* -------------------------------
* :scc1 A Reg 09 <- c0 Master Interrupt Control - Device reset c0 A&B: RTS=1 DTR=1 INT=0
scc1 int: 0
* :scc1 A Reg 04 <- 46 Setting up asynchronous frame format and clock, Parity Enable=0, Even Parity, Stop Bits 1, Clock Mode 16X
* :scc1 A Reg 03 <- c0 Setting up the receiver, Receiver Enable 0, Auto Enables 0, Receiver Bits/Character 8
* :scc1 A Reg 05 <- e2 Setting up the transmitter, Transmitter Enable 0, Transmitter Bits/Character 8, Send Break 0, RTS=1 DTR=1
* :scc1 A Reg 09 <- 02 Master Interrupt Control - No reset 02 A&B: RTS=1 DTR=1 INT=0
* :scc1 A Reg 0b <- 55 Clock Mode Control 55 Clock type TTL level on RTxC pin, RCV CLK=BRG, TRA CLK=BRG, TRxC pin is Output, TRxC CLK=TRA CLK - not_implemented
* :scc1 A Reg 0c <- 7e Low byte of Time Constant for Baudrate generator
* :scc1 A Reg 0d <- 00 High byte of Time Constant for Baudrate generator
* :scc1 A Reg 0e <- 82 Misc Control Bits Baudrate Generator Input DPLL Command - not implemented
* :scc1 A Reg 03 <- c1 Setting up the receiver, Receiver Enable 1, Auto Enables 0, Receiver Bits/Character 8
* :scc1 A Reg 05 <- ea Setting up the transmitter, Transmitter Enable 1, Transmitter Bits/Character 8, Send Break 0, RTS=1, DTR=1
* :scc1 A Reg 0e <- 83 Misc Control Bits DPLL SRC=BRG Command - not implemented, BRG enabled SRC=PCLK, BRG SRC bps=38400=PCLK 4915200/128, BRG OUT 1200=38400/16
* :scc1 A Reg 00 <- 10 Reset External/Status Interrupt
* :scc1 A Reg 00 <- 10 Reset External/Status Interrupt
* SCC init 3 for the keyboard - tricky one that reprogramms the baudrate constant as the last step.
* -------------------------------------------------------------------------------------------------
* :scc1 A Reg 09 <- 02 Master Interrupt Control - No Reset, No vector
* :scc1 A Reg 04 <- 44 Setting up asynchronous frame format and clock, Parity Enable=0, Even Odd, Stop Bits 1, Clock Mode 16X
* :scc1 A Reg 03 <- c0 Setting up the receiver, Receiver Enable 0, Auto Enables 0, Receiver Bits/Character 8
* :scc1 A Reg 05 <- 60 Setting up the transmitter, Transmitter Enable 0, Transmitter Bits/Character 8, Send Break 0, RTS=0 DTR=0
* :scc1 A Reg 0e <- 82 Misc Control Bits Baudrate Generator Input DPLL Command - not implemented
* :scc1 A Reg 0b <- 55 Clock Mode Control 55 Clock type TTL level on RTxC pin, RCV CLK=BRG, TRA CLK=BRG, TRxC pin is Output, TRxC CLK=TRA CLK - not_implemented
* :scc1 A Reg 0c <- 0e Low byte of Time Constant for Baudrate generator -> 9600 baud
* :scc1 A Reg 0d <- 00 High byte of Time Constant for Baudrate generator
* :scc1 A Reg 03 <- c1 Setting up the receiver, Receiver Enable 1, Auto Enables 0, Receiver Bits/Character 8
* :scc1 A Reg 05 <- 68 Setting up the transmitter, Transmitter Enable 1, Transmitter Bits/Character 8, Send Break 0, RTS=0, DTR=0
* :scc1 A Reg 0e <- 83 Misc Control Bits DPLL SRC=BRG Command - not implemented, BRG enabled SRC=PCLK, BRG SRC bps=307200=PCLK 4915200/16, BRG OUT 9600=307200/16
* :scc1 A Reg 00 <- 10 Reset External/Status Interrupt
* :scc1 A Reg 00 <- 10 Reset External/Status Interrupt
* :scc1 A Reg 0c <- 7e Low byte of Time Constant for Baudrate generator -> 1200 baud
*/
ROM_START( sun4_75 )
ROM_REGION32_BE( 0x80000, "user1", ROMREGION_ERASEFF )
ROM_LOAD( "ss2-29.rom", 0x0000, 0x40000, CRC(d04132b3) SHA1(ef26afafa2800b8e2e5e994b3a76ca17ce1314b1))