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Merge pull request #3238 from DavidHaywood/180218
XaviX - allow test mode to be visible in Monster Truck
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commit
098662e1ba
@ -140,6 +140,8 @@ public:
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DECLARE_READ8_MEMBER(pal_ntsc_r);
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DECLARE_READ8_MEMBER(xavix_4000_r);
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DECLARE_READ8_MEMBER(mult_r);
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DECLARE_WRITE8_MEMBER(mult_param_w);
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@ -356,9 +358,9 @@ void xavix_state::draw_tilemap(screen_device &screen, bitmap_ind16 &bitmap, cons
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int xtilesize = 0;
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int offset_multiplier = 0;
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int opaque = 0;
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int rambase = 0;
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uint8_t* tileregs;
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address_space& mainspace = m_maincpu->space(AS_PROGRAM);
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// all this is likely controlled by tilemap registers
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if (which == 0)
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@ -370,7 +372,6 @@ void xavix_state::draw_tilemap(screen_device &screen, bitmap_ind16 &bitmap, cons
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xtilesize = 16;
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offset_multiplier = 32;
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opaque = 1;
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rambase = 0;
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}
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else
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{
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@ -381,7 +382,6 @@ void xavix_state::draw_tilemap(screen_device &screen, bitmap_ind16 &bitmap, cons
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xtilesize = 8;
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offset_multiplier = 8;
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opaque = 0;
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rambase = 0x200;
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}
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if (tileregs[0x7] & 0x02)
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@ -395,14 +395,14 @@ void xavix_state::draw_tilemap(screen_device &screen, bitmap_ind16 &bitmap, cons
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// and expected a fixed layout, still need to handle that.
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int count;
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count = rambase;
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count = tileregs[0x0]<<8;
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for (int y = 0; y < ydimension; y++)
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{
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for (int x = 0; x < xdimension; x++)
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{
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int bpp, pal, scrolly, scrollx;
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int tile = m_mainram[count];
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tile |= (m_mainram[count + (ydimension*xdimension)] << 8);
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int tile = mainspace.read_byte(count);
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tile |= mainspace.read_byte(count + (ydimension*xdimension)) << 8;
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count++;
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bpp = (tileregs[0x3] & 0x0e) >> 1;
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@ -1240,6 +1240,10 @@ WRITE8_MEMBER(xavix_state::tmap1_regs_w)
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WRITE8_MEMBER(xavix_state::xavix_6fd8_w) // also related to tilemap 2?
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{
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// possibly just a mirror of tmap2_regs_w, at least it writes 0x04 here which would be the correct
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// base address to otherwise write at tmap2_regs_w offset 0
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tmap2_regs_w(space,offset,data);
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//logerror("%s: xavix_6fd8_w data %02x\n", machine().describe_context(), data);
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}
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@ -1262,6 +1266,17 @@ READ8_MEMBER(xavix_state::tmap2_regs_r)
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return m_tmap2_regs[offset];
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}
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READ8_MEMBER(xavix_state::xavix_4000_r)
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{
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if (offset < 0x100)
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{
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return ((offset>>4) | (offset<<4));
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}
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else
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{
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return 0x00;
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}
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}
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// DATA reads from 0x8000-0xffff are banked by byte 0xff of 'ram' (this is handled in the CPU core)
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@ -1269,6 +1284,10 @@ ADDRESS_MAP_START(xavix_state::xavix_map)
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AM_RANGE(0x000000, 0x0001ff) AM_RAM
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AM_RANGE(0x000200, 0x003fff) AM_RAM AM_SHARE("mainram")
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// this might not be a real area, the tilemap base register gets set to 0x40 in monster truck service mode, and expects a fixed layout.
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// As that would point at this address maybe said layout is being read from here, or maybe it's just a magic tilemap register value that doesn't read address space at all.
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AM_RANGE(0x004000, 0x0041ff) AM_READ(xavix_4000_r)
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// 6xxx ranges are the video hardware
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// appears to be 256 sprites (shares will be renamed once their purpose is known)
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AM_RANGE(0x006000, 0x0060ff) AM_RAM AM_SHARE("spr_attr0")
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@ -1284,12 +1303,12 @@ ADDRESS_MAP_START(xavix_state::xavix_map)
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AM_RANGE(0x006a00, 0x006a1f) AM_RAM AM_SHARE("spr_attra") // test mode, pass flag 0x20
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AM_RANGE(0x006fc0, 0x006fc0) AM_WRITE(xavix_6fc0_w) // startup
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AM_RANGE(0x006fc0, 0x006fc0) AM_WRITE(xavix_6fc0_w) // startup (maybe this is a mirror of tmap1_regs_w)
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AM_RANGE(0x006fc8, 0x006fcf) AM_WRITE(tmap1_regs_w) // video registers
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AM_RANGE(0x006fd0, 0x006fd7) AM_READWRITE(tmap2_regs_r, tmap2_regs_w)
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AM_RANGE(0x006fd8, 0x006fd8) AM_WRITE(xavix_6fd8_w) // startup (taitons1)
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AM_RANGE(0x006fd8, 0x006fd8) AM_WRITE(xavix_6fd8_w) // startup (mirror of tmap2_regs_w?)
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AM_RANGE(0x006fe0, 0x006fe0) AM_READWRITE(vid_dma_trigger_r, vid_dma_trigger_w) // after writing to 6fe1/6fe2 and 6fe5/6fe6 rad_mtrk writes 0x43/0x44 here then polls on 0x40 (see function call at c273) write values are hardcoded, similar code at 18401
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AM_RANGE(0x006fe1, 0x006fe2) AM_WRITE(vid_dma_params_1_w)
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