mirror of
https://github.com/holub/mame
synced 2025-04-25 09:50:04 +03:00
intelfsh.c: [Joe Sturm]
* Added support for AMD 29F400T, AMD 29F800T and FUJITSU 29F160T. ti85.c: [Joe Sturm] * Improved support of TI83 Plus, TI83 Plus Silver Edition, and TI84 Plus, and TI84 Plus Silver Edition by switching over to bankdev and adding proper flash chips. They should be working now (press Q to power on). Out of whatsnew: ti84p was not added to mess.lst becuase rom is not available yet. Current romload is same CRC as ti84pse but at a smaller size. Once corrected and obtained it should work.
This commit is contained in:
Scott Stone
parent
c47dc0a3df
commit
0a61c69a77
@ -82,7 +82,10 @@ const device_type ATMEL_29C010 = &device_creator<atmel_29c010_device>;
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const device_type AMD_29F010 = &device_creator<amd_29f010_device>;
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const device_type AMD_29F040 = &device_creator<amd_29f040_device>;
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const device_type AMD_29F080 = &device_creator<amd_29f080_device>;
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const device_type AMD_29F400T = &device_creator<amd_29f400t_device>;
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const device_type AMD_29F800T = &device_creator<amd_29f800t_device>;
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const device_type AMD_29LV200T = &device_creator<amd_29lv200t_device>;
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const device_type FUJITSU_29F160T = &device_creator<fujitsu_29f160t_device>;
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const device_type FUJITSU_29F016A = &device_creator<fujitsu_29f016a_device>;
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const device_type FUJITSU_29DL16X = &device_creator<fujitsu_29dl16x_device>;
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const device_type INTEL_E28F400B = &device_creator<intel_e28f400b_device>;
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@ -163,6 +166,7 @@ intelfsh_device::intelfsh_device(const machine_config &mconfig, device_type type
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m_maker_id(0),
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m_sector_is_4k(false),
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m_sector_is_16k(false),
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m_top_boot_sector(false),
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m_status(0x80),
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m_erase_sector(0),
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m_flash_mode(FM_NORMAL),
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@ -211,6 +215,22 @@ intelfsh_device::intelfsh_device(const machine_config &mconfig, device_type type
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m_device_id = 0xd5;
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map = ADDRESS_MAP_NAME( memory_map8_8Mb );
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break;
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case FLASH_AMD_29F400T:
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m_bits = 8;
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m_size = 0x80000;
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m_maker_id = MFG_AMD;
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m_device_id = 0x23;
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m_top_boot_sector = true;
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map = ADDRESS_MAP_NAME( memory_map8_4Mb );
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break;
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case FLASH_AMD_29F800T:
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m_bits = 8;
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m_size = 0x100000;
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m_maker_id = MFG_AMD;
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m_device_id = 0xda;
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m_top_boot_sector = true;
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map = ADDRESS_MAP_NAME( memory_map8_8Mb );
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break;
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case FLASH_AMD_29LV200T:
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m_bits = 8;
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m_size = 0x40000;
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@ -256,6 +276,14 @@ intelfsh_device::intelfsh_device(const machine_config &mconfig, device_type type
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m_device_id = 0x4471;
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map = ADDRESS_MAP_NAME( memory_map16_4Mb );
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break;
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case FLASH_FUJITSU_29F160T:
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m_bits = 8;
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m_size = 0x200000;
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m_maker_id = MFG_FUJITSU;
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m_device_id = 0xad;
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m_top_boot_sector = true;
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map = ADDRESS_MAP_NAME( memory_map8_16Mb );
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break;
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case FLASH_FUJITSU_29F016A:
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m_bits = 8;
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m_size = 0x200000;
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@ -349,6 +377,9 @@ intelfsh16_device::intelfsh16_device(const machine_config &mconfig, device_type
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intel_28f016s5_device::intel_28f016s5_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: intelfsh8_device(mconfig, INTEL_28F016S5, "Intel 28F016S5 Flash", tag, owner, clock, FLASH_INTEL_28F016S5, "intel_28f016s5", __FILE__) { }
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fujitsu_29f160t_device::fujitsu_29f160t_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: intelfsh8_device(mconfig, FUJITSU_29F160T, "Fujitsu 29F160 Flash", tag, owner, clock, FLASH_FUJITSU_29F160T, "fujitsu_29f160t", __FILE__) { }
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fujitsu_29f016a_device::fujitsu_29f016a_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: intelfsh8_device(mconfig, FUJITSU_29F016A, "Fujitsu 29F016A Flash", tag, owner, clock, FLASH_FUJITSU_29F016A, "fujitsu_29f016a", __FILE__) { }
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@ -369,6 +400,12 @@ amd_29f040_device::amd_29f040_device(const machine_config &mconfig, const char *
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amd_29f080_device::amd_29f080_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: intelfsh8_device(mconfig, AMD_29F080, "AMD 29F080 Flash", tag, owner, clock, FLASH_AMD_29F080, "amd_29f080", __FILE__) { }
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amd_29f400t_device::amd_29f400t_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: intelfsh8_device(mconfig, AMD_29F080, "AMD 29F400 Flash", tag, owner, clock, FLASH_AMD_29F400T, "amd_29f400t", __FILE__) { }
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amd_29f800t_device::amd_29f800t_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: intelfsh8_device(mconfig, AMD_29F080, "AMD 29F800 Flash", tag, owner, clock, FLASH_AMD_29F080, "amd_29f800t", __FILE__) { }
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amd_29lv200t_device::amd_29lv200t_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: intelfsh8_device(mconfig, AMD_29LV200T, "AMD 29LV200T Flash", tag, owner, clock, FLASH_AMD_29LV200T, "amd_29lv200t", __FILE__) { }
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@ -878,6 +915,30 @@ void intelfsh_device::write_full(UINT32 address, UINT32 data)
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m_erase_sector = address & ((m_bits == 16) ? ~0x1fff : ~0x3fff);
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m_timer->adjust( attotime::from_msec( 500 ) );
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}
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else if(m_top_boot_sector && address >= (m_size - 64*1024))
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{
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if (address >= (m_size - (16*1024)))
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{
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for (offs_t offs = 0; offs < 16 * 1024; offs++)
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m_addrspace[0]->write_byte((base & ~0x3fff) + offs, 0xff);
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m_erase_sector = address & ((m_bits == 16) ? ~0x1fff : ~0x3fff);
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m_timer->adjust( attotime::from_msec( 500 ) );
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}
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else if (address >= (m_size - (32*1024)))
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{
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for (offs_t offs = 0; offs < 8 * 1024; offs++)
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m_addrspace[0]->write_byte((base & ~0x1fff) + offs, 0xff);
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m_erase_sector = address & ((m_bits == 16) ? ~0xfff : ~0x1fff);
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m_timer->adjust( attotime::from_msec( 250 ) );
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}
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else
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{
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for (offs_t offs = 0; offs < 32 * 1024; offs++)
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m_addrspace[0]->write_byte((base & ~0x7fff) + offs, 0xff);
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m_erase_sector = address & ((m_bits == 16) ? ~0x3fff : ~0x7fff);
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m_timer->adjust( attotime::from_msec( 500 ) );
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}
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}
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else
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{
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for (offs_t offs = 0; offs < 64 * 1024; offs++)
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@ -28,9 +28,18 @@
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#define MCFG_AMD_29F080_ADD(_tag) \
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MCFG_DEVICE_ADD(_tag, AMD_29F080, 0)
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#define MCFG_AMD_29F400T_ADD(_tag) \
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MCFG_DEVICE_ADD(_tag, AMD_29F400T, 0)
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#define MCFG_AMD_29F800T_ADD(_tag) \
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MCFG_DEVICE_ADD(_tag, AMD_29F800T, 0)
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#define MCFG_AMD_29LV200T_ADD(_tag) \
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MCFG_DEVICE_ADD(_tag, AMD_29LV200T, 0)
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#define MCFG_FUJITSU_29F160T_ADD(_tag) \
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MCFG_DEVICE_ADD(_tag, FUJITSU_29F160T, 0)
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#define MCFG_FUJITSU_29F016A_ADD(_tag) \
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MCFG_DEVICE_ADD(_tag, FUJITSU_29F016A, 0)
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@ -94,12 +103,15 @@ public:
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{
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// 8-bit variants
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FLASH_INTEL_28F016S5 = 0x0800,
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FLASH_FUJITSU_29F160T,
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FLASH_FUJITSU_29F016A,
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FLASH_FUJITSU_29DL16X,
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FLASH_ATMEL_29C010,
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FLASH_AMD_29F010,
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FLASH_AMD_29F040,
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FLASH_AMD_29F080,
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FLASH_AMD_29F400T,
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FLASH_AMD_29F800T,
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FLASH_AMD_29LV200T,
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FLASH_SHARP_LH28F016S,
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FLASH_INTEL_E28F008SA,
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@ -149,6 +161,7 @@ protected:
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UINT8 m_maker_id;
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bool m_sector_is_4k;
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bool m_sector_is_16k;
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bool m_top_boot_sector;
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UINT8 m_page_size;
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// internal state
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@ -211,6 +224,12 @@ public:
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intel_28f016s5_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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class fujitsu_29f160t_device : public intelfsh8_device
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{
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public:
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fujitsu_29f160t_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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class fujitsu_29f016a_device : public intelfsh8_device
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{
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public:
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@ -247,6 +266,18 @@ public:
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amd_29f080_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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class amd_29f400t_device : public intelfsh8_device
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{
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public:
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amd_29f400t_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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class amd_29f800t_device : public intelfsh8_device
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{
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public:
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amd_29f800t_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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class amd_29lv200t_device : public intelfsh8_device
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{
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public:
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@ -346,7 +377,10 @@ extern const device_type ATMEL_29C010;
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extern const device_type AMD_29F010;
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extern const device_type AMD_29F040;
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extern const device_type AMD_29F080;
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extern const device_type AMD_29F400T;
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extern const device_type AMD_29F800T;
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extern const device_type AMD_29LV200T;
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extern const device_type FUJITSU_29F160T;
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extern const device_type FUJITSU_29F016A;
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extern const device_type FUJITSU_29DL16X;
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extern const device_type INTEL_E28F400B;
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@ -163,6 +163,19 @@ TI-83Plus ports:
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10: Control port for the display controller
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11: Data port for the display controller
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TI-83PlusSE ports:
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0: Link
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1: Keypad
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2: ?
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3: ON status, LCD power
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4: Interrupt status
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5: Memory page 3
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6: Memory page 1
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7: Memory page 2
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10: Controll port for the display controller
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11: Data port for the display controller
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15: Asic Version
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TI-85 ports:
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0: Video buffer offset (write only)
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1: Keypad
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@ -189,6 +202,7 @@ TI-86 ports:
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#include "cpu/z80/z80.h"
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#include "imagedev/snapquik.h"
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#include "includes/ti85.h"
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#include "machine/bankdev.h"
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/* port i/o functions */
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@ -252,13 +266,48 @@ static ADDRESS_MAP_START( ti83p_io, AS_IO, 8, ti85_state )
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ADDRESS_MAP_GLOBAL_MASK(0xff)
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AM_RANGE(0x0000, 0x0000) AM_READWRITE(ti8x_plus_serial_r, ti8x_plus_serial_w)
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AM_RANGE(0x0001, 0x0001) AM_READWRITE(ti8x_keypad_r, ti8x_keypad_w )
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AM_RANGE(0x0002, 0x0002) AM_READWRITE(ti83p_port_0002_r, ti83p_port_0002_w )
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AM_RANGE(0x0003, 0x0003) AM_READWRITE(ti83_port_0003_r, ti83p_port_0003_w )
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AM_RANGE(0x0004, 0x0004) AM_READWRITE(ti83_port_0003_r, ti83p_port_0004_w )
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AM_RANGE(0x0002, 0x0002) AM_READ(ti83p_port_0002_r)
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AM_RANGE(0x0003, 0x0003) AM_READWRITE(ti83_port_0003_r, ti83p_int_mask_w )
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AM_RANGE(0x0004, 0x0004) AM_READWRITE(ti83p_port_0004_r, ti83p_port_0004_w )
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AM_RANGE(0x0006, 0x0006) AM_READWRITE(ti86_port_0005_r, ti83p_port_0006_w )
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AM_RANGE(0x0007, 0x0007) AM_READWRITE(ti86_port_0006_r, ti83p_port_0007_w )
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AM_RANGE(0x0010, 0x0010) AM_DEVREADWRITE("t6a04", t6a04_device, control_read, control_write)
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AM_RANGE(0x0011, 0x0011) AM_DEVREADWRITE("t6a04", t6a04_device, data_read, data_write)
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AM_RANGE(0x0007, 0x0007) AM_WRITE(ti83p_port_0014_w )
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( ti83pse_io, AS_IO, 8, ti85_state )
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ADDRESS_MAP_GLOBAL_MASK(0xff)
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AM_RANGE(0x0000, 0x0000) AM_READWRITE(ti8x_plus_serial_r, ti8x_plus_serial_w)
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AM_RANGE(0x0001, 0x0001) AM_READWRITE(ti8x_keypad_r, ti8x_keypad_w )
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AM_RANGE(0x0002, 0x0002) AM_READWRITE(ti83pse_port_0002_r, ti83pse_int_ack_w )
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AM_RANGE(0x0003, 0x0003) AM_READWRITE(ti83_port_0003_r, ti83p_int_mask_w )
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AM_RANGE(0x0004, 0x0004) AM_READWRITE(ti83p_port_0004_r, ti83pse_port_0004_w )
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AM_RANGE(0x0005, 0x0005) AM_READWRITE(ti83pse_port_0005_r, ti83pse_port_0005_w )
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AM_RANGE(0x0006, 0x0006) AM_READWRITE(ti86_port_0005_r, ti83pse_port_0006_w )
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AM_RANGE(0x0007, 0x0007) AM_READWRITE(ti86_port_0006_r, ti83pse_port_0007_w )
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AM_RANGE(0x0009, 0x0009) AM_READ(ti83pse_port_0009_r)
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AM_RANGE(0x0010, 0x0010) AM_DEVREADWRITE("t6a04", t6a04_device, control_read, control_write)
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AM_RANGE(0x0011, 0x0011) AM_DEVREADWRITE("t6a04", t6a04_device, data_read, data_write)
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AM_RANGE(0x0012, 0x0012) AM_DEVREADWRITE("t6a04", t6a04_device, control_read, control_write)
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AM_RANGE(0x0013, 0x0013) AM_DEVREADWRITE("t6a04", t6a04_device, data_read, data_write)
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AM_RANGE(0x0014, 0x0014) AM_WRITE(ti83p_port_0014_w )
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AM_RANGE(0x0015, 0x0015) AM_READ(ti83pse_port_0015_r)
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AM_RANGE(0x0020, 0x0020) AM_READWRITE(ti83pse_port_0020_r, ti83pse_port_0020_w )
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AM_RANGE(0x0021, 0x0021) AM_READWRITE(ti83pse_port_0021_r, ti83pse_port_0021_w )
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AM_RANGE(0x0030, 0x0030) AM_READWRITE(ti83pse_ctimer1_setup_r, ti83pse_ctimer1_setup_w )
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AM_RANGE(0x0031, 0x0031) AM_READWRITE(ti83pse_ctimer1_loop_r, ti83pse_ctimer1_loop_w )
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AM_RANGE(0x0032, 0x0032) AM_READWRITE(ti83pse_ctimer1_count_r, ti83pse_ctimer1_count_w )
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AM_RANGE(0x0033, 0x0033) AM_READWRITE(ti83pse_ctimer2_setup_r, ti83pse_ctimer2_setup_w )
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AM_RANGE(0x0034, 0x0034) AM_READWRITE(ti83pse_ctimer2_loop_r, ti83pse_ctimer2_loop_w )
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AM_RANGE(0x0035, 0x0035) AM_READWRITE(ti83pse_ctimer2_count_r, ti83pse_ctimer2_count_w )
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AM_RANGE(0x0036, 0x0036) AM_READWRITE(ti83pse_ctimer3_setup_r, ti83pse_ctimer3_setup_w )
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AM_RANGE(0x0037, 0x0037) AM_READWRITE(ti83pse_ctimer3_loop_r, ti83pse_ctimer3_loop_w )
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AM_RANGE(0x0038, 0x0038) AM_READWRITE(ti83pse_ctimer3_count_r, ti83pse_ctimer3_count_w )
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AM_RANGE(0x0055, 0x0055) AM_READ(ti84pse_port_0055_r)
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AM_RANGE(0x0056, 0x0056) AM_READ(ti84pse_port_0056_r)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( ti86_io, AS_IO, 8, ti85_state )
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@ -288,6 +337,23 @@ static ADDRESS_MAP_START( ti86_mem , AS_PROGRAM, 8, ti85_state )
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AM_RANGE(0xc000, 0xffff) AM_RAMBANK("bank4")
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( ti83pse_banked_mem , AS_PROGRAM, 8, ti85_state )
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AM_RANGE(0x0000, 0x1fffff) AM_DEVREADWRITE("flash", intelfsh8_device, read, write)
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AM_RANGE(0x200000, 0x21BFFF) AM_RAM AM_SHARE("nvram")
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( ti83p_banked_mem , AS_PROGRAM, 8, ti85_state )
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AM_RANGE(0x00000, 0x7ffff) AM_DEVREADWRITE("flash", intelfsh8_device, read, write)
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AM_RANGE(0x100000, 0x107fff) AM_RAM AM_SHARE("nvram")
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( ti83p_asic_mem , AS_PROGRAM, 8, ti85_state )
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AM_RANGE(0x0000, 0x3fff) AM_DEVREADWRITE("membank1", address_map_bank_device, read8, write8)
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AM_RANGE(0x4000, 0x7fff) AM_DEVREADWRITE("membank2", address_map_bank_device, read8, write8)
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AM_RANGE(0x8000, 0xbfff) AM_DEVREADWRITE("membank3", address_map_bank_device, read8, write8)
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AM_RANGE(0xc000, 0xffff) AM_DEVREADWRITE("membank4", address_map_bank_device, read8, write8)
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ADDRESS_MAP_END
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/* keyboard input */
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static INPUT_PORTS_START (ti81)
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@ -428,7 +494,7 @@ static INPUT_PORTS_START (ti82)
|
||||
PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("3") PORT_CODE(KEYCODE_3)
|
||||
PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("2") PORT_CODE(KEYCODE_2)
|
||||
PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("1") PORT_CODE(KEYCODE_1)
|
||||
PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("STORE") PORT_CODE(KEYCODE_TAB)
|
||||
PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("STORE") PORT_CODE(KEYCODE_S)
|
||||
PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("TRACE") PORT_CODE(KEYCODE_F4)
|
||||
PORT_START("BIT2") /* bit 2 */
|
||||
PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Right") PORT_CODE(KEYCODE_RIGHT)
|
||||
@ -470,7 +536,7 @@ static INPUT_PORTS_START (ti82)
|
||||
PORT_START("BIT7") /* bit 7 */
|
||||
PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("STAT") PORT_CODE(KEYCODE_TILDE)
|
||||
PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("x-VAR") PORT_CODE(KEYCODE_X)
|
||||
PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ALPHA") PORT_CODE(KEYCODE_CAPSLOCK)
|
||||
PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ALPHA") PORT_CODE(KEYCODE_LSHIFT)
|
||||
PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("DEL") PORT_CODE(KEYCODE_DEL)
|
||||
PORT_START("ON") /* ON */
|
||||
PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("ON/OFF") PORT_CODE(KEYCODE_Q)
|
||||
@ -597,11 +663,11 @@ MACHINE_CONFIG_END
|
||||
static MACHINE_CONFIG_DERIVED( ti83p, ti81 )
|
||||
MCFG_CPU_MODIFY("maincpu")
|
||||
MCFG_CPU_CLOCK(6000000) /* 8 MHz running at 6 MHz */
|
||||
MCFG_CPU_PROGRAM_MAP(ti86_mem)
|
||||
MCFG_CPU_PROGRAM_MAP(ti83p_asic_mem)
|
||||
MCFG_CPU_IO_MAP(ti83p_io)
|
||||
|
||||
MCFG_MACHINE_START_OVERRIDE(ti85_state, ti83p )
|
||||
MCFG_MACHINE_RESET_OVERRIDE(ti85_state, ti85 )
|
||||
MCFG_MACHINE_RESET_OVERRIDE(ti85_state, ti83p )
|
||||
|
||||
MCFG_SCREEN_MODIFY("screen")
|
||||
MCFG_SCREEN_UPDATE_DEVICE("t6a04", t6a04_device, screen_update)
|
||||
@ -610,23 +676,79 @@ static MACHINE_CONFIG_DERIVED( ti83p, ti81 )
|
||||
MCFG_PALETTE_ENTRIES(2)
|
||||
MCFG_PALETTE_INIT_OWNER(ti85_state, ti82 )
|
||||
|
||||
MCFG_DEVICE_ADD("membank1", ADDRESS_MAP_BANK, 0)
|
||||
MCFG_DEVICE_PROGRAM_MAP(ti83p_banked_mem)
|
||||
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
|
||||
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
|
||||
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
|
||||
|
||||
MCFG_DEVICE_ADD("membank2", ADDRESS_MAP_BANK, 0)
|
||||
MCFG_DEVICE_PROGRAM_MAP(ti83p_banked_mem)
|
||||
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
|
||||
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
|
||||
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
|
||||
|
||||
MCFG_DEVICE_ADD("membank3", ADDRESS_MAP_BANK, 0)
|
||||
MCFG_DEVICE_PROGRAM_MAP(ti83p_banked_mem)
|
||||
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
|
||||
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
|
||||
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
|
||||
|
||||
MCFG_DEVICE_ADD("membank4", ADDRESS_MAP_BANK, 0)
|
||||
MCFG_DEVICE_PROGRAM_MAP(ti83p_banked_mem)
|
||||
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
|
||||
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
|
||||
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
|
||||
|
||||
MCFG_DEVICE_ADD("t6a04", T6A04, 0)
|
||||
MCFG_T6A04_SIZE(96, 64)
|
||||
|
||||
MCFG_SPEAKER_STANDARD_MONO("mono")
|
||||
MCFG_SOUND_ADD("speaker", SPEAKER_SOUND, 0)
|
||||
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
|
||||
|
||||
MCFG_AMD_29F400T_ADD("flash")
|
||||
|
||||
//MCFG_TI83PSERIAL_ADD( "tiserial" )
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
static MACHINE_CONFIG_DERIVED( ti83pse, ti83p )
|
||||
MCFG_CPU_MODIFY("maincpu")
|
||||
MCFG_CPU_CLOCK( 15000000)
|
||||
MCFG_CPU_IO_MAP(ti83pse_io)
|
||||
|
||||
MCFG_DEVICE_MODIFY("membank1")
|
||||
MCFG_DEVICE_PROGRAM_MAP(ti83pse_banked_mem)
|
||||
|
||||
MCFG_DEVICE_MODIFY("membank2")
|
||||
MCFG_DEVICE_PROGRAM_MAP(ti83pse_banked_mem)
|
||||
|
||||
MCFG_DEVICE_MODIFY("membank3")
|
||||
MCFG_DEVICE_PROGRAM_MAP(ti83pse_banked_mem)
|
||||
|
||||
MCFG_DEVICE_MODIFY("membank4")
|
||||
MCFG_DEVICE_PROGRAM_MAP(ti83pse_banked_mem)
|
||||
|
||||
MCFG_MACHINE_START_OVERRIDE(ti85_state, ti83pse )
|
||||
MCFG_MACHINE_RESET_OVERRIDE(ti85_state, ti83pse )
|
||||
MCFG_DEVICE_REPLACE("flash", FUJITSU_29F160T, 0)
|
||||
|
||||
//MCFG_TI83PSERIAL_ADD( "tiserial" )
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
static MACHINE_CONFIG_DERIVED( ti84p, ti83pse )
|
||||
MCFG_DEVICE_REPLACE("flash", AMD_29F800T , 0)
|
||||
//MCFG_TI83PSERIAL_ADD( "tiserial" )
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
|
||||
static MACHINE_CONFIG_DERIVED( ti73, ti83p )
|
||||
//MCFG_DEVICE_REMOVE( "tiserial" )
|
||||
//MCFG_TI73SERIAL_ADD( "tiserial" )
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
ROM_START (ti73)
|
||||
ROM_REGION (0x80000, "bios",0)
|
||||
ROM_REGION (0x80000, "flash",0)
|
||||
ROM_DEFAULT_BIOS("v16")
|
||||
ROM_SYSTEM_BIOS( 0, "v16", "V 1.6" )
|
||||
ROMX_LOAD( "ti73v160.rom", 0x00000, 0x80000, CRC(bb0e3a16) SHA1(d62c2c7532698962818a747a7f32e35e41dfe338), ROM_BIOS(1) )
|
||||
@ -688,7 +810,7 @@ ROM_START (ti83)
|
||||
ROM_END
|
||||
|
||||
ROM_START (ti83p)
|
||||
ROM_REGION (0x80000, "bios",0)
|
||||
ROM_REGION (0x80000, "flash",0)
|
||||
ROM_DEFAULT_BIOS("v116")
|
||||
ROM_SYSTEM_BIOS( 0, "v103", "V 1.03" )
|
||||
ROMX_LOAD( "ti83pv103.bin", 0x00000, 0x80000, CRC(da466be0) SHA1(37eaeeb9fb5c18fb494e322b75070e80cc4d858e), ROM_BIOS(1) )
|
||||
@ -752,19 +874,26 @@ ROM_END
|
||||
|
||||
|
||||
ROM_START (ti83pse)
|
||||
ROM_REGION (0x200000, "bios",0)
|
||||
ROM_REGION (0x200000, "flash", 0)
|
||||
ROM_DEFAULT_BIOS("v116")
|
||||
ROM_SYSTEM_BIOS( 0, "v116", "V 1.16" )
|
||||
ROMX_LOAD( "ti83psev116.bin", 0x00000, 0x200000, CRC(d2570863) SHA1(d4214b3c0ebb26e10fe95294ac72a90d2ba99537), ROM_BIOS(1) )
|
||||
ROM_END
|
||||
|
||||
ROM_START (ti84pse)
|
||||
ROM_REGION (0x200000, "bios",0)
|
||||
ROM_REGION (0x200000, "flash",0)
|
||||
ROM_DEFAULT_BIOS("v241")
|
||||
ROM_SYSTEM_BIOS( 0, "v241", "V 2.41" )
|
||||
ROMX_LOAD( "ti84sev241.bin", 0x00000, 0x200000, CRC(5758db36) SHA1(7daa4f22e9b5dc8a1cc8fd31bceece9fa8b43515), ROM_BIOS(1) )
|
||||
ROM_END
|
||||
|
||||
ROM_START (ti84p)
|
||||
ROM_REGION (0x100000, "flash",0)
|
||||
ROM_DEFAULT_BIOS("v241")
|
||||
ROM_SYSTEM_BIOS( 0, "v241", "V 2.41" )
|
||||
ROMX_LOAD( "ti84v241.bin", 0x00000, 0x100000, CRC(5758db36) SHA1(7daa4f22e9b5dc8a1cc8fd31bceece9fa8b43515), ROM_BIOS(1) )
|
||||
ROM_END
|
||||
|
||||
|
||||
/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME FLAGS */
|
||||
COMP( 1990, ti81, 0, 0, ti81, ti81, driver_device, 0, "Texas Instruments", "TI-81", GAME_NO_SOUND )
|
||||
@ -775,6 +904,6 @@ COMP( 1996, ti83, 0, 0, ti83, ti83, driver_device, 0, "T
|
||||
COMP( 1997, ti86, 0, 0, ti86, ti85, driver_device, 0, "Texas Instruments", "TI-86", GAME_NO_SOUND )
|
||||
COMP( 1998, ti73, 0, 0, ti73, ti82, driver_device, 0, "Texas Instruments", "TI-73", GAME_NO_SOUND )
|
||||
COMP( 1999, ti83p, 0, 0, ti83p, ti82, driver_device, 0, "Texas Instruments", "TI-83 Plus", GAME_NO_SOUND )
|
||||
COMP( 2001, ti83pse, 0, 0, ti85, ti85, driver_device, 0, "Texas Instruments", "TI-83 Plus Silver Edition", GAME_NOT_WORKING | GAME_NO_SOUND)
|
||||
//COMP( 2004, ti84p, 0, 0, ti85, ti85, driver_device, 0, "Texas Instruments", "TI-84 Plus", GAME_NOT_WORKING | GAME_NO_SOUND)
|
||||
COMP( 2004, ti84pse, 0, 0, ti85, ti85, driver_device, 0, "Texas Instruments", "TI-84 Plus Silver Edition", GAME_NOT_WORKING | GAME_NO_SOUND)
|
||||
COMP( 2001, ti83pse, 0, 0, ti83pse, ti82, driver_device, 0, "Texas Instruments", "TI-83 Plus Silver Edition", GAME_NO_SOUND )
|
||||
COMP( 2004, ti84p, 0, 0, ti84p, ti82, driver_device, 0, "Texas Instruments", "TI-84 Plus", GAME_NO_SOUND )
|
||||
COMP( 2004, ti84pse, 0, 0, ti83pse, ti82, driver_device, 0, "Texas Instruments", "TI-84 Plus Silver Edition", GAME_NO_SOUND )
|
||||
|
||||
@ -9,8 +9,44 @@
|
||||
|
||||
#include "imagedev/snapquik.h"
|
||||
#include "video/t6a04.h"
|
||||
#include "machine/bankdev.h"
|
||||
#include "sound/speaker.h"
|
||||
#include "machine/nvram.h"
|
||||
#include "machine/intelfsh.h"
|
||||
|
||||
|
||||
/* model */
|
||||
typedef enum {
|
||||
TI81,
|
||||
TI81v2,
|
||||
TI82,
|
||||
TI83,
|
||||
TI85,
|
||||
TI86,
|
||||
TI83P,
|
||||
TI83PSE,
|
||||
TI84P,
|
||||
TI84PSE
|
||||
} ti85_models;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT8 loop;
|
||||
UINT8 setup;
|
||||
float divsor;
|
||||
bool interrupt;
|
||||
UINT8 max;
|
||||
UINT8 count;
|
||||
} ti83pse_timer;
|
||||
|
||||
typedef enum TI83PSE_CTIMER
|
||||
{
|
||||
CRYSTAL_TIMER1 = 0,
|
||||
CRYSTAL_TIMER2,
|
||||
CRYSTAL_TIMER3,
|
||||
HW_TIMER1,
|
||||
HW_TIMER2
|
||||
} ti83pse_ctimers;
|
||||
|
||||
class ti85_state : public driver_device
|
||||
{
|
||||
@ -20,26 +56,41 @@ public:
|
||||
m_maincpu(*this, "maincpu"),
|
||||
m_speaker(*this, "speaker"),
|
||||
// m_serial(*this, "tiserial"),
|
||||
m_nvram(*this, "nvram")
|
||||
m_nvram(*this, "nvram"),
|
||||
m_flash(*this, "flash"),
|
||||
m_membank1(*this, "membank1"),
|
||||
m_membank2(*this, "membank2"),
|
||||
m_membank3(*this, "membank3"),
|
||||
m_membank4(*this, "membank4")
|
||||
{ }
|
||||
|
||||
required_device<cpu_device> m_maincpu;
|
||||
optional_device<speaker_sound_device> m_speaker;
|
||||
//optional_device<> m_serial;
|
||||
optional_shared_ptr<UINT8> m_nvram;
|
||||
optional_device<intelfsh_device> m_flash;
|
||||
optional_device<address_map_bank_device> m_membank1;
|
||||
optional_device<address_map_bank_device> m_membank2;
|
||||
optional_device<address_map_bank_device> m_membank3;
|
||||
optional_device<address_map_bank_device> m_membank4;
|
||||
|
||||
UINT8 m_LCD_memory_base;
|
||||
UINT8 m_LCD_contrast;
|
||||
UINT8 m_LCD_status;
|
||||
UINT8 m_timer_interrupt_mask;
|
||||
UINT8 m_timer_interrupt_status;
|
||||
UINT8 m_ctimer_interrupt_status;
|
||||
UINT8 m_ON_interrupt_mask;
|
||||
UINT8 m_ON_interrupt_status;
|
||||
UINT8 m_ON_pressed;
|
||||
UINT8 m_flash_unlocked;
|
||||
UINT8 m_ti8x_memory_page_0;
|
||||
UINT8 m_ti8x_memory_page_1;
|
||||
UINT8 m_ti8x_memory_page_2;
|
||||
UINT8 m_ti8x_memory_page_3;
|
||||
UINT8 m_LCD_mask;
|
||||
UINT8 m_power_mode;
|
||||
UINT8 m_cpu_speed;
|
||||
UINT8 m_keypad_mask;
|
||||
UINT8 m_video_buffer_width;
|
||||
UINT8 m_interrupt_speed;
|
||||
@ -51,6 +102,7 @@ public:
|
||||
UINT8 m_white_out;
|
||||
UINT8 m_ti8x_port2;
|
||||
UINT8 m_ti83p_port4;
|
||||
UINT8 m_ti83pse_port21;
|
||||
int m_ti_video_memory_size;
|
||||
int m_ti_screen_x_size;
|
||||
int m_ti_screen_y_size;
|
||||
@ -80,11 +132,18 @@ public:
|
||||
DECLARE_WRITE8_MEMBER(ti83_port_0002_w);
|
||||
DECLARE_WRITE8_MEMBER(ti83_port_0003_w);
|
||||
DECLARE_WRITE8_MEMBER(ti8x_plus_serial_w);
|
||||
DECLARE_WRITE8_MEMBER(ti83p_port_0002_w);
|
||||
DECLARE_WRITE8_MEMBER(ti83p_port_0003_w);
|
||||
DECLARE_WRITE8_MEMBER(ti83p_int_mask_w);
|
||||
DECLARE_WRITE8_MEMBER(ti83p_port_0004_w);
|
||||
DECLARE_WRITE8_MEMBER(ti83p_port_0006_w);
|
||||
DECLARE_WRITE8_MEMBER(ti83p_port_0007_w);
|
||||
DECLARE_WRITE8_MEMBER(ti83pse_int_ack_w);
|
||||
DECLARE_WRITE8_MEMBER(ti83pse_port_0004_w);
|
||||
DECLARE_WRITE8_MEMBER(ti83pse_port_0005_w);
|
||||
DECLARE_WRITE8_MEMBER(ti83pse_port_0006_w);
|
||||
DECLARE_WRITE8_MEMBER(ti83pse_port_0007_w);
|
||||
DECLARE_WRITE8_MEMBER(ti83p_port_0014_w);
|
||||
DECLARE_WRITE8_MEMBER(ti83pse_port_0020_w);
|
||||
DECLARE_WRITE8_MEMBER(ti83pse_port_0021_w);
|
||||
DECLARE_READ8_MEMBER( ti85_port_0002_r );
|
||||
DECLARE_READ8_MEMBER( ti85_port_0003_r );
|
||||
DECLARE_READ8_MEMBER( ti85_port_0004_r );
|
||||
@ -94,22 +153,69 @@ public:
|
||||
DECLARE_READ8_MEMBER( ti83_port_0002_r );
|
||||
DECLARE_READ8_MEMBER( ti83_port_0003_r );
|
||||
DECLARE_READ8_MEMBER( ti83p_port_0002_r );
|
||||
DECLARE_READ8_MEMBER( ti83p_port_0004_r );
|
||||
DECLARE_READ8_MEMBER( ti83pse_port_0002_r );
|
||||
DECLARE_READ8_MEMBER( ti83pse_port_0005_r );
|
||||
DECLARE_READ8_MEMBER( ti83pse_port_0009_r );
|
||||
DECLARE_READ8_MEMBER( ti83pse_port_0015_r );
|
||||
DECLARE_READ8_MEMBER( ti83pse_port_0020_r );
|
||||
DECLARE_READ8_MEMBER( ti83pse_port_0021_r );
|
||||
DECLARE_READ8_MEMBER( ti84pse_port_0055_r );
|
||||
DECLARE_READ8_MEMBER( ti84pse_port_0056_r );
|
||||
virtual void machine_start();
|
||||
virtual void video_start();
|
||||
DECLARE_PALETTE_INIT(ti85);
|
||||
DECLARE_MACHINE_RESET(ti85);
|
||||
DECLARE_MACHINE_RESET(ti83p);
|
||||
DECLARE_MACHINE_RESET(ti83pse);
|
||||
DECLARE_PALETTE_INIT(ti82);
|
||||
DECLARE_MACHINE_START(ti86);
|
||||
DECLARE_MACHINE_START(ti83p);
|
||||
DECLARE_MACHINE_START(ti83pse);
|
||||
UINT32 screen_update_ti85(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
|
||||
TIMER_CALLBACK_MEMBER(ti85_timer_callback);
|
||||
TIMER_CALLBACK_MEMBER(ti83_timer1_callback);
|
||||
TIMER_CALLBACK_MEMBER(ti83_timer2_callback);
|
||||
|
||||
//crystal timers
|
||||
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
|
||||
void ti83pse_count( UINT8 timer, UINT8 data);
|
||||
|
||||
emu_timer *m_crystal_timer1;
|
||||
emu_timer *m_crystal_timer2;
|
||||
emu_timer *m_crystal_timer3;
|
||||
DECLARE_READ8_MEMBER( ti83pse_ctimer1_setup_r );
|
||||
DECLARE_WRITE8_MEMBER( ti83pse_ctimer1_setup_w );
|
||||
DECLARE_READ8_MEMBER( ti83pse_ctimer1_loop_r );
|
||||
DECLARE_WRITE8_MEMBER( ti83pse_ctimer1_loop_w );
|
||||
DECLARE_READ8_MEMBER( ti83pse_ctimer1_count_r );
|
||||
DECLARE_WRITE8_MEMBER( ti83pse_ctimer1_count_w );
|
||||
DECLARE_READ8_MEMBER( ti83pse_ctimer2_setup_r );
|
||||
DECLARE_WRITE8_MEMBER( ti83pse_ctimer2_setup_w );
|
||||
DECLARE_READ8_MEMBER( ti83pse_ctimer2_loop_r );
|
||||
DECLARE_WRITE8_MEMBER( ti83pse_ctimer2_loop_w );
|
||||
DECLARE_READ8_MEMBER( ti83pse_ctimer2_count_r );
|
||||
DECLARE_WRITE8_MEMBER( ti83pse_ctimer2_count_w );
|
||||
DECLARE_READ8_MEMBER( ti83pse_ctimer3_setup_r );
|
||||
DECLARE_WRITE8_MEMBER( ti83pse_ctimer3_setup_w );
|
||||
DECLARE_READ8_MEMBER( ti83pse_ctimer3_loop_r );
|
||||
DECLARE_WRITE8_MEMBER( ti83pse_ctimer3_loop_w );
|
||||
DECLARE_READ8_MEMBER( ti83pse_ctimer3_count_r );
|
||||
DECLARE_WRITE8_MEMBER( ti83pse_ctimer3_count_w );
|
||||
|
||||
|
||||
void update_ti85_memory ();
|
||||
void update_ti83p_memory ();
|
||||
void update_ti83pse_memory ();
|
||||
void update_ti86_memory ();
|
||||
void ti8x_snapshot_setup_registers (UINT8 * data);
|
||||
void ti85_setup_snapshot (UINT8 * data);
|
||||
void ti86_setup_snapshot (UINT8 * data);
|
||||
DECLARE_SNAPSHOT_LOAD_MEMBER( ti8x );
|
||||
|
||||
ti83pse_timer m_ctimer[3];
|
||||
|
||||
//address_space &asic;
|
||||
};
|
||||
|
||||
#endif /* TI85_H_ */
|
||||
|
||||
@ -14,7 +14,6 @@
|
||||
#define TI85_SNAPSHOT_SIZE 32976
|
||||
#define TI86_SNAPSHOT_SIZE 131284
|
||||
|
||||
|
||||
TIMER_CALLBACK_MEMBER(ti85_state::ti85_timer_callback)
|
||||
{
|
||||
if (ioport("ON")->read() & 0x01)
|
||||
@ -23,7 +22,7 @@ TIMER_CALLBACK_MEMBER(ti85_state::ti85_timer_callback)
|
||||
{
|
||||
m_maincpu->set_input_line(0, HOLD_LINE);
|
||||
m_ON_interrupt_status = 1;
|
||||
if (!m_timer_interrupt_mask) m_timer_interrupt_mask = 1;
|
||||
if (!m_timer_interrupt_mask) m_timer_interrupt_mask = 2;
|
||||
}
|
||||
m_ON_pressed = 1;
|
||||
return;
|
||||
@ -33,7 +32,102 @@ TIMER_CALLBACK_MEMBER(ti85_state::ti85_timer_callback)
|
||||
if (m_timer_interrupt_mask)
|
||||
{
|
||||
m_maincpu->set_input_line(0, HOLD_LINE);
|
||||
m_timer_interrupt_status = 1;
|
||||
m_timer_interrupt_status = m_timer_interrupt_mask;
|
||||
}
|
||||
}
|
||||
|
||||
TIMER_CALLBACK_MEMBER(ti85_state::ti83_timer1_callback)
|
||||
{
|
||||
if (ioport("ON")->read() & 0x01)
|
||||
{
|
||||
if (m_ON_interrupt_mask && !m_ON_pressed)
|
||||
{
|
||||
m_maincpu->set_input_line(0, HOLD_LINE);
|
||||
m_ON_interrupt_status = 1;
|
||||
}
|
||||
m_ON_pressed = 1;
|
||||
return;
|
||||
}
|
||||
else
|
||||
{
|
||||
m_ON_pressed = 0;
|
||||
}
|
||||
if (m_timer_interrupt_mask & 2)
|
||||
{
|
||||
m_maincpu->set_input_line(0, HOLD_LINE);
|
||||
m_timer_interrupt_status = m_timer_interrupt_status | 2;
|
||||
}
|
||||
}
|
||||
|
||||
TIMER_CALLBACK_MEMBER(ti85_state::ti83_timer2_callback)
|
||||
{
|
||||
if (m_timer_interrupt_mask & 4)
|
||||
{
|
||||
m_maincpu->set_input_line(0, HOLD_LINE);
|
||||
m_timer_interrupt_status = m_timer_interrupt_status | 4;
|
||||
}
|
||||
}
|
||||
|
||||
void ti85_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
|
||||
{
|
||||
switch (id)
|
||||
{
|
||||
case CRYSTAL_TIMER3:
|
||||
case CRYSTAL_TIMER2:
|
||||
case CRYSTAL_TIMER1:
|
||||
if (m_ctimer[id].count)
|
||||
{
|
||||
m_ctimer[id].count--;
|
||||
if (!m_ctimer[id].count)
|
||||
{
|
||||
if (!(m_ctimer[id].loop & 4))
|
||||
{
|
||||
if (!(m_ctimer[id].loop & 1))
|
||||
{
|
||||
m_ctimer[id].setup = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
ti83pse_count(id, m_ctimer[id].max);
|
||||
}
|
||||
if (!(m_ctimer[id].loop & 2))
|
||||
{
|
||||
//generate interrupt
|
||||
m_ctimer_interrupt_status |= (0x20 << id);
|
||||
m_maincpu->set_input_line(0, HOLD_LINE);
|
||||
}
|
||||
m_ctimer[id].loop &= 2;
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
case HW_TIMER1:
|
||||
if (ioport("ON")->read() & 0x01)
|
||||
{
|
||||
if (m_ON_interrupt_mask && !m_ON_pressed)
|
||||
{
|
||||
m_maincpu->set_input_line(0, HOLD_LINE);
|
||||
m_ON_interrupt_status = 1;
|
||||
}
|
||||
m_ON_pressed = 1;
|
||||
return;
|
||||
}
|
||||
else
|
||||
{
|
||||
m_ON_pressed = 0;
|
||||
}
|
||||
if (m_timer_interrupt_mask & 2)
|
||||
{
|
||||
m_maincpu->set_input_line(0, HOLD_LINE);
|
||||
m_timer_interrupt_status = m_timer_interrupt_status | 2;
|
||||
}
|
||||
break;
|
||||
case HW_TIMER2:
|
||||
if (m_timer_interrupt_mask & 4)
|
||||
{
|
||||
m_maincpu->set_input_line(0, HOLD_LINE);
|
||||
m_timer_interrupt_status = m_timer_interrupt_status | 4;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -59,22 +153,56 @@ void ti85_state::update_ti83p_memory ()
|
||||
{
|
||||
address_space &space = m_maincpu->space(AS_PROGRAM);
|
||||
|
||||
if (m_ti8x_memory_page_1 & 0x40)
|
||||
m_membank1->set_bank(0); //Always flash page 0, well allmost
|
||||
|
||||
if (m_ti83p_port4 & 1)
|
||||
{
|
||||
ti8x_update_bank(space, (m_ti83p_port4 & 1) ? 2 : 1, m_ti8x_ram, m_ti8x_memory_page_1 & 0x01, true);
|
||||
}
|
||||
else
|
||||
{
|
||||
ti8x_update_bank(space, (m_ti83p_port4 & 1) ? 2 : 1, m_bios, m_ti8x_memory_page_1 & 0x1f, false);
|
||||
}
|
||||
|
||||
m_membank2->set_bank(m_ti8x_memory_page_1 & 0xfe);
|
||||
|
||||
if (m_ti8x_memory_page_2 & 0x40)
|
||||
{
|
||||
ti8x_update_bank(space, (m_ti83p_port4 & 1) ? 3 : 2, m_ti8x_ram, m_ti8x_memory_page_2 & 0x01, true);
|
||||
m_membank3->set_bank(m_ti8x_memory_page_1);
|
||||
|
||||
m_membank4->set_bank(m_ti8x_memory_page_2);
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
ti8x_update_bank(space, (m_ti83p_port4 & 1) ? 3 : 2, m_bios, m_ti8x_memory_page_2 & 0x1f, false);
|
||||
|
||||
m_membank2->set_bank(m_ti8x_memory_page_1);
|
||||
|
||||
m_membank3->set_bank(m_ti8x_memory_page_2);
|
||||
|
||||
m_membank4->set_bank(0x40); //Always first ram page
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
void ti85_state::update_ti83pse_memory ()
|
||||
{
|
||||
address_space &space = m_maincpu->space(AS_PROGRAM);
|
||||
|
||||
m_membank1->set_bank(m_ti8x_memory_page_0);
|
||||
|
||||
if (m_ti83p_port4 & 1)
|
||||
{
|
||||
|
||||
m_membank2->set_bank(m_ti8x_memory_page_1 & 0xfe);
|
||||
|
||||
m_membank3->set_bank(m_ti8x_memory_page_1 | 1);
|
||||
|
||||
m_membank4->set_bank(m_ti8x_memory_page_2);
|
||||
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
m_membank2->set_bank(m_ti8x_memory_page_1);
|
||||
|
||||
m_membank3->set_bank(m_ti8x_memory_page_2);
|
||||
|
||||
m_membank4->set_bank(m_ti8x_memory_page_3 + 0x80);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
@ -127,7 +255,7 @@ void ti85_state::machine_start()
|
||||
m_port4_bit0 = 0;
|
||||
m_ti81_port_7_data = 0;
|
||||
|
||||
machine().scheduler().timer_pulse(attotime::from_hz(200), timer_expired_delegate(FUNC(ti85_state::ti85_timer_callback),this));
|
||||
machine().scheduler().timer_pulse(attotime::from_hz(256), timer_expired_delegate(FUNC(ti85_state::ti85_timer_callback),this));
|
||||
|
||||
space.unmap_write(0x0000, 0x3fff);
|
||||
space.unmap_write(0x4000, 0x7fff);
|
||||
@ -142,19 +270,52 @@ MACHINE_RESET_MEMBER(ti85_state,ti85)
|
||||
m_PCR = 0xc0;
|
||||
}
|
||||
|
||||
MACHINE_RESET_MEMBER(ti85_state,ti83p)
|
||||
{
|
||||
m_red_out = 0x00;
|
||||
m_white_out = 0x00;
|
||||
m_PCR = 0xc0;
|
||||
|
||||
m_ti8x_memory_page_0 = 0;//0x1f;
|
||||
m_ti8x_memory_page_1 = 0x1f;
|
||||
m_ti8x_memory_page_2 = 0;
|
||||
m_ti8x_memory_page_3 = 0;
|
||||
m_ti83p_port4 = 1;
|
||||
update_ti83p_memory();
|
||||
|
||||
m_maincpu->set_pc(0x8000);
|
||||
}
|
||||
|
||||
MACHINE_RESET_MEMBER(ti85_state,ti83pse)
|
||||
{
|
||||
m_red_out = 0x00;
|
||||
m_white_out = 0x00;
|
||||
m_PCR = 0xc0;
|
||||
|
||||
m_ti8x_memory_page_0 = 0;//0x1f;
|
||||
m_ti8x_memory_page_1 = 0x7f;
|
||||
m_ti8x_memory_page_2 = 0;
|
||||
m_ti8x_memory_page_3 = 0;
|
||||
m_ti83p_port4 = 1;
|
||||
update_ti83pse_memory();
|
||||
|
||||
m_maincpu->set_pc(0x8000);
|
||||
}
|
||||
|
||||
MACHINE_START_MEMBER(ti85_state,ti83p)
|
||||
{
|
||||
address_space &space = m_maincpu->space(AS_PROGRAM);
|
||||
m_bios = memregion("bios")->base();
|
||||
//m_bios = memregion("flash")->base();
|
||||
|
||||
m_timer_interrupt_mask = 0;
|
||||
m_timer_interrupt_status = 0;
|
||||
m_ON_interrupt_mask = 0;
|
||||
m_ON_interrupt_status = 0;
|
||||
m_ON_pressed = 0;
|
||||
m_ti8x_memory_page_1 = 0;
|
||||
m_ti8x_memory_page_0 = 0;//0x1f;
|
||||
m_ti8x_memory_page_1 = 0x1f;
|
||||
m_ti8x_memory_page_2 = 0;
|
||||
m_ti8x_memory_page_3 = 0;
|
||||
m_LCD_memory_base = 0;
|
||||
m_LCD_status = 0;
|
||||
m_LCD_mask = 0;
|
||||
@ -162,24 +323,68 @@ MACHINE_START_MEMBER(ti85_state,ti83p)
|
||||
m_keypad_mask = 0;
|
||||
m_video_buffer_width = 0;
|
||||
m_interrupt_speed = 0;
|
||||
m_port4_bit0 = 0;
|
||||
m_ti83p_port4 = 1;
|
||||
m_flash_unlocked = 0;
|
||||
|
||||
m_ti8x_ram = auto_alloc_array(machine(), UINT8, 32*1024);
|
||||
memset(m_ti8x_ram, 0, sizeof(UINT8)*32*1024);
|
||||
ti85_state::update_ti83p_memory ();
|
||||
|
||||
space.unmap_write(0x0000, 0x3fff);
|
||||
space.unmap_write(0x4000, 0x7fff);
|
||||
space.unmap_write(0x8000, 0xbfff);
|
||||
machine().scheduler().timer_pulse(attotime::from_hz(256), timer_expired_delegate(FUNC(ti85_state::ti83_timer1_callback),this));
|
||||
machine().scheduler().timer_pulse(attotime::from_hz(512), timer_expired_delegate(FUNC(ti85_state::ti83_timer2_callback),this));
|
||||
|
||||
membank("bank1")->set_base(m_bios);
|
||||
membank("bank2")->set_base(m_bios);
|
||||
membank("bank3")->set_base(m_bios);
|
||||
membank("bank4")->set_base(m_ti8x_ram);
|
||||
machine().device<nvram_device>("nvram")->set_base(m_ti8x_ram, sizeof(UINT8)*32*1024);
|
||||
|
||||
machine().scheduler().timer_pulse(attotime::from_hz(200), timer_expired_delegate(FUNC(ti85_state::ti85_timer_callback),this));
|
||||
/* save states and debugging */
|
||||
save_item(NAME(m_timer_interrupt_mask));
|
||||
save_item(NAME(m_ti8x_memory_page_0));
|
||||
save_item(NAME(m_ti8x_memory_page_1));
|
||||
save_item(NAME(m_ti8x_memory_page_2));
|
||||
save_item(NAME(m_ti8x_memory_page_3));
|
||||
save_item(NAME(m_ti83p_port4));
|
||||
}
|
||||
|
||||
MACHINE_START_MEMBER(ti85_state,ti83pse)
|
||||
{
|
||||
address_space &space = m_maincpu->space(AS_PROGRAM);
|
||||
//address_space &asic = ADDRESS_MAP_NAME(ti83p_asic_mem);
|
||||
|
||||
m_timer_interrupt_mask = 0;
|
||||
m_timer_interrupt_status = 0;
|
||||
m_ctimer_interrupt_status = 0;
|
||||
m_ON_interrupt_mask = 0;
|
||||
m_ON_interrupt_status = 0;
|
||||
m_ON_pressed = 0;
|
||||
m_ti8x_memory_page_0 = 00;//0x7f;
|
||||
m_ti8x_memory_page_1 = 0x7f;
|
||||
m_ti8x_memory_page_2 = 0;
|
||||
m_ti8x_memory_page_3 = 0;
|
||||
m_LCD_memory_base = 0;
|
||||
m_LCD_status = 0;
|
||||
m_LCD_mask = 0;
|
||||
m_power_mode = 0;
|
||||
m_keypad_mask = 0;
|
||||
m_video_buffer_width = 0;
|
||||
m_interrupt_speed = 0;
|
||||
m_ti83p_port4 = 1;
|
||||
m_flash_unlocked = 0;
|
||||
|
||||
ti85_state::update_ti83p_memory();
|
||||
m_maincpu->set_pc(0x8000);
|
||||
|
||||
|
||||
machine().scheduler().timer_pulse(attotime::from_hz(256), timer_expired_delegate(FUNC(ti85_state::ti83_timer1_callback),this));
|
||||
machine().scheduler().timer_pulse(attotime::from_hz(512), timer_expired_delegate(FUNC(ti85_state::ti83_timer2_callback),this));
|
||||
|
||||
m_crystal_timer1 = timer_alloc(CRYSTAL_TIMER1);
|
||||
m_crystal_timer2 = timer_alloc(CRYSTAL_TIMER2);
|
||||
m_crystal_timer3 = timer_alloc(CRYSTAL_TIMER3);
|
||||
|
||||
/* save states and debugging */
|
||||
save_item(NAME(m_ctimer_interrupt_status));
|
||||
save_item(NAME(m_timer_interrupt_status));
|
||||
save_item(NAME(m_ti8x_memory_page_0));
|
||||
save_item(NAME(m_ti8x_memory_page_1));
|
||||
save_item(NAME(m_ti8x_memory_page_2));
|
||||
save_item(NAME(m_ti8x_memory_page_3));
|
||||
save_item(NAME(m_ti83p_port4));
|
||||
}
|
||||
|
||||
MACHINE_START_MEMBER(ti85_state,ti86)
|
||||
{
|
||||
@ -213,7 +418,7 @@ MACHINE_START_MEMBER(ti85_state,ti86)
|
||||
membank("bank4")->set_base(m_ti8x_ram);
|
||||
machine().device<nvram_device>("nvram")->set_base(m_ti8x_ram, sizeof(UINT8)*128*1024);
|
||||
|
||||
machine().scheduler().timer_pulse(attotime::from_hz(200), timer_expired_delegate(FUNC(ti85_state::ti85_timer_callback),this));
|
||||
machine().scheduler().timer_pulse(attotime::from_hz(256), timer_expired_delegate(FUNC(ti85_state::ti85_timer_callback),this));
|
||||
}
|
||||
|
||||
|
||||
@ -309,6 +514,11 @@ READ8_MEMBER(ti85_state::ti86_port_0006_r )
|
||||
return m_ti8x_memory_page_2;
|
||||
}
|
||||
|
||||
READ8_MEMBER(ti85_state::ti83pse_port_0005_r )
|
||||
{
|
||||
return m_ti8x_memory_page_3;
|
||||
}
|
||||
|
||||
READ8_MEMBER(ti85_state::ti83_port_0000_r)
|
||||
{
|
||||
return ((m_ti8x_memory_page_1 & 0x08) << 1) | 0x0C;
|
||||
@ -323,14 +533,13 @@ READ8_MEMBER(ti85_state::ti83_port_0003_r )
|
||||
{
|
||||
int data = 0;
|
||||
|
||||
data |= m_LCD_mask;
|
||||
|
||||
if (m_ON_interrupt_status)
|
||||
data |= 0x01;
|
||||
if (!m_ON_pressed)
|
||||
data |= 0x08;
|
||||
m_ON_interrupt_status = 0;
|
||||
m_timer_interrupt_status = 0;
|
||||
|
||||
data |= m_timer_interrupt_status;
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
@ -350,6 +559,50 @@ READ8_MEMBER(ti85_state::ti83p_port_0002_r )
|
||||
return m_ti8x_port2|3;
|
||||
}
|
||||
|
||||
READ8_MEMBER(ti85_state::ti83p_port_0004_r )
|
||||
{
|
||||
int data = 0;
|
||||
|
||||
//data |= m_LCD_mask;
|
||||
|
||||
if (m_ON_interrupt_status)
|
||||
data |= 0x01;
|
||||
if (!m_ON_pressed)
|
||||
data |= 0x08;
|
||||
|
||||
data |= m_timer_interrupt_status;
|
||||
|
||||
data |= m_ctimer_interrupt_status;
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
//------------------------
|
||||
// bit 0 - battery test (not implemented)
|
||||
// Bit 1 - LCD wait
|
||||
// bit 2 - flash lock
|
||||
// bit 3 - not used
|
||||
// bit 4 - not used
|
||||
// bit 5 - Set if USB hardware is present
|
||||
// bit 6 - Indicates if Link Assist is available
|
||||
// bit 7 - SE or Basic
|
||||
|
||||
READ8_MEMBER(ti85_state::ti83pse_port_0002_r )
|
||||
{
|
||||
return 0xC3 | (m_flash_unlocked << 2);
|
||||
}
|
||||
|
||||
READ8_MEMBER(ti85_state::ti83pse_port_0009_r )
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
READ8_MEMBER(ti85_state::ti83pse_port_0015_r )
|
||||
{
|
||||
return 0x33;
|
||||
}
|
||||
|
||||
|
||||
WRITE8_MEMBER(ti85_state::ti81_port_0007_w)
|
||||
{
|
||||
m_ti81_port_7_data = data;
|
||||
@ -460,31 +713,28 @@ WRITE8_MEMBER(ti85_state::ti8x_plus_serial_w)
|
||||
m_PCR = data & 0xf0;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ti85_state::ti83p_port_0002_w)
|
||||
WRITE8_MEMBER(ti85_state::ti83pse_int_ack_w)
|
||||
{
|
||||
m_ti8x_port2 = data;
|
||||
//Lets ignore this for now, I think it'll be fine.
|
||||
m_ON_interrupt_status = data & 1;
|
||||
m_timer_interrupt_status = data & 0x06;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ti85_state::ti83p_port_0003_w)
|
||||
WRITE8_MEMBER(ti85_state::ti83p_int_mask_w)
|
||||
{
|
||||
m_LCD_mask = (data&0x08) >> 2;
|
||||
//m_LCD_mask = (data&0x08) >> 2;
|
||||
m_ON_interrupt_mask = data & 0x01;
|
||||
m_ON_interrupt_status &= m_ON_interrupt_mask;
|
||||
|
||||
m_timer_interrupt_mask = data & 0x06;
|
||||
|
||||
m_timer_interrupt_status &= m_timer_interrupt_mask;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ti85_state::ti83p_port_0004_w)
|
||||
{
|
||||
if ((data & 1) && !(m_ti83p_port4 & 1))
|
||||
{
|
||||
m_ti8x_memory_page_1 = 0x1f;
|
||||
m_ti8x_memory_page_2 = 0x1f;
|
||||
}
|
||||
else if (!(data & 1) && (m_ti83p_port4 & 1))
|
||||
{
|
||||
m_ti8x_memory_page_1 = 0x1f;
|
||||
m_ti8x_memory_page_2 = 0x40;
|
||||
}
|
||||
m_ti83p_port4 = data | 0xe0;
|
||||
update_ti83p_memory();
|
||||
m_ti83p_port4 = data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ti85_state::ti83p_port_0006_w)
|
||||
@ -499,6 +749,234 @@ WRITE8_MEMBER(ti85_state::ti83p_port_0007_w)
|
||||
update_ti83p_memory();
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ti85_state::ti83pse_port_0004_w)
|
||||
{
|
||||
m_ti83p_port4 = data;
|
||||
update_ti83pse_memory();
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ti85_state::ti83pse_port_0005_w)
|
||||
{
|
||||
m_ti8x_memory_page_3 = data & 0x07;
|
||||
update_ti83pse_memory();
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ti85_state::ti83pse_port_0006_w)
|
||||
{
|
||||
m_ti8x_memory_page_1 = data; //& ((data&0x80) ? 0x41 : 0x7f);
|
||||
update_ti83pse_memory();
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ti85_state::ti83pse_port_0007_w)
|
||||
{
|
||||
m_ti8x_memory_page_2 = data; //& ((data&0x80) ? 0x41 : 0x7f);
|
||||
update_ti83pse_memory();
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ti85_state::ti83p_port_0014_w)
|
||||
{
|
||||
m_flash_unlocked = data;
|
||||
update_ti83pse_memory();
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ti85_state::ti83pse_port_0020_w)
|
||||
{
|
||||
m_cpu_speed = data;
|
||||
if(data)
|
||||
{
|
||||
m_maincpu->set_unscaled_clock(15000000);
|
||||
}
|
||||
else
|
||||
{
|
||||
m_maincpu->set_unscaled_clock(6000000);
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER(ti85_state::ti83pse_port_0020_r)
|
||||
{
|
||||
return m_cpu_speed;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ti85_state::ti83pse_port_0021_w)
|
||||
{
|
||||
m_ti83pse_port21 = data & 0x0f;
|
||||
}
|
||||
|
||||
READ8_MEMBER(ti85_state::ti83pse_port_0021_r)
|
||||
{
|
||||
return m_ti83pse_port21;
|
||||
}
|
||||
|
||||
READ8_MEMBER(ti85_state::ti84pse_port_0055_r)
|
||||
{
|
||||
return 0x1f;
|
||||
}
|
||||
|
||||
READ8_MEMBER(ti85_state::ti84pse_port_0056_r)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
//timer ports
|
||||
|
||||
void ti85_state::ti83pse_count( UINT8 timer, UINT8 data)
|
||||
{
|
||||
m_ctimer[timer].max = m_ctimer[timer].count = data;
|
||||
|
||||
if (m_ctimer[timer].setup)
|
||||
{
|
||||
switch (m_ctimer[timer].setup & 0x07)
|
||||
{
|
||||
case 0x00:
|
||||
m_ctimer[timer].divsor = 3.0;
|
||||
break;
|
||||
case 0x01:
|
||||
m_ctimer[timer].divsor = 32.0;
|
||||
break;
|
||||
case 0x02:
|
||||
m_ctimer[timer].divsor = 327.000;
|
||||
break;
|
||||
case 0x03:
|
||||
m_ctimer[timer].divsor = 3276.00;
|
||||
break;
|
||||
case 0x04:
|
||||
m_ctimer[timer].divsor = 1.0;
|
||||
break;
|
||||
case 0x05:
|
||||
m_ctimer[timer].divsor = 16.0;
|
||||
break;
|
||||
case 0x06:
|
||||
m_ctimer[timer].divsor = 256.0;
|
||||
break;
|
||||
case 0x07:
|
||||
m_ctimer[timer].divsor = 4096.0;
|
||||
break;
|
||||
}
|
||||
switch (timer)
|
||||
{
|
||||
case CRYSTAL_TIMER1:
|
||||
m_crystal_timer1->adjust(attotime::zero, 0, attotime::from_hz( 32768.0/m_ctimer[timer].divsor));
|
||||
m_crystal_timer1->enable(true);
|
||||
break;
|
||||
case CRYSTAL_TIMER2:
|
||||
m_crystal_timer2->adjust(attotime::zero, 0, attotime::from_hz( 32768.0/m_ctimer[timer].divsor));
|
||||
m_crystal_timer2->enable(true);
|
||||
break;
|
||||
case CRYSTAL_TIMER3:
|
||||
m_crystal_timer3->adjust(attotime::zero, 0, attotime::from_hz( 32768.0/m_ctimer[timer].divsor));
|
||||
m_crystal_timer3->enable(true);
|
||||
break;
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
READ8_MEMBER(ti85_state::ti83pse_ctimer1_setup_r)
|
||||
{
|
||||
return m_ctimer[CRYSTAL_TIMER1].setup;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ti85_state::ti83pse_ctimer1_setup_w)
|
||||
{
|
||||
m_crystal_timer1->enable(false);
|
||||
m_ctimer[CRYSTAL_TIMER1].setup = data;
|
||||
}
|
||||
|
||||
READ8_MEMBER(ti85_state::ti83pse_ctimer1_loop_r)
|
||||
{
|
||||
return m_ctimer[CRYSTAL_TIMER1].loop;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ti85_state::ti83pse_ctimer1_loop_w)
|
||||
{
|
||||
m_ctimer[CRYSTAL_TIMER1].loop = data & 0x03;
|
||||
m_ctimer_interrupt_status = 0;
|
||||
}
|
||||
|
||||
READ8_MEMBER(ti85_state::ti83pse_ctimer1_count_r)
|
||||
{
|
||||
return m_ctimer[CRYSTAL_TIMER1].count;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ti85_state::ti83pse_ctimer1_count_w)
|
||||
{
|
||||
ti83pse_count(CRYSTAL_TIMER1, data);
|
||||
|
||||
}
|
||||
|
||||
//
|
||||
|
||||
READ8_MEMBER(ti85_state::ti83pse_ctimer2_setup_r)
|
||||
{
|
||||
return m_ctimer[CRYSTAL_TIMER2].setup;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ti85_state::ti83pse_ctimer2_setup_w)
|
||||
{
|
||||
m_crystal_timer2->enable(false);
|
||||
m_ctimer[CRYSTAL_TIMER2].setup = data;
|
||||
}
|
||||
|
||||
READ8_MEMBER(ti85_state::ti83pse_ctimer2_loop_r)
|
||||
{
|
||||
return m_ctimer[CRYSTAL_TIMER2].loop;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ti85_state::ti83pse_ctimer2_loop_w)
|
||||
{
|
||||
m_ctimer[CRYSTAL_TIMER2].loop = data & 0x03;
|
||||
m_ctimer_interrupt_status = 0;
|
||||
}
|
||||
|
||||
READ8_MEMBER(ti85_state::ti83pse_ctimer2_count_r)
|
||||
{
|
||||
return m_ctimer[CRYSTAL_TIMER2].count;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ti85_state::ti83pse_ctimer2_count_w)
|
||||
{
|
||||
ti83pse_count(CRYSTAL_TIMER2, data);
|
||||
|
||||
}
|
||||
|
||||
//
|
||||
|
||||
READ8_MEMBER(ti85_state::ti83pse_ctimer3_setup_r)
|
||||
{
|
||||
return m_ctimer[CRYSTAL_TIMER3].setup;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ti85_state::ti83pse_ctimer3_setup_w)
|
||||
{
|
||||
m_crystal_timer3->enable(false);
|
||||
m_ctimer[CRYSTAL_TIMER3].setup = data;
|
||||
}
|
||||
|
||||
READ8_MEMBER(ti85_state::ti83pse_ctimer3_loop_r)
|
||||
{
|
||||
return m_ctimer[CRYSTAL_TIMER3].loop;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ti85_state::ti83pse_ctimer3_loop_w)
|
||||
{
|
||||
m_ctimer[CRYSTAL_TIMER3].loop = data & 0x03;
|
||||
m_ctimer_interrupt_status = 0;
|
||||
}
|
||||
|
||||
READ8_MEMBER(ti85_state::ti83pse_ctimer3_count_r)
|
||||
{
|
||||
return m_ctimer[CRYSTAL_TIMER3].count;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ti85_state::ti83pse_ctimer3_count_w)
|
||||
{
|
||||
ti83pse_count(CRYSTAL_TIMER3, data);
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
/***************************************************************************
|
||||
TI calculators snapshot files (SAV)
|
||||
***************************************************************************/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user