mirror of
https://github.com/holub/mame
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arm7.c: Modernized cpu core. (nw)
This commit is contained in:
Wilbert Pol
parent
1e12a504fd
commit
0a71ecb681
2
.gitattributes
vendored
2
.gitattributes
vendored
@ -378,10 +378,8 @@ src/emu/cpu/arm7/arm7dasm.c svneol=native#text/plain
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src/emu/cpu/arm7/arm7drc.c svneol=native#text/plain
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src/emu/cpu/arm7/arm7help.h svneol=native#text/plain
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src/emu/cpu/arm7/arm7ops.c svneol=native#text/plain
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src/emu/cpu/arm7/arm7ops.h svneol=native#text/plain
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src/emu/cpu/arm7/arm7tdrc.c svneol=native#text/plain
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src/emu/cpu/arm7/arm7thmb.c svneol=native#text/plain
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src/emu/cpu/arm7/arm7thmb.h svneol=native#text/plain
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src/emu/cpu/asap/asap.c svneol=native#text/plain
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src/emu/cpu/asap/asap.h svneol=native#text/plain
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src/emu/cpu/asap/asapdasm.c svneol=native#text/plain
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File diff suppressed because it is too large
Load Diff
@ -33,6 +33,10 @@
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#ifndef __ARM7_H__
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#define __ARM7_H__
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#include "cpu/drcfe.h"
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#include "cpu/drcuml.h"
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#include "cpu/drcumlsh.h"
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#define ARM7_MAX_FASTRAM 4
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#define ARM7_MAX_HOTSPOTS 16
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@ -68,12 +72,506 @@ enum
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* PUBLIC FUNCTIONS
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***************************************************************************************************/
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DECLARE_LEGACY_CPU_DEVICE(ARM7, arm7);
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DECLARE_LEGACY_CPU_DEVICE(ARM7_BE, arm7_be);
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DECLARE_LEGACY_CPU_DEVICE(ARM7500, arm7500);
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DECLARE_LEGACY_CPU_DEVICE(ARM9, arm9);
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DECLARE_LEGACY_CPU_DEVICE(ARM920T, arm920t);
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DECLARE_LEGACY_CPU_DEVICE(PXA255, pxa255);
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DECLARE_LEGACY_CPU_DEVICE(SA1110, sa1110);
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class arm7_cpu_device : public cpu_device
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{
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public:
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// construction/destruction
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arm7_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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arm7_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source, UINT8 archRev, UINT8 archFlags, endianness_t endianness = ENDIANNESS_LITTLE);
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protected:
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// device-level overrides
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virtual void device_start();
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virtual void device_reset();
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// device_execute_interface overrides
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virtual UINT32 execute_min_cycles() const { return 3; }
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virtual UINT32 execute_max_cycles() const { return 4; }
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virtual UINT32 execute_input_lines() const { return 4; } /* There are actually only 2 input lines: we use 3 variants of the ABORT line while there is only 1 real one */
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virtual void execute_run();
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virtual void execute_set_input(int inputnum, int state);
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// device_memory_interface overrides
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virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; }
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virtual bool memory_translate(address_spacenum spacenum, int intention, offs_t &address);
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// device_state_interface overrides
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virtual void state_export(const device_state_entry &entry);
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void state_string_export(const device_state_entry &entry, astring &string);
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// device_disasm_interface overrides
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virtual UINT32 disasm_min_opcode_bytes() const { return 2; }
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virtual UINT32 disasm_max_opcode_bytes() const { return 4; }
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virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
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address_space_config m_program_config;
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UINT32 m_r[/*NUM_REGS*/37];
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UINT32 m_pendingIrq;
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UINT32 m_pendingFiq;
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UINT32 m_pendingAbtD;
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UINT32 m_pendingAbtP;
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UINT32 m_pendingUnd;
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UINT32 m_pendingSwi;
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int m_icount;
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endianness_t m_endian;
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device_irq_acknowledge_callback m_irq_callback;
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address_space *m_program;
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direct_read_data *m_direct;
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/* Coprocessor Registers */
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UINT32 m_control;
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UINT32 m_tlbBase;
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UINT32 m_faultStatus[2];
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UINT32 m_faultAddress;
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UINT32 m_fcsePID;
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UINT32 m_domainAccessControl;
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UINT8 m_archRev; // ARM architecture revision (3, 4, and 5 are valid)
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UINT8 m_archFlags; // architecture flags
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//#if ARM7_MMU_ENABLE_HACK
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// UINT32 mmu_enable_addr; // workaround for "MMU is enabled when PA != VA" problem
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//#endif
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UINT32 m_copro_id;
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// For debugger
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UINT32 m_pc;
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INT64 saturate_qbit_overflow(INT64 res);
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void SwitchMode(UINT32 cpsr_mode_val);
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UINT32 decodeShift(UINT32 insn, UINT32 *pCarry);
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int loadInc(UINT32 pat, UINT32 rbv, UINT32 s, int mode);
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int loadDec(UINT32 pat, UINT32 rbv, UINT32 s, int mode);
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int storeInc(UINT32 pat, UINT32 rbv, int mode);
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int storeDec(UINT32 pat, UINT32 rbv, int mode);
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void HandleCoProcDO(UINT32 insn);
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void HandleCoProcRT(UINT32 insn);
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void HandleCoProcDT(UINT32 insn);
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void HandleBranch(UINT32 insn);
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void HandleMemSingle(UINT32 insn);
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void HandleHalfWordDT(UINT32 insn);
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void HandleSwap(UINT32 insn);
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void HandlePSRTransfer(UINT32 insn);
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void HandleALU(UINT32 insn);
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void HandleMul(UINT32 insn);
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void HandleSMulLong(UINT32 insn);
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void HandleUMulLong(UINT32 insn);
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void HandleMemBlock(UINT32 insn);
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void arm7ops_0123(UINT32 insn);
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void arm7ops_4567(UINT32 insn);
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void arm7ops_89(UINT32 insn);
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void arm7ops_ab(UINT32 insn);
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void arm7ops_cd(UINT32 insn);
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void arm7ops_e(UINT32 insn);
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void arm7ops_f(UINT32 insn);
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void set_cpsr(UINT32 val);
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bool arm7_tlb_translate(offs_t &addr, int flags);
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UINT32 arm7_tlb_get_first_level_descriptor( UINT32 vaddr );
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UINT32 arm7_tlb_get_second_level_descriptor( UINT32 granularity, UINT32 first_desc, UINT32 vaddr );
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int detect_fault(int permission, int ap, int flags);
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void arm7_check_irq_state();
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void arm7_cpu_write32(UINT32 addr, UINT32 data);
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void arm7_cpu_write16(UINT32 addr, UINT16 data);
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void arm7_cpu_write8(UINT32 addr, UINT8 data);
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UINT32 arm7_cpu_read32(UINT32 addr);
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UINT16 arm7_cpu_read16(UINT32 addr);
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UINT8 arm7_cpu_read8(UINT32 addr);
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// Coprocessor support
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DECLARE_WRITE32_MEMBER( arm7_do_callback );
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DECLARE_READ32_MEMBER( arm7_rt_r_callback );
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DECLARE_WRITE32_MEMBER( arm7_rt_w_callback );
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void arm7_dt_r_callback(UINT32 insn, UINT32 *prn);
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void arm7_dt_w_callback(UINT32 insn, UINT32 *prn);
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void tg00_0(UINT32 pc, UINT32 insn);
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void tg00_1(UINT32 pc, UINT32 insn);
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void tg01_0(UINT32 pc, UINT32 insn);
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void tg01_10(UINT32 pc, UINT32 insn);
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void tg01_11(UINT32 pc, UINT32 insn);
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void tg01_12(UINT32 pc, UINT32 insn);
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void tg01_13(UINT32 pc, UINT32 insn);
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void tg02_0(UINT32 pc, UINT32 insn);
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void tg02_1(UINT32 pc, UINT32 insn);
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void tg03_0(UINT32 pc, UINT32 insn);
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void tg03_1(UINT32 pc, UINT32 insn);
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void tg04_00_00(UINT32 pc, UINT32 insn);
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void tg04_00_01(UINT32 pc, UINT32 insn);
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void tg04_00_02(UINT32 pc, UINT32 insn);
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void tg04_00_03(UINT32 pc, UINT32 insn);
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void tg04_00_04(UINT32 pc, UINT32 insn);
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void tg04_00_05(UINT32 pc, UINT32 insn);
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void tg04_00_06(UINT32 pc, UINT32 insn);
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void tg04_00_07(UINT32 pc, UINT32 insn);
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void tg04_00_08(UINT32 pc, UINT32 insn);
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void tg04_00_09(UINT32 pc, UINT32 insn);
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void tg04_00_0a(UINT32 pc, UINT32 insn);
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void tg04_00_0b(UINT32 pc, UINT32 insn);
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void tg04_00_0c(UINT32 pc, UINT32 insn);
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void tg04_00_0d(UINT32 pc, UINT32 insn);
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void tg04_00_0e(UINT32 pc, UINT32 insn);
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void tg04_00_0f(UINT32 pc, UINT32 insn);
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void tg04_01_00(UINT32 pc, UINT32 insn);
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void tg04_01_01(UINT32 pc, UINT32 insn);
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void tg04_01_02(UINT32 pc, UINT32 insn);
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void tg04_01_03(UINT32 pc, UINT32 insn);
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void tg04_01_10(UINT32 pc, UINT32 insn);
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void tg04_01_11(UINT32 pc, UINT32 insn);
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void tg04_01_12(UINT32 pc, UINT32 insn);
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void tg04_01_13(UINT32 pc, UINT32 insn);
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void tg04_01_20(UINT32 pc, UINT32 insn);
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void tg04_01_21(UINT32 pc, UINT32 insn);
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void tg04_01_22(UINT32 pc, UINT32 insn);
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void tg04_01_23(UINT32 pc, UINT32 insn);
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void tg04_01_30(UINT32 pc, UINT32 insn);
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void tg04_01_31(UINT32 pc, UINT32 insn);
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void tg04_01_32(UINT32 pc, UINT32 insn);
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void tg04_01_33(UINT32 pc, UINT32 insn);
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void tg04_0203(UINT32 pc, UINT32 insn);
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void tg05_0(UINT32 pc, UINT32 insn);
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void tg05_1(UINT32 pc, UINT32 insn);
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void tg05_2(UINT32 pc, UINT32 insn);
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void tg05_3(UINT32 pc, UINT32 insn);
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void tg05_4(UINT32 pc, UINT32 insn);
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void tg05_5(UINT32 pc, UINT32 insn);
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void tg05_6(UINT32 pc, UINT32 insn);
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void tg05_7(UINT32 pc, UINT32 insn);
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void tg06_0(UINT32 pc, UINT32 insn);
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void tg06_1(UINT32 pc, UINT32 insn);
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void tg07_0(UINT32 pc, UINT32 insn);
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void tg07_1(UINT32 pc, UINT32 insn);
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void tg08_0(UINT32 pc, UINT32 insn);
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void tg08_1(UINT32 pc, UINT32 insn);
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void tg09_0(UINT32 pc, UINT32 insn);
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void tg09_1(UINT32 pc, UINT32 insn);
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void tg0a_0(UINT32 pc, UINT32 insn);
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void tg0a_1(UINT32 pc, UINT32 insn);
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void tg0b_0(UINT32 pc, UINT32 insn);
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void tg0b_1(UINT32 pc, UINT32 insn);
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void tg0b_2(UINT32 pc, UINT32 insn);
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void tg0b_3(UINT32 pc, UINT32 insn);
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void tg0b_4(UINT32 pc, UINT32 insn);
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void tg0b_5(UINT32 pc, UINT32 insn);
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void tg0b_6(UINT32 pc, UINT32 insn);
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void tg0b_7(UINT32 pc, UINT32 insn);
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void tg0b_8(UINT32 pc, UINT32 insn);
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void tg0b_9(UINT32 pc, UINT32 insn);
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void tg0b_a(UINT32 pc, UINT32 insn);
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void tg0b_b(UINT32 pc, UINT32 insn);
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void tg0b_c(UINT32 pc, UINT32 insn);
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void tg0b_d(UINT32 pc, UINT32 insn);
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void tg0b_e(UINT32 pc, UINT32 insn);
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void tg0b_f(UINT32 pc, UINT32 insn);
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void tg0c_0(UINT32 pc, UINT32 insn);
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void tg0c_1(UINT32 pc, UINT32 insn);
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void tg0d_0(UINT32 pc, UINT32 insn);
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void tg0d_1(UINT32 pc, UINT32 insn);
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void tg0d_2(UINT32 pc, UINT32 insn);
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void tg0d_3(UINT32 pc, UINT32 insn);
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void tg0d_4(UINT32 pc, UINT32 insn);
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void tg0d_5(UINT32 pc, UINT32 insn);
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void tg0d_6(UINT32 pc, UINT32 insn);
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void tg0d_7(UINT32 pc, UINT32 insn);
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void tg0d_8(UINT32 pc, UINT32 insn);
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void tg0d_9(UINT32 pc, UINT32 insn);
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void tg0d_a(UINT32 pc, UINT32 insn);
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void tg0d_b(UINT32 pc, UINT32 insn);
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void tg0d_c(UINT32 pc, UINT32 insn);
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void tg0d_d(UINT32 pc, UINT32 insn);
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void tg0d_e(UINT32 pc, UINT32 insn);
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void tg0d_f(UINT32 pc, UINT32 insn);
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void tg0e_0(UINT32 pc, UINT32 insn);
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void tg0e_1(UINT32 pc, UINT32 insn);
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void tg0f_0(UINT32 pc, UINT32 insn);
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void tg0f_1(UINT32 pc, UINT32 insn);
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typedef void ( arm7_cpu_device::*arm7thumb_ophandler ) (UINT32, UINT32);
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static const arm7thumb_ophandler thumb_handler[0x40*0x10];
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typedef void ( arm7_cpu_device::*arm7ops_ophandler )(UINT32);
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static const arm7ops_ophandler ops_handler[0x10];
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//
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// DRC
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//
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/* fast RAM info */
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struct fast_ram_info
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{
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offs_t start; /* start of the RAM block */
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offs_t end; /* end of the RAM block */
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UINT8 readonly; /* TRUE if read-only */
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void * base; /* base in memory where the RAM lives */
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};
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struct hotspot_info
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{
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UINT32 pc;
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UINT32 opcode;
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UINT32 cycles;
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};
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/* internal compiler state */
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struct compiler_state
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{
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UINT32 cycles; /* accumulated cycles */
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UINT8 checkints; /* need to check interrupts before next instruction */
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UINT8 checksoftints; /* need to check software interrupts before next instruction */
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uml::code_label labelnum; /* index for local labels */
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};
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/* ARM7 registers */
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struct arm7imp_state
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{
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/* core state */
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drc_cache * cache; /* pointer to the DRC code cache */
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drcuml_state * drcuml; /* DRC UML generator state */
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//arm7_frontend * drcfe; /* pointer to the DRC front-end state */
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UINT32 drcoptions; /* configurable DRC options */
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/* internal stuff */
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UINT8 cache_dirty; /* true if we need to flush the cache */
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UINT32 jmpdest; /* destination jump target */
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/* parameters for subroutines */
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UINT64 numcycles; /* return value from gettotalcycles */
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UINT32 mode; /* current global mode */
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const char * format; /* format string for print_debug */
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UINT32 arg0; /* print_debug argument 1 */
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UINT32 arg1; /* print_debug argument 2 */
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/* register mappings */
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uml::parameter regmap[/*NUM_REGS*/37]; /* parameter to register mappings for all 16 integer registers */
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/* subroutines */
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uml::code_handle * entry; /* entry point */
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uml::code_handle * nocode; /* nocode exception handler */
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uml::code_handle * out_of_cycles; /* out of cycles exception handler */
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uml::code_handle * tlb_translate; /* tlb translation handler */
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uml::code_handle * detect_fault; /* tlb fault detection handler */
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uml::code_handle * check_irq; /* irq check handler */
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uml::code_handle * read8; /* read byte */
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uml::code_handle * write8; /* write byte */
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uml::code_handle * read16; /* read half */
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uml::code_handle * write16; /* write half */
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uml::code_handle * read32; /* read word */
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uml::code_handle * write32; /* write word */
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/* fast RAM */
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UINT32 fastram_select;
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fast_ram_info fastram[ARM7_MAX_FASTRAM];
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/* hotspots */
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UINT32 hotspot_select;
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hotspot_info hotspot[ARM7_MAX_HOTSPOTS];
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} m_impstate;
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typedef void ( arm7_cpu_device::*arm7thumb_drcophandler)(drcuml_block*, compiler_state*, const opcode_desc*);
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static const arm7thumb_drcophandler drcthumb_handler[0x40*0x10];
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void drctg00_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* Shift left */
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void drctg00_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* Shift right */
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void drctg01_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
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void drctg01_10(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
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void drctg01_11(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* SUB Rd, Rs, Rn */
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void drctg01_12(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* ADD Rd, Rs, #imm */
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void drctg01_13(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* SUB Rd, Rs, #imm */
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void drctg02_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
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void drctg02_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
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void drctg03_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* ADD Rd, #Offset8 */
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void drctg03_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* SUB Rd, #Offset8 */
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void drctg04_00_00(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* AND Rd, Rs */
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void drctg04_00_01(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* EOR Rd, Rs */
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void drctg04_00_02(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* LSL Rd, Rs */
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void drctg04_00_03(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* LSR Rd, Rs */
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void drctg04_00_04(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* ASR Rd, Rs */
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void drctg04_00_05(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* ADC Rd, Rs */
|
||||
void drctg04_00_06(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* SBC Rd, Rs */
|
||||
void drctg04_00_07(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* ROR Rd, Rs */
|
||||
void drctg04_00_08(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* TST Rd, Rs */
|
||||
void drctg04_00_09(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* NEG Rd, Rs */
|
||||
void drctg04_00_0a(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* CMP Rd, Rs */
|
||||
void drctg04_00_0b(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* CMN Rd, Rs - check flags, add dasm */
|
||||
void drctg04_00_0c(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* ORR Rd, Rs */
|
||||
void drctg04_00_0d(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* MUL Rd, Rs */
|
||||
void drctg04_00_0e(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* BIC Rd, Rs */
|
||||
void drctg04_00_0f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* MVN Rd, Rs */
|
||||
void drctg04_01_00(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
void drctg04_01_01(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* ADD Rd, HRs */
|
||||
void drctg04_01_02(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* ADD HRd, Rs */
|
||||
void drctg04_01_03(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* Add HRd, HRs */
|
||||
void drctg04_01_10(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* CMP Rd, Rs */
|
||||
void drctg04_01_11(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* CMP Rd, Hs */
|
||||
void drctg04_01_12(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* CMP Hd, Rs */
|
||||
void drctg04_01_13(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* CMP Hd, Hs */
|
||||
void drctg04_01_20(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* MOV Rd, Rs (undefined) */
|
||||
void drctg04_01_21(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* MOV Rd, Hs */
|
||||
void drctg04_01_22(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* MOV Hd, Rs */
|
||||
void drctg04_01_23(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* MOV Hd, Hs */
|
||||
void drctg04_01_30(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
void drctg04_01_31(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
void drctg04_01_32(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
void drctg04_01_33(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
void drctg04_0203(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
void drctg05_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* STR Rd, [Rn, Rm] */
|
||||
void drctg05_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* STRH Rd, [Rn, Rm] */
|
||||
void drctg05_2(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* STRB Rd, [Rn, Rm] */
|
||||
void drctg05_3(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* LDSB Rd, [Rn, Rm] todo, add dasm */
|
||||
void drctg05_4(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* LDR Rd, [Rn, Rm] */
|
||||
void drctg05_5(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* LDRH Rd, [Rn, Rm] */
|
||||
void drctg05_6(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* LDRB Rd, [Rn, Rm] */
|
||||
void drctg05_7(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* LDSH Rd, [Rn, Rm] */
|
||||
void drctg06_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* Store */
|
||||
void drctg06_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* Load */
|
||||
void drctg07_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* Store */
|
||||
void drctg07_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* Load */
|
||||
void drctg08_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* Store */
|
||||
void drctg08_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* Load */
|
||||
void drctg09_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* Store */
|
||||
void drctg09_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* Load */
|
||||
void drctg0a_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* ADD Rd, PC, #nn */
|
||||
void drctg0a_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* ADD Rd, SP, #nn */
|
||||
void drctg0b_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* ADD SP, #imm */
|
||||
void drctg0b_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
void drctg0b_2(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
void drctg0b_3(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
void drctg0b_4(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* PUSH {Rlist} */
|
||||
void drctg0b_5(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* PUSH {Rlist}{LR} */
|
||||
void drctg0b_6(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
void drctg0b_7(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
void drctg0b_8(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
void drctg0b_9(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
void drctg0b_a(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
void drctg0b_b(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
void drctg0b_c(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* POP {Rlist} */
|
||||
void drctg0b_d(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* POP {Rlist}{PC} */
|
||||
void drctg0b_e(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
void drctg0b_f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
void drctg0c_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* Store */
|
||||
void drctg0c_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* Load */
|
||||
void drctg0d_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); // COND_EQ:
|
||||
void drctg0d_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); // COND_NE:
|
||||
void drctg0d_2(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); // COND_CS:
|
||||
void drctg0d_3(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); // COND_CC:
|
||||
void drctg0d_4(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); // COND_MI:
|
||||
void drctg0d_5(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); // COND_PL:
|
||||
void drctg0d_6(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); // COND_VS:
|
||||
void drctg0d_7(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); // COND_VC:
|
||||
void drctg0d_8(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); // COND_HI:
|
||||
void drctg0d_9(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); // COND_LS:
|
||||
void drctg0d_a(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); // COND_GE:
|
||||
void drctg0d_b(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); // COND_LT:
|
||||
void drctg0d_c(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); // COND_GT:
|
||||
void drctg0d_d(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); // COND_LE:
|
||||
void drctg0d_e(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); // COND_AL:
|
||||
void drctg0d_f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); // SWI (this is sort of a "hole" in the opcode encoding)
|
||||
void drctg0e_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
void drctg0e_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
void drctg0f_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
void drctg0f_1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc); /* BL */
|
||||
|
||||
void load_fast_iregs(drcuml_block *block);
|
||||
void save_fast_iregs(drcuml_block *block);
|
||||
void arm7_drc_init();
|
||||
void arm7_drc_exit();
|
||||
void execute_run_drc();
|
||||
void arm7drc_set_options(UINT32 options);
|
||||
void arm7drc_add_fastram(offs_t start, offs_t end, UINT8 readonly, void *base);
|
||||
void arm7drc_add_hotspot(offs_t pc, UINT32 opcode, UINT32 cycles);
|
||||
void code_flush_cache();
|
||||
void code_compile_block(UINT8 mode, offs_t pc);
|
||||
void cfunc_get_cycles();
|
||||
void cfunc_unimplemented();
|
||||
void static_generate_entry_point();
|
||||
void static_generate_check_irq();
|
||||
void static_generate_nocode_handler();
|
||||
void static_generate_out_of_cycles();
|
||||
void static_generate_detect_fault(uml::code_handle **handleptr);
|
||||
void static_generate_tlb_translate(uml::code_handle **handleptr);
|
||||
void static_generate_memory_accessor(int size, bool istlb, bool iswrite, const char *name, uml::code_handle **handleptr);
|
||||
void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param);
|
||||
void generate_checksum_block(drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast);
|
||||
void generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
void generate_delay_slot_and_branch(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 linkreg);
|
||||
|
||||
typedef bool ( arm7_cpu_device::*drcarm7ops_ophandler)(drcuml_block*, compiler_state*, const opcode_desc*, UINT32);
|
||||
static const drcarm7ops_ophandler drcops_handler[0x10];
|
||||
|
||||
void saturate_qbit_overflow(drcuml_block *block);
|
||||
bool drcarm7ops_0123(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 op);
|
||||
bool drcarm7ops_4567(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 op);
|
||||
bool drcarm7ops_89(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 op);
|
||||
bool drcarm7ops_ab(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 op);
|
||||
bool drcarm7ops_cd(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 op);
|
||||
bool drcarm7ops_e(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 op);
|
||||
bool drcarm7ops_f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 op);
|
||||
int generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
|
||||
};
|
||||
|
||||
|
||||
class arm7_be_cpu_device : public arm7_cpu_device
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
arm7_be_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
};
|
||||
|
||||
|
||||
class arm7500_cpu_device : public arm7_cpu_device
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
arm7500_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
};
|
||||
|
||||
|
||||
class arm9_cpu_device : public arm7_cpu_device
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
arm9_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
};
|
||||
|
||||
|
||||
class arm920t_cpu_device : public arm7_cpu_device
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
arm920t_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
};
|
||||
|
||||
|
||||
class pxa255_cpu_device : public arm7_cpu_device
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
pxa255_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
};
|
||||
|
||||
|
||||
class sa1110_cpu_device : public arm7_cpu_device
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
sa1110_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
};
|
||||
|
||||
|
||||
extern const device_type ARM7;
|
||||
extern const device_type ARM7_BE;
|
||||
extern const device_type ARM7500;
|
||||
extern const device_type ARM9;
|
||||
extern const device_type ARM920T;
|
||||
extern const device_type PXA255;
|
||||
extern const device_type SA1110;
|
||||
|
||||
#endif /* __ARM7_H__ */
|
||||
|
||||
@ -77,28 +77,6 @@
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
/* Prototypes */
|
||||
|
||||
|
||||
extern UINT32 decodeShift(arm_state *arm, UINT32 insn, UINT32 *pCarry);
|
||||
|
||||
void arm7_check_irq_state(arm_state *arm);
|
||||
|
||||
|
||||
/* Static Vars */
|
||||
// Note: for multi-cpu implementation, this approach won't work w/o modification
|
||||
write32_device_func arm7_coproc_do_callback; // holder for the co processor Data Operations Callback func.
|
||||
read32_device_func arm7_coproc_rt_r_callback; // holder for the co processor Register Transfer Read Callback func.
|
||||
write32_device_func arm7_coproc_rt_w_callback; // holder for the co processor Register Transfer Write Callback Callback func.
|
||||
|
||||
#ifdef UNUSED_DEFINITION
|
||||
// custom dasm callback handlers for co-processor instructions
|
||||
char *(*arm7_dasm_cop_dt_callback)(arm_state *arm, char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
|
||||
char *(*arm7_dasm_cop_rt_callback)(arm_state *arm, char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
|
||||
char *(*arm7_dasm_cop_do_callback)(arm_state *arm, char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
|
||||
#endif
|
||||
|
||||
|
||||
// convert cpsr mode num into to text
|
||||
static const char modetext[ARM7_NUM_MODES][5] = {
|
||||
"USER", "FIRQ", "IRQ", "SVC", "ILL1", "ILL2", "ILL3", "ABT",
|
||||
@ -116,46 +94,12 @@ static const char *GetModeText(int cpsr)
|
||||
* Main CPU Funcs
|
||||
***************************************************************************/
|
||||
|
||||
// CPU INIT
|
||||
static void arm7_core_init(device_t *device, const char *cpuname)
|
||||
{
|
||||
arm_state *arm = get_safe_token(device);
|
||||
|
||||
device->save_item(NAME(arm->r));
|
||||
device->save_item(NAME(arm->pendingIrq));
|
||||
device->save_item(NAME(arm->pendingFiq));
|
||||
device->save_item(NAME(arm->pendingAbtD));
|
||||
device->save_item(NAME(arm->pendingAbtP));
|
||||
device->save_item(NAME(arm->pendingUnd));
|
||||
device->save_item(NAME(arm->pendingSwi));
|
||||
}
|
||||
|
||||
// CPU RESET
|
||||
static void arm7_core_reset(legacy_cpu_device *device)
|
||||
{
|
||||
arm_state *arm = get_safe_token(device);
|
||||
|
||||
device_irq_acknowledge_callback save_irqcallback = arm->irq_callback;
|
||||
|
||||
memset(arm, 0, sizeof(arm_state));
|
||||
arm->irq_callback = save_irqcallback;
|
||||
arm->device = device;
|
||||
arm->program = &device->space(AS_PROGRAM);
|
||||
arm->endian = ENDIANNESS_LITTLE;
|
||||
arm->direct = &arm->program->direct();
|
||||
|
||||
/* start up in SVC mode with interrupts disabled. */
|
||||
ARM7REG(eCPSR) = I_MASK | F_MASK | 0x10;
|
||||
SwitchMode(arm, eARM7_MODE_SVC);
|
||||
R15 = 0;
|
||||
}
|
||||
|
||||
// CPU CHECK IRQ STATE
|
||||
// Note: couldn't find any exact cycle counts for most of these exceptions
|
||||
void arm7_check_irq_state(arm_state *arm)
|
||||
void arm7_cpu_device::arm7_check_irq_state()
|
||||
{
|
||||
UINT32 cpsr = GET_CPSR; /* save current CPSR */
|
||||
UINT32 pc = R15 + 4; /* save old pc (already incremented in pipeline) */;
|
||||
UINT32 cpsr = m_r[eCPSR]; /* save current CPSR */
|
||||
UINT32 pc = m_r[eR15] + 4; /* save old pc (already incremented in pipeline) */;
|
||||
|
||||
/* Exception priorities:
|
||||
|
||||
@ -169,25 +113,25 @@ void arm7_check_irq_state(arm_state *arm)
|
||||
*/
|
||||
|
||||
// Data Abort
|
||||
if (arm->pendingAbtD) {
|
||||
if (m_pendingAbtD) {
|
||||
if (MODE26) fatalerror( "pendingAbtD (todo)\n");
|
||||
SwitchMode(arm, eARM7_MODE_ABT); /* Set ABT mode so PC is saved to correct R14 bank */
|
||||
SET_REGISTER(arm, 14, pc - 8 + 8); /* save PC to R14 */
|
||||
SET_REGISTER(arm, SPSR, cpsr); /* Save current CPSR */
|
||||
SwitchMode(eARM7_MODE_ABT); /* Set ABT mode so PC is saved to correct R14 bank */
|
||||
SET_REGISTER(14, pc - 8 + 8); /* save PC to R14 */
|
||||
SET_REGISTER(SPSR, cpsr); /* Save current CPSR */
|
||||
SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */
|
||||
SET_CPSR(GET_CPSR & ~T_MASK);
|
||||
R15 = 0x10; /* IRQ Vector address */
|
||||
if ((COPRO_CTRL & COPRO_CTRL_MMU_EN) && (COPRO_CTRL & COPRO_CTRL_INTVEC_ADJUST)) R15 |= 0xFFFF0000;
|
||||
arm->pendingAbtD = 0;
|
||||
m_pendingAbtD = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
// FIQ
|
||||
if (arm->pendingFiq && (cpsr & F_MASK) == 0) {
|
||||
if (m_pendingFiq && (cpsr & F_MASK) == 0) {
|
||||
if (MODE26) fatalerror( "pendingFiq (todo)\n");
|
||||
SwitchMode(arm, eARM7_MODE_FIQ); /* Set FIQ mode so PC is saved to correct R14 bank */
|
||||
SET_REGISTER(arm, 14, pc - 4 + 4); /* save PC to R14 */
|
||||
SET_REGISTER(arm, SPSR, cpsr); /* Save current CPSR */
|
||||
SwitchMode(eARM7_MODE_FIQ); /* Set FIQ mode so PC is saved to correct R14 bank */
|
||||
SET_REGISTER(14, pc - 4 + 4); /* save PC to R14 */
|
||||
SET_REGISTER(SPSR, cpsr); /* Save current CPSR */
|
||||
SET_CPSR(GET_CPSR | I_MASK | F_MASK); /* Mask both IRQ & FIQ */
|
||||
SET_CPSR(GET_CPSR & ~T_MASK);
|
||||
R15 = 0x1c; /* IRQ Vector address */
|
||||
@ -196,12 +140,12 @@ void arm7_check_irq_state(arm_state *arm)
|
||||
}
|
||||
|
||||
// IRQ
|
||||
if (arm->pendingIrq && (cpsr & I_MASK) == 0) {
|
||||
SwitchMode(arm, eARM7_MODE_IRQ); /* Set IRQ mode so PC is saved to correct R14 bank */
|
||||
SET_REGISTER(arm, 14, pc - 4 + 4); /* save PC to R14 */
|
||||
if (m_pendingIrq && (cpsr & I_MASK) == 0) {
|
||||
SwitchMode(eARM7_MODE_IRQ); /* Set IRQ mode so PC is saved to correct R14 bank */
|
||||
SET_REGISTER(14, pc - 4 + 4); /* save PC to R14 */
|
||||
if (MODE32)
|
||||
{
|
||||
SET_REGISTER(arm, SPSR, cpsr); /* Save current CPSR */
|
||||
SET_REGISTER(SPSR, cpsr); /* Save current CPSR */
|
||||
SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */
|
||||
SET_CPSR(GET_CPSR & ~T_MASK);
|
||||
R15 = 0x18; /* IRQ Vector address */
|
||||
@ -218,56 +162,56 @@ void arm7_check_irq_state(arm_state *arm)
|
||||
}
|
||||
|
||||
// Prefetch Abort
|
||||
if (arm->pendingAbtP) {
|
||||
if (m_pendingAbtP) {
|
||||
if (MODE26) fatalerror( "pendingAbtP (todo)\n");
|
||||
SwitchMode(arm, eARM7_MODE_ABT); /* Set ABT mode so PC is saved to correct R14 bank */
|
||||
SET_REGISTER(arm, 14, pc - 4 + 4); /* save PC to R14 */
|
||||
SET_REGISTER(arm, SPSR, cpsr); /* Save current CPSR */
|
||||
SwitchMode(eARM7_MODE_ABT); /* Set ABT mode so PC is saved to correct R14 bank */
|
||||
SET_REGISTER(14, pc - 4 + 4); /* save PC to R14 */
|
||||
SET_REGISTER(SPSR, cpsr); /* Save current CPSR */
|
||||
SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */
|
||||
SET_CPSR(GET_CPSR & ~T_MASK);
|
||||
R15 = 0x0c; /* IRQ Vector address */
|
||||
if ((COPRO_CTRL & COPRO_CTRL_MMU_EN) && (COPRO_CTRL & COPRO_CTRL_INTVEC_ADJUST)) R15 |= 0xFFFF0000;
|
||||
arm->pendingAbtP = 0;
|
||||
m_pendingAbtP = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
// Undefined instruction
|
||||
if (arm->pendingUnd) {
|
||||
if (m_pendingUnd) {
|
||||
if (MODE26) fatalerror( "pendingUnd (todo)\n");
|
||||
SwitchMode(arm, eARM7_MODE_UND); /* Set UND mode so PC is saved to correct R14 bank */
|
||||
SwitchMode(eARM7_MODE_UND); /* Set UND mode so PC is saved to correct R14 bank */
|
||||
// compensate for prefetch (should this also be done for normal IRQ?)
|
||||
if (T_IS_SET(GET_CPSR))
|
||||
{
|
||||
SET_REGISTER(arm, 14, pc - 4 + 2); /* save PC to R14 */
|
||||
SET_REGISTER(14, pc - 4 + 2); /* save PC to R14 */
|
||||
}
|
||||
else
|
||||
{
|
||||
SET_REGISTER(arm, 14, pc - 4 + 4 - 4); /* save PC to R14 */
|
||||
SET_REGISTER(14, pc - 4 + 4 - 4); /* save PC to R14 */
|
||||
}
|
||||
SET_REGISTER(arm, SPSR, cpsr); /* Save current CPSR */
|
||||
SET_REGISTER(SPSR, cpsr); /* Save current CPSR */
|
||||
SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */
|
||||
SET_CPSR(GET_CPSR & ~T_MASK);
|
||||
R15 = 0x04; /* IRQ Vector address */
|
||||
if ((COPRO_CTRL & COPRO_CTRL_MMU_EN) && (COPRO_CTRL & COPRO_CTRL_INTVEC_ADJUST)) R15 |= 0xFFFF0000;
|
||||
arm->pendingUnd = 0;
|
||||
m_pendingUnd = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
// Software Interrupt
|
||||
if (arm->pendingSwi) {
|
||||
SwitchMode(arm, eARM7_MODE_SVC); /* Set SVC mode so PC is saved to correct R14 bank */
|
||||
if (m_pendingSwi) {
|
||||
SwitchMode(eARM7_MODE_SVC); /* Set SVC mode so PC is saved to correct R14 bank */
|
||||
// compensate for prefetch (should this also be done for normal IRQ?)
|
||||
if (T_IS_SET(GET_CPSR))
|
||||
{
|
||||
SET_REGISTER(arm, 14, pc - 4 + 2); /* save PC to R14 */
|
||||
SET_REGISTER(14, pc - 4 + 2); /* save PC to R14 */
|
||||
}
|
||||
else
|
||||
{
|
||||
SET_REGISTER(arm, 14, pc - 4 + 4); /* save PC to R14 */
|
||||
SET_REGISTER(14, pc - 4 + 4); /* save PC to R14 */
|
||||
}
|
||||
if (MODE32)
|
||||
{
|
||||
SET_REGISTER(arm, SPSR, cpsr); /* Save current CPSR */
|
||||
SET_REGISTER(SPSR, cpsr); /* Save current CPSR */
|
||||
SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */
|
||||
SET_CPSR(GET_CPSR & ~T_MASK); /* Go to ARM mode */
|
||||
R15 = 0x08; /* Jump to the SWI vector */
|
||||
@ -280,34 +224,8 @@ void arm7_check_irq_state(arm_state *arm)
|
||||
SET_CPSR(temp); /* Mask IRQ */
|
||||
}
|
||||
if ((COPRO_CTRL & COPRO_CTRL_MMU_EN) && (COPRO_CTRL & COPRO_CTRL_INTVEC_ADJUST)) R15 |= 0xFFFF0000;
|
||||
arm->pendingSwi = 0;
|
||||
m_pendingSwi = 0;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
// CPU - SET IRQ LINE
|
||||
static void arm7_core_set_irq_line(arm_state *arm, int irqline, int state)
|
||||
{
|
||||
switch (irqline) {
|
||||
case ARM7_IRQ_LINE: /* IRQ */
|
||||
arm->pendingIrq = state & 1;
|
||||
break;
|
||||
|
||||
case ARM7_FIRQ_LINE: /* FIRQ */
|
||||
arm->pendingFiq = state & 1;
|
||||
break;
|
||||
|
||||
case ARM7_ABORT_EXCEPTION:
|
||||
arm->pendingAbtD = state & 1;
|
||||
break;
|
||||
case ARM7_ABORT_PREFETCH_EXCEPTION:
|
||||
arm->pendingAbtP = state & 1;
|
||||
break;
|
||||
|
||||
case ARM7_UNDEFINE_EXCEPTION:
|
||||
arm->pendingUnd = state & 1;
|
||||
break;
|
||||
}
|
||||
|
||||
ARM7_CHECKIRQ;
|
||||
}
|
||||
|
||||
@ -93,7 +93,7 @@ enum
|
||||
};
|
||||
|
||||
/* Coprocessor-related macros */
|
||||
#define COPRO_TLB_BASE arm->tlbBase
|
||||
#define COPRO_TLB_BASE m_tlbBase
|
||||
#define COPRO_TLB_BASE_MASK 0xffffc000
|
||||
#define COPRO_TLB_VADDR_FLTI_MASK 0xfff00000
|
||||
#define COPRO_TLB_VADDR_FLTI_MASK_SHIFT 18
|
||||
@ -117,7 +117,7 @@ enum
|
||||
#define COPRO_TLB_SECTION_TABLE 2
|
||||
#define COPRO_TLB_FINE_TABLE 3
|
||||
|
||||
#define COPRO_CTRL arm->control
|
||||
#define COPRO_CTRL m_control
|
||||
#define COPRO_CTRL_MMU_EN 0x00000001
|
||||
#define COPRO_CTRL_ADDRFAULT_EN 0x00000002
|
||||
#define COPRO_CTRL_DCACHE_EN 0x00000004
|
||||
@ -141,23 +141,14 @@ enum
|
||||
#define COPRO_CTRL_INTVEC_F 1
|
||||
#define COPRO_CTRL_MASK 0x0000338f
|
||||
|
||||
#define COPRO_DOMAIN_ACCESS_CONTROL arm->domainAccessControl
|
||||
#define COPRO_DOMAIN_ACCESS_CONTROL m_domainAccessControl
|
||||
|
||||
#define COPRO_FAULT_STATUS_D arm->faultStatus[0]
|
||||
#define COPRO_FAULT_STATUS_P arm->faultStatus[1]
|
||||
#define COPRO_FAULT_STATUS_D m_faultStatus[0]
|
||||
#define COPRO_FAULT_STATUS_P m_faultStatus[1]
|
||||
|
||||
#define COPRO_FAULT_ADDRESS arm->faultAddress
|
||||
#define COPRO_FAULT_ADDRESS m_faultAddress
|
||||
|
||||
#define COPRO_FCSE_PID arm->fcsePID
|
||||
|
||||
/* Coprocessor Registers */
|
||||
#define ARM7COPRO_REGS \
|
||||
UINT32 control; \
|
||||
UINT32 tlbBase; \
|
||||
UINT32 faultStatus[2]; \
|
||||
UINT32 faultAddress; \
|
||||
UINT32 fcsePID; \
|
||||
UINT32 domainAccessControl;
|
||||
#define COPRO_FCSE_PID m_fcsePID
|
||||
|
||||
enum
|
||||
{
|
||||
@ -170,20 +161,6 @@ enum
|
||||
eARM_ARCHFLAGS_MODE26 = 64, // supports 26-bit backwards compatibility mode
|
||||
};
|
||||
|
||||
#define ARM7CORE_REGS \
|
||||
UINT32 r[NUM_REGS]; \
|
||||
UINT32 pendingIrq; \
|
||||
UINT32 pendingFiq; \
|
||||
UINT32 pendingAbtD; \
|
||||
UINT32 pendingAbtP; \
|
||||
UINT32 pendingUnd; \
|
||||
UINT32 pendingSwi; \
|
||||
int icount; \
|
||||
endianness_t endian; \
|
||||
device_irq_acknowledge_callback irq_callback; \
|
||||
legacy_cpu_device *device; \
|
||||
address_space *program; \
|
||||
direct_read_data *direct;
|
||||
|
||||
//#define ARM7_USE_DRC
|
||||
|
||||
@ -197,16 +174,35 @@ struct arm7imp_state;
|
||||
/* CPU state struct */
|
||||
struct arm_state
|
||||
{
|
||||
ARM7CORE_REGS // these must be included in your cpu specific register implementation
|
||||
ARM7COPRO_REGS
|
||||
UINT32 m_r[NUM_REGS];
|
||||
UINT32 m_pendingIrq;
|
||||
UINT32 m_pendingFiq;
|
||||
UINT32 m_pendingAbtD;
|
||||
UINT32 m_pendingAbtP;
|
||||
UINT32 m_pendingUnd;
|
||||
UINT32 m_pendingSwi;
|
||||
int m_icount;
|
||||
endianness_t m_endian;
|
||||
device_irq_acknowledge_callback m_irq_callback;
|
||||
legacy_cpu_device *m_device;
|
||||
address_space *m_program;
|
||||
direct_read_data *m_direct;
|
||||
|
||||
UINT8 archRev; // ARM architecture revision (3, 4, and 5 are valid)
|
||||
UINT8 archFlags; // architecture flags
|
||||
/* Coprocessor Registers */
|
||||
UINT32 m_control;
|
||||
UINT32 m_tlbBase;
|
||||
UINT32 m_faultStatus[2];
|
||||
UINT32 m_faultAddress;
|
||||
UINT32 m_fcsePID;
|
||||
UINT32 m_domainAccessControl;
|
||||
|
||||
UINT8 m_archRev; // ARM architecture revision (3, 4, and 5 are valid)
|
||||
UINT8 m_archFlags; // architecture flags
|
||||
|
||||
#if ARM7_MMU_ENABLE_HACK
|
||||
UINT32 mmu_enable_addr; // workaround for "MMU is enabled when PA != VA" problem
|
||||
#endif
|
||||
arm7imp_state impstate;
|
||||
arm7imp_state m_impstate;
|
||||
};
|
||||
|
||||
/****************************************************************************************************
|
||||
@ -501,10 +497,10 @@ enum
|
||||
#define ROR(v, s) (LSR((v), (s)) | (LSL((v), 32u - (s))))
|
||||
|
||||
/* Convenience Macros */
|
||||
#define R15 ARM7REG(eR15)
|
||||
#define R15 m_r[eR15]
|
||||
#define SPSR 17 // SPSR is always the 18th register in our 0 based array sRegisterTable[][18]
|
||||
#define GET_CPSR ARM7REG(eCPSR)
|
||||
#define SET_CPSR(v) set_cpsr(arm,v)
|
||||
#define GET_CPSR m_r[eCPSR]
|
||||
#define SET_CPSR(v) set_cpsr(v)
|
||||
#define MODE_FLAG 0xF // Mode bits are 4:0 of CPSR, but we ignore bit 4.
|
||||
#define GET_MODE (GET_CPSR & MODE_FLAG)
|
||||
#define SIGN_BIT ((UINT32)(1 << 31))
|
||||
@ -525,23 +521,12 @@ enum
|
||||
#define ARM7_TLB_WRITE (1 << 3)
|
||||
|
||||
/* At one point I thought these needed to be cpu implementation specific, but they don't.. */
|
||||
#define GET_REGISTER(state, reg) GetRegister(state, reg)
|
||||
#define SET_REGISTER(state, reg, val) SetRegister(state, reg, val)
|
||||
#define GET_MODE_REGISTER(state, mode, reg) GetModeRegister(state, mode, reg)
|
||||
#define SET_MODE_REGISTER(state, mode, reg, val) SetModeRegister(state, mode, reg, val)
|
||||
#define ARM7_CHECKIRQ arm7_check_irq_state(arm)
|
||||
#define GET_REGISTER(reg) GetRegister(reg)
|
||||
#define SET_REGISTER(reg, val) SetRegister(reg, val)
|
||||
#define GET_MODE_REGISTER(mode, reg) GetModeRegister(mode, reg)
|
||||
#define SET_MODE_REGISTER(mode, reg, val) SetModeRegister(mode, reg, val)
|
||||
#define ARM7_CHECKIRQ arm7_check_irq_state()
|
||||
|
||||
extern write32_device_func arm7_coproc_do_callback;
|
||||
extern read32_device_func arm7_coproc_rt_r_callback;
|
||||
extern write32_device_func arm7_coproc_rt_w_callback;
|
||||
extern void arm7_dt_r_callback(arm_state *arm, UINT32 insn, UINT32 *prn, UINT32 (*read32)(arm_state *arm, UINT32 addr));
|
||||
extern void arm7_dt_w_callback(arm_state *arm, UINT32 insn, UINT32 *prn, void (*write32)(arm_state *arm, UINT32 addr, UINT32 data));
|
||||
|
||||
#ifdef UNUSED_DEFINITION
|
||||
extern char *(*arm7_dasm_cop_dt_callback)(arm_state *arm, char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
|
||||
extern char *(*arm7_dasm_cop_rt_callback)(arm_state *arm, char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
|
||||
extern char *(*arm7_dasm_cop_do_callback)(arm_state *arm, char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
|
||||
#endif
|
||||
|
||||
/* ARM flavors */
|
||||
enum arm_flavor
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,12 +1,10 @@
|
||||
/* ARM7 core helper Macros / Functions */
|
||||
|
||||
/* Macros that need to be defined according to the cpu implementation specific need */
|
||||
#define ARM7REG(reg) arm->r[reg]
|
||||
#define ARM7_ICOUNT arm->icount
|
||||
#define ARM7REG(reg) m_r[reg]
|
||||
#define ARM7_ICOUNT m_icount
|
||||
|
||||
|
||||
extern void SwitchMode(arm_state *arm, int cpsr_mode_val);
|
||||
|
||||
#if 0
|
||||
#define LOG(x) mame_printf_debug x
|
||||
#else
|
||||
@ -45,19 +43,19 @@ extern void SwitchMode(arm_state *arm, int cpsr_mode_val);
|
||||
#define DRCHandleThumbALUAddFlags(rd, rn, op2) \
|
||||
UML_AND(block, DRC_CPSR, DRC_CPSR, ~(N_MASK | Z_MASK | V_MASK | C_MASK)); \
|
||||
DRCHandleALUNZFlags(rd); \
|
||||
UML_XOR(block, I1, rn, ~0); \
|
||||
UML_CMP(block, I1, op2); \
|
||||
UML_MOVc(block, COND_B, I1, C_BIT); \
|
||||
UML_MOVc(block, COND_AE, I1, 0); \
|
||||
UML_OR(block, I0, I0, I1); \
|
||||
UML_XOR(block, I1, rn, op2); \
|
||||
UML_XOR(block, I2, rn, rd); \
|
||||
UML_AND(block, I1, I1, I2); \
|
||||
UML_TEST(block, I1, 1 << 31); \
|
||||
UML_MOVc(block, COND_NZ, I1, V_BIT); \
|
||||
UML_MOVc(block, COND_Z, I1, 0); \
|
||||
UML_OR(block, I0, I0, I1); \
|
||||
UML_OR(block, DRC_CPSR, DRC_CPSR, I0); \
|
||||
UML_XOR(block, uml::I1, rn, ~0); \
|
||||
UML_CMP(block, uml::I1, op2); \
|
||||
UML_MOVc(block, uml::COND_B, uml::I1, C_BIT); \
|
||||
UML_MOVc(block, uml::COND_AE, uml::I1, 0); \
|
||||
UML_OR(block, uml::I0, uml::I0, uml::I1); \
|
||||
UML_XOR(block, uml::I1, rn, op2); \
|
||||
UML_XOR(block, uml::I2, rn, rd); \
|
||||
UML_AND(block, uml::I1, uml::I1, uml::I2); \
|
||||
UML_TEST(block, uml::I1, 1 << 31); \
|
||||
UML_MOVc(block, uml::COND_NZ, uml::I1, V_BIT); \
|
||||
UML_MOVc(block, uml::COND_Z, uml::I1, 0); \
|
||||
UML_OR(block, uml::I0, uml::I0, uml::I1); \
|
||||
UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0); \
|
||||
UML_ADD(block, DRC_PC, DRC_PC, 2);
|
||||
|
||||
#define HandleALUSubFlags(rd, rn, op2) \
|
||||
@ -78,28 +76,28 @@ extern void SwitchMode(arm_state *arm, int cpsr_mode_val);
|
||||
#define DRCHandleThumbALUSubFlags(rd, rn, op2) \
|
||||
UML_AND(block, DRC_CPSR, DRC_CPSR, ~(N_MASK | Z_MASK | V_MASK | C_MASK)); \
|
||||
DRCHandleALUNZFlags(rd); \
|
||||
UML_XOR(block, I1, rn, op2); \
|
||||
UML_XOR(block, I2, rn, rd); \
|
||||
UML_AND(block, I1, I1, I2); \
|
||||
UML_TEST(block, I1, 1 << 31); \
|
||||
UML_MOVc(block, COND_NZ, I1, V_BIT); \
|
||||
UML_MOVc(block, COND_Z, I1, 0); \
|
||||
UML_OR(block, I0, I0, I1); \
|
||||
UML_OR(block, DRC_CPSR, DRC_CPSR, I0); \
|
||||
UML_AND(block, I0, rd, 1 << 31); \
|
||||
UML_AND(block, I1, op2, 1 << 31); \
|
||||
UML_AND(block, I2, rn, 1 << 31); \
|
||||
UML_XOR(block, I2, I2, ~0); \
|
||||
UML_AND(block, I1, I1, I2); \
|
||||
UML_AND(block, I2, I2, I0); \
|
||||
UML_OR(block, I1, I1, I2); \
|
||||
UML_AND(block, I2, op2, 1 << 31); \
|
||||
UML_AND(block, I2, I2, I0); \
|
||||
UML_OR(block, I1, I1, I2); \
|
||||
UML_TEST(block, I1, 1 << 31); \
|
||||
UML_MOVc(block, COND_NZ, I0, C_MASK); \
|
||||
UML_MOVc(block, COND_Z, I0, 0); \
|
||||
UML_OR(block, DRC_CPSR, DRC_CPSR, I0); \
|
||||
UML_XOR(block, uml::I1, rn, op2); \
|
||||
UML_XOR(block, uml::I2, rn, rd); \
|
||||
UML_AND(block, uml::I1, uml::I1, uml::I2); \
|
||||
UML_TEST(block, uml::I1, 1 << 31); \
|
||||
UML_MOVc(block, uml::COND_NZ, uml::I1, V_BIT); \
|
||||
UML_MOVc(block, uml::COND_Z, uml::I1, 0); \
|
||||
UML_OR(block, uml::I0, uml::I0, uml::I1); \
|
||||
UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0); \
|
||||
UML_AND(block, uml::I0, rd, 1 << 31); \
|
||||
UML_AND(block, uml::I1, op2, 1 << 31); \
|
||||
UML_AND(block, uml::I2, rn, 1 << 31); \
|
||||
UML_XOR(block, uml::I2, uml::I2, ~0); \
|
||||
UML_AND(block, uml::I1, uml::I1, uml::I2); \
|
||||
UML_AND(block, uml::I2, uml::I2, uml::I0); \
|
||||
UML_OR(block, uml::I1, uml::I1, uml::I2); \
|
||||
UML_AND(block, uml::I2, op2, 1 << 31); \
|
||||
UML_AND(block, uml::I2, uml::I2, uml::I0); \
|
||||
UML_OR(block, uml::I1, uml::I1, uml::I2); \
|
||||
UML_TEST(block, uml::I1, 1 << 31); \
|
||||
UML_MOVc(block, uml::COND_NZ, uml::I0, C_MASK); \
|
||||
UML_MOVc(block, uml::COND_Z, uml::I0, 0); \
|
||||
UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0); \
|
||||
UML_ADD(block, DRC_PC, DRC_PC, 2);
|
||||
|
||||
/* Set NZC flags for logical operations. */
|
||||
@ -109,12 +107,12 @@ extern void SwitchMode(arm_state *arm, int cpsr_mode_val);
|
||||
#define HandleALUNZFlags(rd) \
|
||||
(((rd) & SIGN_BIT) | ((!(rd)) << Z_BIT))
|
||||
|
||||
#define DRCHandleALUNZFlags(rd) \
|
||||
UML_AND(block, I0, rd, SIGN_BIT); \
|
||||
UML_CMP(block, rd, 0); \
|
||||
UML_MOVc(block, COND_E, I1, 1); \
|
||||
UML_MOVc(block, COND_NE, I1, 0); \
|
||||
UML_ROLINS(block, I0, I1, Z_BIT, 1 << Z_BIT);
|
||||
#define DRCHandleALUNZFlags(rd) \
|
||||
UML_AND(block, uml::I0, rd, SIGN_BIT); \
|
||||
UML_CMP(block, rd, 0); \
|
||||
UML_MOVc(block, uml::COND_E, uml::I1, 1); \
|
||||
UML_MOVc(block, uml::COND_NE, uml::I1, 0); \
|
||||
UML_ROLINS(block, uml::I0, uml::I1, Z_BIT, 1 << Z_BIT);
|
||||
|
||||
// Long ALU Functions use bit 63
|
||||
#define HandleLongALUNZFlags(rd) \
|
||||
@ -127,11 +125,11 @@ extern void SwitchMode(arm_state *arm, int cpsr_mode_val);
|
||||
| (((sc) != 0) << C_BIT))); \
|
||||
R15 += 4;
|
||||
|
||||
#define DRC_RD mem(&GET_REGISTER(arm, rd))
|
||||
#define DRC_RS mem(&GET_REGISTER(arm, rs))
|
||||
#define DRC_CPSR mem(&GET_CPSR)
|
||||
#define DRC_PC mem(&R15)
|
||||
#define DRC_REG(i) mem(&arm->r[(i)]);
|
||||
#define DRC_RD uml::mem(&GET_REGISTER(rd))
|
||||
#define DRC_RS uml::mem(&GET_REGISTER(rs))
|
||||
#define DRC_CPSR uml::mem(&GET_CPSR)
|
||||
#define DRC_PC uml::mem(&R15)
|
||||
#define DRC_REG(i) uml::mem(&m_r[(i)])
|
||||
|
||||
#define DRCHandleALULogicalFlags(rd, sc) \
|
||||
if (insn & INSN_S) \
|
||||
@ -139,172 +137,30 @@ extern void SwitchMode(arm_state *arm, int cpsr_mode_val);
|
||||
UML_AND(block, DRC_CPSR, DRC_CPSR, ~(N_MASK | Z_MASK | C_MASK); \
|
||||
DRCHandleALUNZFlags(rd); \
|
||||
UML_TEST(block, sc, ~0); \
|
||||
UML_MOVc(block, COND_Z, I1, C_BIT); \
|
||||
UML_MOVc(block, COND_NZ, I1, 0); \
|
||||
UML_OR(block, I0, I0, I1); \
|
||||
UML_OR(block, DRC_CPSR, DRC_CPSR, I0); \
|
||||
UML_MOVc(block, uml::COND_Z, uml::I1, C_BIT); \
|
||||
UML_MOVc(block, uml::COND_NZ, uml::I1, 0); \
|
||||
UML_OR(block, uml::I0, uml::I0, uml::I1); \
|
||||
UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0); \
|
||||
} \
|
||||
UML_ADD(block, DRC_PC, DRC_PC, 4);
|
||||
|
||||
void set_cpsr( arm_state *arm, UINT32 val);
|
||||
|
||||
// used to be functions, but no longer a need, so we'll use define for better speed.
|
||||
#define GetRegister(arm, rIndex) ARM7REG(sRegisterTable[GET_MODE][rIndex])
|
||||
#define SetRegister(arm, rIndex, value) ARM7REG(sRegisterTable[GET_MODE][rIndex]) = value
|
||||
#define GetRegister(rIndex) m_r[sRegisterTable[GET_MODE][rIndex]]
|
||||
#define SetRegister(rIndex, value) m_r[sRegisterTable[GET_MODE][rIndex]] = value
|
||||
|
||||
#define GetModeRegister(arm, mode, rIndex) ARM7REG(sRegisterTable[mode][rIndex])
|
||||
#define SetModeRegister(arm, mode, rIndex, value) ARM7REG(sRegisterTable[mode][rIndex]) = value
|
||||
|
||||
int arm7_tlb_translate(arm_state *arm, UINT32 *addr, int flags);
|
||||
void arm7_check_irq_state(arm_state *arm);
|
||||
|
||||
typedef const void (*arm7thumb_ophandler)(arm_state*, UINT32, UINT32);
|
||||
extern arm7thumb_ophandler thumb_handler[0x40*0x10];
|
||||
|
||||
typedef const void (*arm7ops_ophandler)(arm_state*, UINT32);
|
||||
|
||||
extern arm7ops_ophandler ops_handler[0x10];
|
||||
|
||||
extern void (*arm7_coproc_dt_r_callback)(arm_state *arm, UINT32 insn, UINT32 *prn, UINT32 (*read32)(arm_state *arm, UINT32 addr));
|
||||
extern void (*arm7_coproc_dt_w_callback)(arm_state *arm, UINT32 insn, UINT32 *prn, void (*write32)(arm_state *arm, UINT32 addr, UINT32 data));
|
||||
|
||||
|
||||
/***************************************************************************
|
||||
* Default Memory Handlers
|
||||
***************************************************************************/
|
||||
INLINE void arm7_cpu_write32(arm_state *arm, UINT32 addr, UINT32 data)
|
||||
{
|
||||
if( COPRO_CTRL & COPRO_CTRL_MMU_EN )
|
||||
{
|
||||
if (!arm7_tlb_translate( arm, &addr, ARM7_TLB_ABORT_D | ARM7_TLB_WRITE ))
|
||||
{
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
addr &= ~3;
|
||||
if ( arm->endian == ENDIANNESS_BIG )
|
||||
arm->program->write_dword(addr, data);
|
||||
else
|
||||
arm->program->write_dword(addr, data);
|
||||
}
|
||||
|
||||
|
||||
INLINE void arm7_cpu_write16(arm_state *arm, UINT32 addr, UINT16 data)
|
||||
{
|
||||
if( COPRO_CTRL & COPRO_CTRL_MMU_EN )
|
||||
{
|
||||
if (!arm7_tlb_translate( arm, &addr, ARM7_TLB_ABORT_D | ARM7_TLB_WRITE ))
|
||||
{
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
addr &= ~1;
|
||||
if ( arm->endian == ENDIANNESS_BIG )
|
||||
arm->program->write_word(addr, data);
|
||||
else
|
||||
arm->program->write_word(addr, data);
|
||||
}
|
||||
|
||||
INLINE void arm7_cpu_write8(arm_state *arm, UINT32 addr, UINT8 data)
|
||||
{
|
||||
if( COPRO_CTRL & COPRO_CTRL_MMU_EN )
|
||||
{
|
||||
if (!arm7_tlb_translate( arm, &addr, ARM7_TLB_ABORT_D | ARM7_TLB_WRITE ))
|
||||
{
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
if ( arm->endian == ENDIANNESS_BIG )
|
||||
arm->program->write_byte(addr, data);
|
||||
else
|
||||
arm->program->write_byte(addr, data);
|
||||
}
|
||||
|
||||
INLINE UINT32 arm7_cpu_read32(arm_state *arm, UINT32 addr)
|
||||
{
|
||||
UINT32 result;
|
||||
|
||||
if( COPRO_CTRL & COPRO_CTRL_MMU_EN )
|
||||
{
|
||||
if (!arm7_tlb_translate( arm, &addr, ARM7_TLB_ABORT_D | ARM7_TLB_READ ))
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
if (addr & 3)
|
||||
{
|
||||
if ( arm->endian == ENDIANNESS_BIG )
|
||||
result = arm->program->read_dword(addr & ~3);
|
||||
else
|
||||
result = arm->program->read_dword(addr & ~3);
|
||||
result = (result >> (8 * (addr & 3))) | (result << (32 - (8 * (addr & 3))));
|
||||
}
|
||||
else
|
||||
{
|
||||
if ( arm->endian == ENDIANNESS_BIG )
|
||||
result = arm->program->read_dword(addr);
|
||||
else
|
||||
result = arm->program->read_dword(addr);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
INLINE UINT16 arm7_cpu_read16(arm_state *arm, UINT32 addr)
|
||||
{
|
||||
UINT16 result;
|
||||
|
||||
if( COPRO_CTRL & COPRO_CTRL_MMU_EN )
|
||||
{
|
||||
if (!arm7_tlb_translate( arm, &addr, ARM7_TLB_ABORT_D | ARM7_TLB_READ ))
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
if ( arm->endian == ENDIANNESS_BIG )
|
||||
result = arm->program->read_word(addr & ~1);
|
||||
else
|
||||
result = arm->program->read_word(addr & ~1);
|
||||
|
||||
if (addr & 1)
|
||||
{
|
||||
result = ((result >> 8) & 0xff) | ((result & 0xff) << 8);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
INLINE UINT8 arm7_cpu_read8(arm_state *arm, UINT32 addr)
|
||||
{
|
||||
if( COPRO_CTRL & COPRO_CTRL_MMU_EN )
|
||||
{
|
||||
if (!arm7_tlb_translate( arm, &addr, ARM7_TLB_ABORT_D | ARM7_TLB_READ ))
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
// Handle through normal 8 bit handler (for 32 bit cpu)
|
||||
if ( arm->endian == ENDIANNESS_BIG )
|
||||
return arm->program->read_byte(addr);
|
||||
else
|
||||
return arm->program->read_byte(addr);
|
||||
}
|
||||
#define GetModeRegister(mode, rIndex) m_r[sRegisterTable[mode][rIndex]]
|
||||
#define SetModeRegister(mode, rIndex, value) m_r[sRegisterTable[mode][rIndex]] = value
|
||||
|
||||
|
||||
/* Macros that can be re-defined for custom cpu implementations - The core expects these to be defined */
|
||||
/* In this case, we are using the default arm7 handlers (supplied by the core)
|
||||
- but simply changes these and define your own if needed for cpu implementation specific needs */
|
||||
#define READ8(addr) arm7_cpu_read8(arm, addr)
|
||||
#define WRITE8(addr,data) arm7_cpu_write8(arm, addr,data)
|
||||
#define READ16(addr) arm7_cpu_read16(arm, addr)
|
||||
#define WRITE16(addr,data) arm7_cpu_write16(arm, addr,data)
|
||||
#define READ32(addr) arm7_cpu_read32(arm, addr)
|
||||
#define WRITE32(addr,data) arm7_cpu_write32(arm, addr,data)
|
||||
#define READ8(addr) arm7_cpu_read8(addr)
|
||||
#define WRITE8(addr,data) arm7_cpu_write8(addr,data)
|
||||
#define READ16(addr) arm7_cpu_read16(addr)
|
||||
#define WRITE16(addr,data) arm7_cpu_write16(addr,data)
|
||||
#define READ32(addr) arm7_cpu_read32(addr)
|
||||
#define WRITE32(addr,data) arm7_cpu_write32(addr,data)
|
||||
#define PTR_READ32 &arm7_cpu_read32
|
||||
#define PTR_WRITE32 &arm7_cpu_write32
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,8 +0,0 @@
|
||||
|
||||
const void arm7ops_0123(arm_state *arm, UINT32 insn);
|
||||
const void arm7ops_4567(arm_state *arm, UINT32 insn);
|
||||
const void arm7ops_89(arm_state *arm, UINT32 insn);
|
||||
const void arm7ops_ab(arm_state *arm, UINT32 insn);
|
||||
const void arm7ops_cd(arm_state *arm, UINT32 insn);
|
||||
const void arm7ops_e(arm_state *arm, UINT32 insn);
|
||||
const void arm7ops_f(arm_state *arm, UINT32 insn);
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,103 +0,0 @@
|
||||
|
||||
|
||||
|
||||
const void tg00_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg00_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg01_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg01_10(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg01_11(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg01_12(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg01_13(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg02_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg02_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg03_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg03_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_00(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_01(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_02(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_03(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_04(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_05(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_06(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_07(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_08(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_09(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_0a(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_0b(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_0c(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_0d(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_0e(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_00_0f(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_00(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_01(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_02(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_03(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_10(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_11(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_12(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_13(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_20(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_21(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_22(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_23(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_30(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_31(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_32(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_01_33(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg04_0203(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg05_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg05_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg05_2(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg05_3(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg05_4(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg05_5(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg05_6(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg05_7(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg06_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg06_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg07_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg07_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg08_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg08_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg09_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg09_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0a_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0a_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_2(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_3(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_4(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_5(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_6(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_7(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_8(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_9(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_a(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_b(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_c(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_d(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_e(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0b_f(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0c_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0c_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_2(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_3(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_4(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_5(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_6(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_7(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_8(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_9(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_a(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_b(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_c(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_d(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_e(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0d_f(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0e_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0e_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0f_0(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
const void tg0f_1(arm_state *arm, UINT32 pc, UINT32 insn);
|
||||
@ -95,7 +95,9 @@ $(CPUOBJ)/arm7/arm7.o: $(CPUSRC)/arm7/arm7.c \
|
||||
$(CPUSRC)/arm7/arm7help.h \
|
||||
$(CPUSRC)/arm7/arm7thmb.c \
|
||||
$(CPUSRC)/arm7/arm7ops.c \
|
||||
$(CPUSRC)/arm7/arm7core.c
|
||||
$(CPUSRC)/arm7/arm7core.c \
|
||||
$(CPUSRC)/arm7/arm7drc.c \
|
||||
$(CPUSRC)/arm7/arm7tdrc.c
|
||||
|
||||
$(CPUOBJ)/arm7/arm7ops.o: $(CPUSRC)/arm7/arm7ops.c \
|
||||
$(CPUSRC)/arm7/arm7.h \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user