diff --git a/src/devices/cpu/arm7/arm7ops.cpp b/src/devices/cpu/arm7/arm7ops.cpp
index f93b5c4473a..ea10a36be4d 100644
--- a/src/devices/cpu/arm7/arm7ops.cpp
+++ b/src/devices/cpu/arm7/arm7ops.cpp
@@ -1549,15 +1549,18 @@ void arm7_cpu_device::arm9ops_1(uint32_t insn)
 	{
 		// unsupported (armv6 onwards only)
 		arm9ops_undef(insn);
+		R15 += 4;
 	}
 	else if ((insn & 0x00ff00f0) == 0x00010000) /* set endianness (SETEND) */
 	{
 		// unsupported (armv6 onwards only)
 		arm9ops_undef(insn);
+		R15 += 4;
 	}
 	else
 	{
 		arm9ops_undef(insn);
+		R15 += 4;
 	}
 }
 
@@ -1568,10 +1571,12 @@ void arm7_cpu_device::arm9ops_57(uint32_t insn)
 	{
 		// unsupported (armv6 onwards only)
 		arm9ops_undef(insn);
+		R15 += 4;
 	}
 	else
 	{
 		arm9ops_undef(insn);
+		R15 += 4;
 	}
 }
 
@@ -1582,15 +1587,18 @@ void arm7_cpu_device::arm9ops_89(uint32_t insn)
 	{
 		// unsupported (armv6 onwards only)
 		arm9ops_undef(insn);
+		R15 += 4;
 	}
 	else if ((insn & 0x00500f00) == 0x00100a00) /* Return From Exception (RFE) */
 	{
 		// unsupported (armv6 onwards only)
 		arm9ops_undef(insn);
+		R15 += 4;
 	}
 	else
 	{
 		arm9ops_undef(insn);
+		R15 += 4;
 	}
 }
 
@@ -1608,10 +1616,12 @@ void arm7_cpu_device::arm9ops_c(uint32_t insn)
 	{
 		// unsupported
 		arm9ops_undef(insn);
+		R15 += 4;
 	}
 	else
 	{
 		arm9ops_undef(insn);
+		R15 += 4;
 	}
 }
 
@@ -1620,6 +1630,7 @@ void arm7_cpu_device::arm9ops_e(uint32_t insn)
 	/* Additional coprocessor register transfer */
 	// unsupported
 	arm9ops_undef(insn);
+	R15 += 4;
 }