i8244: return 0 on write-only registers

This commit is contained in:
hap 2020-08-03 23:09:17 +02:00
parent ca3eaa5229
commit 0c548843e9
2 changed files with 8 additions and 7 deletions

View File

@ -8,6 +8,7 @@ TODO:
- NTSC has 263 scanlines, PAL has 313 scanlines, a quick fix will probably
cause small regressions here and there
- PAL has 228 clocks per line (so, 456 half clocks)
- are the 'reserved' registers like RAM, or does writing have no effect?
***************************************************************************/
@ -273,7 +274,6 @@ uint8_t i8244_device::read(offs_t offset)
data = m_y_beam_pos;
break;
case 0xa5:
if ((m_vdc.s.control & VDC_CONTROL_REG_STROBE_XY))
{
@ -282,9 +282,10 @@ uint8_t i8244_device::read(offs_t offset)
data = m_x_beam_pos;
break;
case 0xa7: case 0xa8: case 0xa9:
m_stream->update(); // updates sound shift registers
data = m_vdc.reg[offset];
case 0x02: case 0x06: case 0x0a: case 0x0e:
case 0xa3: case 0xa7: case 0xa8: case 0xa9:
// write-only registers
data = 0;
break;
default:

View File

@ -57,7 +57,7 @@ protected:
uint8_t reg[0x100];
struct {
struct {
uint8_t y,x,color,res;
uint8_t y,x,color,reserved;
} sprites[4];
struct {
uint8_t y,x,ptr,color;
@ -74,12 +74,12 @@ protected:
uint8_t color;
uint8_t y;
uint8_t x;
uint8_t res;
uint8_t reserved;
uint8_t shift1;
uint8_t shift2;
uint8_t shift3;
uint8_t sound;
uint8_t res2[5+0x10];
uint8_t reserved2[5+0x10];
uint8_t hgrid[2][0x10];
uint8_t vgrid[0x10];
} s;