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-machine/pxa255.cpp: Cleaned up peripheral emulation code. (#11780) [Ryan Holtz]

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* Implemented free-running timer.
* Eliminated internal header in favor of scoped enums.
* Eliminated double-dispatch switch/case in handlers, in favor of individual register handlers.
* Reworked GPIO handling for correctness.

-misc/39in1.cpp: Fixed GPIO hookup, now boots on its own. [Ryan Holtz]
This commit is contained in:
MooglyGuy 2023-11-27 20:19:45 +01:00 committed by GitHub
parent c626209de7
commit 0c9f5dd225
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GPG Key ID: 4AEE18F83AFDEB23
6 changed files with 2136 additions and 2127 deletions
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1
scripts/src/machine.lua
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@ -3000,7 +3000,6 @@ if (MACHINES["PXA255"]~=null) then
files {
MAME_DIR .. "src/devices/machine/pxa255.cpp",
MAME_DIR .. "src/devices/machine/pxa255.h",
MAME_DIR .. "src/devices/machine/pxa255defs.h",
}
end

3167
src/devices/machine/pxa255.cpp
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File diff suppressed because it is too large Load Diff

538
src/devices/machine/pxa255.h
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@ -19,253 +19,461 @@
#include "sound/dmadac.h"
#include "emupal.h"
#include "pxa255defs.h"
class pxa255_periphs_device : public device_t
{
public:
template <typename T>
pxa255_periphs_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&cpu_tag)
pxa255_periphs_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock, T &&cpu_tag)
: pxa255_periphs_device(mconfig, tag, owner, clock)
{
m_maincpu.set_tag(std::forward<T>(cpu_tag));
}
pxa255_periphs_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
pxa255_periphs_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
auto gpio0_write() { return m_gpio0_w.bind(); }
auto gpio0_read() { return m_gpio0_r.bind(); }
auto gpio1_write() { return m_gpio1_w.bind(); }
auto gpio1_read() { return m_gpio1_r.bind(); }
auto gpio2_write() { return m_gpio2_w.bind(); }
auto gpio2_read() { return m_gpio2_r.bind(); }
template <int Bit> auto gpio_out() { return m_gpio_w[Bit].bind(); }
template <int Bit> void gpio_in(int state);
uint32_t dma_r(offs_t offset, uint32_t mem_mask = ~0);
void dma_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
uint32_t i2s_r(offs_t offset, uint32_t mem_mask = ~0);
void i2s_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
uint32_t rtc_r(offs_t offset, uint32_t mem_mask = ~0);
void rtc_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
uint32_t ostimer_r(offs_t offset, uint32_t mem_mask = ~0);
void ostimer_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
uint32_t intc_r(offs_t offset, uint32_t mem_mask = ~0);
void intc_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
void gpio_bit_w(offs_t offset, uint8_t data, uint8_t mem_mask = ~0);
uint32_t gpio_r(offs_t offset, uint32_t mem_mask = ~0);
void gpio_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
uint32_t lcd_r(offs_t offset, uint32_t mem_mask = ~0);
void lcd_w(address_space &space, offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
uint32_t power_r(offs_t offset, uint32_t mem_mask = ~0);
void power_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
uint32_t clocks_r(offs_t offset, uint32_t mem_mask = ~0);
void clocks_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
void map(address_map &map);
// gpio_bit_w
protected:
virtual void device_add_mconfig(machine_config &config) override;
virtual void device_start() override;
virtual void device_reset() override;
static constexpr u32 INTERNAL_OSC = 3686400;
// DMA Hardware
void dma_irq_check();
void dma_load_descriptor_and_start(int channel);
void ostimer_irq_check();
void update_interrupts();
void lcd_load_dma_descriptor(address_space & space, uint32_t address, int channel);
void lcd_irq_check();
void lcd_dma_kickoff(int channel);
void lcd_check_load_next_branch(int channel);
uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
TIMER_CALLBACK_MEMBER(dma_end_tick);
TIMER_CALLBACK_MEMBER(audio_dma_end_tick);
TIMER_CALLBACK_MEMBER(ostimer_match_tick);
TIMER_CALLBACK_MEMBER(lcd_dma_eof_tick);
TIMER_CALLBACK_MEMBER(rtc_tick);
TIMER_CALLBACK_MEMBER(dma_end_tick);
void dma_finish(int channel);
void set_irq_line(uint32_t line, int state);
u32 dma_dcsr_r(offs_t offset, u32 mem_mask);
void dma_dcsr_w(offs_t offset, u32 data, u32 mem_mask);
u32 dma_dint_r(offs_t offset, u32 mem_mask);
void dma_dint_w(offs_t offset, u32 data, u32 mem_mask);
u32 dma_drcmr_r(offs_t offset, u32 mem_mask);
void dma_drcmr_w(offs_t offset, u32 data, u32 mem_mask);
template <int Which> u32 dma_ddadr_r(offs_t offset, u32 mem_mask);
template <int Which> void dma_ddadr_w(offs_t offset, u32 data, u32 mem_mask);
template <int Which> u32 dma_dsadr_r(offs_t offset, u32 mem_mask);
template <int Which> void dma_dsadr_w(offs_t offset, u32 data, u32 mem_mask);
template <int Which> u32 dma_dtadr_r(offs_t offset, u32 mem_mask);
template <int Which> void dma_dtadr_w(offs_t offset, u32 data, u32 mem_mask);
template <int Which> u32 dma_dcmd_r(offs_t offset, u32 mem_mask);
template <int Which> void dma_dcmd_w(offs_t offset, u32 data, u32 mem_mask);
enum dma_bits_t : u32
{
DCSR_BUSERRINTR = 1u << 0,
DCSR_STARTINTR = 1u << 1,
DCSR_ENDINTR = 1u << 2,
DCSR_STOPSTATE = 1u << 3,
DCSR_REQPEND = 1u << 8,
DCSR_STOPIRQ = 1u << 29,
DCSR_NODESCFETCH = 1u << 30,
DCSR_RUN = 1u << 31,
DDADR_STOP = 1u << 0,
DCMD_INCSRCADDR = 1u << 31,
DCMD_INCTRGADDR = 1u << 30,
DCMD_STARTIRQEN = 1u << 22,
DCMD_ENDIRQEN = 1u << 21,
DCMD_SIZE_SHIFT = 16,
DCMD_SIZE_MASK = 3,
DCMD_SIZE_0 = 0,
DCMD_SIZE_8 = 1,
DCMD_SIZE_16 = 2,
DCMD_SIZE_32 = 3
};
struct dma_regs
{
uint32_t dcsr[16];
uint32_t pad0[44];
u32 dcsr[16];
u32 dint;
u32 drcmr[40];
uint32_t dint;
uint32_t pad1[3];
uint32_t drcmr[40];
uint32_t pad2[24];
uint32_t ddadr[16];
uint32_t dsadr[16];
uint32_t dtadr[16];
uint32_t dcmd[16];
u32 ddadr[16];
u32 dsadr[16];
u32 dtadr[16];
u32 dcmd[16];
emu_timer* timer[16];
};
struct i2s_regs
{
uint32_t sacr0;
uint32_t sacr1;
uint32_t pad0;
dma_regs m_dma_regs;
uint32_t sasr0;
uint32_t pad1;
uint32_t saimr;
uint32_t saicr;
uint32_t pad2[17];
uint32_t sadiv;
uint32_t pad3[6];
uint32_t sadr;
};
// RTC Hardware
TIMER_CALLBACK_MEMBER(rtc_tick);
u32 rtc_rcnr_r(offs_t offset, u32 mem_mask);
void rtc_rcnr_w(offs_t offset, u32 data, u32 mem_mask);
u32 rtc_rtar_r(offs_t offset, u32 mem_mask);
void rtc_rtar_w(offs_t offset, u32 data, u32 mem_mask);
u32 rtc_rtsr_r(offs_t offset, u32 mem_mask);
void rtc_rtsr_w(offs_t offset, u32 data, u32 mem_mask);
u32 rtc_rttr_r(offs_t offset, u32 mem_mask);
void rtc_rttr_w(offs_t offset, u32 data, u32 mem_mask);
struct rtc_regs
{
uint32_t rcnr;
uint32_t rtar;
uint32_t rtsr;
uint32_t rttr;
u32 rcnr;
u32 rtar;
u32 rtsr;
u32 rttr;
emu_timer *timer;
};
rtc_regs m_rtc_regs;
// I2S (Audio) Hardware
u32 i2s_sacr0_r(offs_t offset, u32 mem_mask);
void i2s_sacr0_w(offs_t offset, u32 data, u32 mem_mask);
u32 i2s_sacr1_r(offs_t offset, u32 mem_mask);
void i2s_sacr1_w(offs_t offset, u32 data, u32 mem_mask);
u32 i2s_sasr0_r(offs_t offset, u32 mem_mask);
void i2s_sasr0_w(offs_t offset, u32 data, u32 mem_mask);
u32 i2s_saimr_r(offs_t offset, u32 mem_mask);
void i2s_saimr_w(offs_t offset, u32 data, u32 mem_mask);
u32 i2s_saicr_r(offs_t offset, u32 mem_mask);
void i2s_saicr_w(offs_t offset, u32 data, u32 mem_mask);
u32 i2s_sadiv_r(offs_t offset, u32 mem_mask);
void i2s_sadiv_w(offs_t offset, u32 data, u32 mem_mask);
u32 i2s_sadr_r(offs_t offset, u32 mem_mask);
void i2s_sadr_w(offs_t offset, u32 data, u32 mem_mask);
enum i2s_bits_t : u32
{
SASR0_TNF = 1u << 0,
SASR0_RNE = 1u << 1,
SASR0_BSY = 1u << 2,
SASR0_TFS = 1u << 3,
SASR0_RFS = 1u << 4,
SASR0_TUR = 1u << 5,
SASR0_ROR = 1u << 6,
SASR0_TFL = 15u << 8,
SASR0_RFL = 15u << 12,
SAICR_TUR = 1u << 5,
SAICR_ROR = 1u << 6,
};
struct i2s_regs
{
u32 sacr0;
u32 sacr1;
u32 sasr0;
u32 saimr;
u32 saicr;
u32 sadiv;
u32 sadr;
};
i2s_regs m_i2s_regs;
// Timer Hardware
void ostimer_irq_check();
TIMER_CALLBACK_MEMBER(ostimer_match_tick);
template <int Which> void ostimer_update_interrupts();
void ostimer_update_count();
template <int Which> u32 tmr_osmr_r(offs_t offset, u32 mem_mask);
template <int Which> void tmr_osmr_w(offs_t offset, u32 data, u32 mem_mask);
u32 tmr_oscr_r(offs_t offset, u32 mem_mask);
void tmr_oscr_w(offs_t offset, u32 data, u32 mem_mask);
u32 tmr_ossr_r(offs_t offset, u32 mem_mask);
void tmr_ossr_w(offs_t offset, u32 data, u32 mem_mask);
u32 tmr_ower_r(offs_t offset, u32 mem_mask);
void tmr_ower_w(offs_t offset, u32 data, u32 mem_mask);
u32 tmr_oier_r(offs_t offset, u32 mem_mask);
void tmr_oier_w(offs_t offset, u32 data, u32 mem_mask);
enum tmr_bits_t : u32
{
OSSR_M0 = 1u << 0,
OSSR_M1 = 1u << 1,
OSSR_M2 = 1u << 2,
OSSR_M3 = 1u << 3,
OIER_E0 = 1u << 0,
OIER_E1 = 1u << 1,
OIER_E2 = 1u << 2,
OIER_E3 = 1u << 3
};
struct ostmr_regs
{
uint32_t osmr[4];
uint32_t oscr;
uint32_t ossr;
uint32_t ower;
uint32_t oier;
u32 osmr[4];
u32 oscr;
u32 ossr;
u32 ower;
u32 oier;
emu_timer* timer[4];
attotime last_count_sync;
};
ostmr_regs m_ostimer_regs;
// Interrupt Hardware
enum intc_bits_t : u32
{
INT_HUART = 1u << 7,
INT_GPIO0 = 1u << 8,
INT_GPIO1 = 1u << 9,
INT_GPIO84_2 = 1u << 10,
INT_USB = 1u << 11,
INT_PMU = 1u << 12,
INT_I2S = 1u << 13,
INT_AC97 = 1u << 14,
INT_NETWORK = 1u << 16,
INT_LCD = 1u << 17,
INT_I2C = 1u << 18,
INT_ICP = 1u << 19,
INT_STUART = 1u << 20,
INT_BTUART = 1u << 21,
INT_FFUART = 1u << 22,
INT_MMC = 1u << 23,
INT_SSP = 1u << 24,
INT_DMA = 1u << 25,
INT_OSTIMER0 = 1u << 26,
INT_OSTIMER1 = 1u << 27,
INT_OSTIMER2 = 1u << 28,
INT_OSTIMER3 = 1u << 29,
INT_RTC_HZ = 1u << 30,
INT_RTC_ALARM = 1u << 31
};
void update_interrupts();
u32 intc_icip_r(offs_t offset, u32 mem_mask);
void intc_icip_w(offs_t offset, u32 data, u32 mem_mask);
u32 intc_icmr_r(offs_t offset, u32 mem_mask);
void intc_icmr_w(offs_t offset, u32 data, u32 mem_mask);
u32 intc_iclr_r(offs_t offset, u32 mem_mask);
void intc_iclr_w(offs_t offset, u32 data, u32 mem_mask);
u32 intc_icfp_r(offs_t offset, u32 mem_mask);
void intc_icfp_w(offs_t offset, u32 data, u32 mem_mask);
u32 intc_icpr_r(offs_t offset, u32 mem_mask);
void intc_icpr_w(offs_t offset, u32 data, u32 mem_mask);
u32 intc_iccr_r(offs_t offset, u32 mem_mask);
void intc_iccr_w(offs_t offset, u32 data, u32 mem_mask);
struct intc_regs
{
uint32_t icip;
uint32_t icmr;
uint32_t iclr;
uint32_t icfp;
uint32_t icpr;
uint32_t iccr;
u32 icip;
u32 icmr;
u32 iclr;
u32 icfp;
u32 icpr;
u32 iccr;
};
intc_regs m_intc_regs;
// GPIO Hardware
template <int Which> void update_gpio_outputs(const u32 old);
template <int Which> void check_gpio_irqs(const u32 old);
template <int Which> u32 gpio_gplr_r(offs_t offset, u32 mem_mask);
template <int Which> void gpio_gplr_w(offs_t offset, u32 data, u32 mem_mask);
template <int Which> u32 gpio_gpdr_r(offs_t offset, u32 mem_mask);
template <int Which> void gpio_gpdr_w(offs_t offset, u32 data, u32 mem_mask);
template <int Which> u32 gpio_gpsr_r(offs_t offset, u32 mem_mask);
template <int Which> void gpio_gpsr_w(offs_t offset, u32 data, u32 mem_mask);
template <int Which> u32 gpio_gpcr_r(offs_t offset, u32 mem_mask);
template <int Which> void gpio_gpcr_w(offs_t offset, u32 data, u32 mem_mask);
template <int Which> u32 gpio_grer_r(offs_t offset, u32 mem_mask);
template <int Which> void gpio_grer_w(offs_t offset, u32 data, u32 mem_mask);
template <int Which> u32 gpio_gfer_r(offs_t offset, u32 mem_mask);
template <int Which> void gpio_gfer_w(offs_t offset, u32 data, u32 mem_mask);
template <int Which> u32 gpio_gedr_r(offs_t offset, u32 mem_mask);
template <int Which> void gpio_gedr_w(offs_t offset, u32 data, u32 mem_mask);
template <int Which> u32 gpio_gafrl_r(offs_t offset, u32 mem_mask);
template <int Which> void gpio_gafrl_w(offs_t offset, u32 data, u32 mem_mask);
template <int Which> u32 gpio_gafru_r(offs_t offset, u32 mem_mask);
template <int Which> void gpio_gafru_w(offs_t offset, u32 data, u32 mem_mask);
struct gpio_regs
{
uint32_t gplr0; // GPIO Pin-Level
uint32_t gplr1;
uint32_t gplr2;
u32 gpdr[3];
u32 gpsr[3];
u32 gpcr[3];
u32 grer[3];
u32 gfer[3];
u32 gedr[3];
u32 gafrl[3];
u32 gafru[3];
u32 out_data[3]; // Output data
u32 in_data[3]; // Input data
};
uint32_t gpdr0;
uint32_t gpdr1;
uint32_t gpdr2;
gpio_regs m_gpio_regs;
uint32_t gpsr0;
uint32_t gpsr1;
uint32_t gpsr2;
// LCD Hardware
u32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
uint32_t gpcr0;
uint32_t gpcr1;
uint32_t gpcr2;
TIMER_CALLBACK_MEMBER(lcd_dma_eof_tick);
void lcd_load_dma_descriptor(u32 address, int channel);
void lcd_irq_check();
void lcd_dma_kickoff(int channel);
void lcd_check_load_next_branch(int channel);
uint32_t grer0;
uint32_t grer1;
uint32_t grer2;
template <int Which> u32 lcd_lccr_r(offs_t offset, u32 mem_mask);
template <int Which> void lcd_lccr_w(offs_t offset, u32 data, u32 mem_mask);
template <int Which> u32 lcd_fbr_r(offs_t offset, u32 mem_mask);
template <int Which> void lcd_fbr_w(offs_t offset, u32 data, u32 mem_mask);
u32 lcd_lcsr_r(offs_t offset, u32 mem_mask);
void lcd_lcsr_w(offs_t offset, u32 data, u32 mem_mask);
u32 lcd_liidr_r(offs_t offset, u32 mem_mask);
void lcd_liidr_w(offs_t offset, u32 data, u32 mem_mask);
u32 lcd_trgbr_r(offs_t offset, u32 mem_mask);
void lcd_trgbr_w(offs_t offset, u32 data, u32 mem_mask);
u32 lcd_tcr_r(offs_t offset, u32 mem_mask);
void lcd_tcr_w(offs_t offset, u32 data, u32 mem_mask);
template <int Which> u32 lcd_fdadr_r(offs_t offset, u32 mem_mask);
template <int Which> void lcd_fdadr_w(offs_t offset, u32 data, u32 mem_mask);
template <int Which> u32 lcd_fsadr_r(offs_t offset, u32 mem_mask);
template <int Which> void lcd_fsadr_w(offs_t offset, u32 data, u32 mem_mask);
template <int Which> u32 lcd_fidr_r(offs_t offset, u32 mem_mask);
template <int Which> void lcd_fidr_w(offs_t offset, u32 data, u32 mem_mask);
template <int Which> u32 lcd_ldcmd_r(offs_t offset, u32 mem_mask);
template <int Which> void lcd_ldcmd_w(offs_t offset, u32 data, u32 mem_mask);
uint32_t gfer0;
uint32_t gfer1;
uint32_t gfer2;
enum lcd_bits_t : u32
{
LCCR0_ENB = 1u << 0,
LCCR0_CMS = 1u << 1,
LCCR0_SDS = 1u << 2,
LCCR0_LDM = 1u << 3,
LCCR0_SFM = 1u << 4,
LCCR0_IUM = 1u << 5,
LCCR0_EFM = 1u << 6,
LCCR0_PAS = 1u << 7,
LCCR0_DPD = 1u << 9,
LCCR0_DIS = 1u << 10,
LCCR0_QDM = 1u << 11,
LCCR0_PDD = 0xff << 12,
LCCR0_BM = 1u << 20,
LCCR0_OUM = 1u << 21,
uint32_t gedr0;
uint32_t gedr1;
uint32_t gedr2;
LCCR1_PPL = 0x000003ff,
uint32_t gafr0l;
uint32_t gafr0u;
uint32_t gafr1l;
uint32_t gafr1u;
uint32_t gafr2l;
uint32_t gafr2u;
LCCR2_LPP = 0x000003ff,
LCSR_LDD = 1u << 0,
LCSR_SOF = 1u << 1,
LCSR_BER = 1u << 2,
LCSR_ABC = 1u << 3,
LCSR_IUL = 1u << 4,
LCSR_IUU = 1u << 5,
LCSR_OU = 1u << 6,
LCSR_QD = 1u << 7,
LCSR_EOF = 1u << 8,
LCSR_BS = 1u << 9,
LCSR_SINT = 1u << 10,
LDCMD_EOFINT = 1u << 21,
LDCMD_SOFINT = 1u << 22,
LDCMD_PAL = 1u << 26
};
struct lcd_dma_regs
{
uint32_t fdadr;
uint32_t fsadr;
uint32_t fidr;
uint32_t ldcmd;
u32 fdadr;
u32 fsadr;
u32 fidr;
u32 ldcmd;
emu_timer *eof;
};
struct lcd_regs
{
uint32_t lccr0;
uint32_t lccr1;
uint32_t lccr2;
uint32_t lccr3;
u32 lccr[4];
uint32_t fbr[2];
u32 fbr[2];
uint32_t lcsr;
uint32_t liidr;
uint32_t trgbr;
uint32_t tcr;
u32 lcsr;
u32 liidr;
u32 trgbr;
u32 tcr;
lcd_dma_regs dma[2];
};
lcd_regs m_lcd_regs;
// Power Management Hardware
u32 pwr_pmcr_r(offs_t offset, u32 mem_mask);
void pwr_pmcr_w(offs_t offset, u32 data, u32 mem_mask);
u32 pwr_pssr_r(offs_t offset, u32 mem_mask);
void pwr_pssr_w(offs_t offset, u32 data, u32 mem_mask);
u32 pwr_pspr_r(offs_t offset, u32 mem_mask);
void pwr_pspr_w(offs_t offset, u32 data, u32 mem_mask);
u32 pwr_pwer_r(offs_t offset, u32 mem_mask);
void pwr_pwer_w(offs_t offset, u32 data, u32 mem_mask);
u32 pwr_prer_r(offs_t offset, u32 mem_mask);
void pwr_prer_w(offs_t offset, u32 data, u32 mem_mask);
u32 pwr_pfer_r(offs_t offset, u32 mem_mask);
void pwr_pfer_w(offs_t offset, u32 data, u32 mem_mask);
u32 pwr_pedr_r(offs_t offset, u32 mem_mask);
void pwr_pedr_w(offs_t offset, u32 data, u32 mem_mask);
u32 pwr_pcfr_r(offs_t offset, u32 mem_mask);
void pwr_pcfr_w(offs_t offset, u32 data, u32 mem_mask);
template <int Which> u32 pwr_pgsr_r(offs_t offset, u32 mem_mask);
template <int Which> void pwr_pgsr_w(offs_t offset, u32 data, u32 mem_mask);
u32 pwr_rcsr_r(offs_t offset, u32 mem_mask);
u32 pwr_pmfw_r(offs_t offset, u32 mem_mask);
void pwr_pmfw_w(offs_t offset, u32 data, u32 mem_mask);
struct power_regs
{
uint32_t pmcr;
uint32_t pssr;
uint32_t pspr;
uint32_t pwer;
uint32_t prer;
uint32_t pfer;
uint32_t pedr;
uint32_t pcfr;
uint32_t pgsr0;
uint32_t pgsr1;
uint32_t pgsr2;
uint32_t rcsr;
uint32_t pmfw;
u32 pmcr;
u32 pssr;
u32 pspr;
u32 pwer;
u32 prer;
u32 pfer;
u32 pedr;
u32 pcfr;
u32 pgsr[3];
u32 rcsr;
u32 pmfw;
};
struct clocks_regs
{
uint32_t cccr;
uint32_t cken;
uint32_t oscc;
};
dma_regs m_dma_regs;
i2s_regs m_i2s_regs;
rtc_regs m_rtc_regs;
ostmr_regs m_ostimer_regs;
intc_regs m_intc_regs;
gpio_regs m_gpio_regs;
lcd_regs m_lcd_regs;
power_regs m_power_regs;
clocks_regs m_clocks_regs;
devcb_write32 m_gpio0_w;
devcb_write32 m_gpio1_w;
devcb_write32 m_gpio2_w;
devcb_read32 m_gpio0_r;
devcb_read32 m_gpio1_r;
devcb_read32 m_gpio2_r;
// System Clock Hardware
u32 clk_cccr_r(offs_t offset, u32 mem_mask);
void clk_cccr_w(offs_t offset, u32 data, u32 mem_mask);
u32 clk_cken_r(offs_t offset, u32 mem_mask);
void clk_cken_w(offs_t offset, u32 data, u32 mem_mask);
u32 clk_oscc_r(offs_t offset, u32 mem_mask);
void clk_oscc_w(offs_t offset, u32 data, u32 mem_mask);
struct clk_regs
{
u32 cccr;
u32 cken;
u32 oscc;
};
clk_regs m_clk_regs;
void set_irq_line(u32 line, int state);
devcb_write_line::array<96> m_gpio_w;
required_device<cpu_device> m_maincpu;
required_device_array<dmadac_sound_device, 2> m_dmadac;
required_device<palette_device> m_palette;
std::unique_ptr<uint32_t[]> m_lcd_palette; // 0x100
std::unique_ptr<uint8_t[]> m_lcd_framebuffer; // 0x100000
std::unique_ptr<int16_t[]> m_samples; // 0x1000
std::unique_ptr<u32[]> m_lcd_palette; // 0x100
std::unique_ptr<u8[]> m_lcd_framebuffer; // 0x100000
std::unique_ptr<s16[]> m_samples; // 0x1000
};
DECLARE_DEVICE_TYPE(PXA255_PERIPHERALS, pxa255_periphs_device)

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src/devices/machine/pxa255defs.h
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@ -1,427 +0,0 @@
// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/**************************************************************************
*
* Intel XScale PXA255 peripheral emulation defines
*
**************************************************************************/
#ifndef MAME_MACHINE_PXA255DEFS
#define MAME_MACHINE_PXA255DEFS
#pragma once
/*
PXA255 DMA controller
pg. 151 to 182, PXA255 Processor Developers Manual [278693-002].pdf
*/
#define PXA255_DMA_BASE_ADDR (0x40000000)
#define PXA255_DCSR0 (PXA255_DMA_BASE_ADDR + 0x00000000)
#define PXA255_DCSR1 (PXA255_DMA_BASE_ADDR + 0x00000004)
#define PXA255_DCSR2 (PXA255_DMA_BASE_ADDR + 0x00000008)
#define PXA255_DCSR3 (PXA255_DMA_BASE_ADDR + 0x0000000c)
#define PXA255_DCSR4 (PXA255_DMA_BASE_ADDR + 0x00000010)
#define PXA255_DCSR5 (PXA255_DMA_BASE_ADDR + 0x00000014)
#define PXA255_DCSR6 (PXA255_DMA_BASE_ADDR + 0x00000018)
#define PXA255_DCSR7 (PXA255_DMA_BASE_ADDR + 0x0000001c)
#define PXA255_DCSR8 (PXA255_DMA_BASE_ADDR + 0x00000020)
#define PXA255_DCSR9 (PXA255_DMA_BASE_ADDR + 0x00000024)
#define PXA255_DCSR10 (PXA255_DMA_BASE_ADDR + 0x00000028)
#define PXA255_DCSR11 (PXA255_DMA_BASE_ADDR + 0x0000002c)
#define PXA255_DCSR12 (PXA255_DMA_BASE_ADDR + 0x00000030)
#define PXA255_DCSR13 (PXA255_DMA_BASE_ADDR + 0x00000034)
#define PXA255_DCSR14 (PXA255_DMA_BASE_ADDR + 0x00000038)
#define PXA255_DCSR15 (PXA255_DMA_BASE_ADDR + 0x0000003c)
#define PXA255_DCSR_RUN (0x80000000)
#define PXA255_DCSR_NODESCFETCH (0x40000000)
#define PXA255_DCSR_STOPIRQ (0x20000000)
#define PXA255_DCSR_REQPEND (0x00000100)
#define PXA255_DCSR_STOPSTATE (0x00000008)
#define PXA255_DCSR_ENDINTR (0x00000004)
#define PXA255_DCSR_STARTINTR (0x00000002)
#define PXA255_DCSR_BUSERRINTR (0x00000001)
#define PXA255_DINT (PXA255_DMA_BASE_ADDR + 0x000000f0)
#define PXA255_DRCMR0 (PXA255_DMA_BASE_ADDR + 0x00000100)
#define PXA255_DRCMR1 (PXA255_DMA_BASE_ADDR + 0x00000104)
#define PXA255_DRCMR2 (PXA255_DMA_BASE_ADDR + 0x00000108)
#define PXA255_DRCMR3 (PXA255_DMA_BASE_ADDR + 0x0000010c)
#define PXA255_DRCMR4 (PXA255_DMA_BASE_ADDR + 0x00000110)
#define PXA255_DRCMR5 (PXA255_DMA_BASE_ADDR + 0x00000114)
#define PXA255_DRCMR6 (PXA255_DMA_BASE_ADDR + 0x00000118)
#define PXA255_DRCMR7 (PXA255_DMA_BASE_ADDR + 0x0000011c)
#define PXA255_DRCMR8 (PXA255_DMA_BASE_ADDR + 0x00000120)
#define PXA255_DRCMR9 (PXA255_DMA_BASE_ADDR + 0x00000124)
#define PXA255_DRCMR10 (PXA255_DMA_BASE_ADDR + 0x00000128)
#define PXA255_DRCMR11 (PXA255_DMA_BASE_ADDR + 0x0000012c)
#define PXA255_DRCMR12 (PXA255_DMA_BASE_ADDR + 0x00000130)
#define PXA255_DRCMR13 (PXA255_DMA_BASE_ADDR + 0x00000134)
#define PXA255_DRCMR14 (PXA255_DMA_BASE_ADDR + 0x00000138)
#define PXA255_DRCMR15 (PXA255_DMA_BASE_ADDR + 0x0000013c)
#define PXA255_DRCMR16 (PXA255_DMA_BASE_ADDR + 0x00000140)
#define PXA255_DRCMR17 (PXA255_DMA_BASE_ADDR + 0x00000144)
#define PXA255_DRCMR18 (PXA255_DMA_BASE_ADDR + 0x00000148)
#define PXA255_DRCMR19 (PXA255_DMA_BASE_ADDR + 0x0000014c)
#define PXA255_DRCMR20 (PXA255_DMA_BASE_ADDR + 0x00000150)
#define PXA255_DRCMR21 (PXA255_DMA_BASE_ADDR + 0x00000154)
#define PXA255_DRCMR22 (PXA255_DMA_BASE_ADDR + 0x00000158)
#define PXA255_DRCMR23 (PXA255_DMA_BASE_ADDR + 0x0000015c)
#define PXA255_DRCMR24 (PXA255_DMA_BASE_ADDR + 0x00000160)
#define PXA255_DRCMR25 (PXA255_DMA_BASE_ADDR + 0x00000164)
#define PXA255_DRCMR26 (PXA255_DMA_BASE_ADDR + 0x00000168)
#define PXA255_DRCMR27 (PXA255_DMA_BASE_ADDR + 0x0000016c)
#define PXA255_DRCMR28 (PXA255_DMA_BASE_ADDR + 0x00000170)
#define PXA255_DRCMR29 (PXA255_DMA_BASE_ADDR + 0x00000174)
#define PXA255_DRCMR30 (PXA255_DMA_BASE_ADDR + 0x00000178)
#define PXA255_DRCMR31 (PXA255_DMA_BASE_ADDR + 0x0000017c)
#define PXA255_DRCMR32 (PXA255_DMA_BASE_ADDR + 0x00000180)
#define PXA255_DRCMR33 (PXA255_DMA_BASE_ADDR + 0x00000184)
#define PXA255_DRCMR34 (PXA255_DMA_BASE_ADDR + 0x00000188)
#define PXA255_DRCMR35 (PXA255_DMA_BASE_ADDR + 0x0000018c)
#define PXA255_DRCMR36 (PXA255_DMA_BASE_ADDR + 0x00000190)
#define PXA255_DRCMR37 (PXA255_DMA_BASE_ADDR + 0x00000194)
#define PXA255_DRCMR38 (PXA255_DMA_BASE_ADDR + 0x00000198)
#define PXA255_DRCMR39 (PXA255_DMA_BASE_ADDR + 0x0000019c)
#define PXA255_DDADR0 (PXA255_DMA_BASE_ADDR + 0x00000200)
#define PXA255_DSADR0 (PXA255_DMA_BASE_ADDR + 0x00000204)
#define PXA255_DTADR0 (PXA255_DMA_BASE_ADDR + 0x00000208)
#define PXA255_DCMD0 (PXA255_DMA_BASE_ADDR + 0x0000020c)
#define PXA255_DDADR1 (PXA255_DMA_BASE_ADDR + 0x00000210)
#define PXA255_DSADR1 (PXA255_DMA_BASE_ADDR + 0x00000214)
#define PXA255_DTADR1 (PXA255_DMA_BASE_ADDR + 0x00000218)
#define PXA255_DCMD1 (PXA255_DMA_BASE_ADDR + 0x0000021c)
#define PXA255_DDADR2 (PXA255_DMA_BASE_ADDR + 0x00000220)
#define PXA255_DSADR2 (PXA255_DMA_BASE_ADDR + 0x00000224)
#define PXA255_DTADR2 (PXA255_DMA_BASE_ADDR + 0x00000228)
#define PXA255_DCMD2 (PXA255_DMA_BASE_ADDR + 0x0000022c)
#define PXA255_DDADR3 (PXA255_DMA_BASE_ADDR + 0x00000230)
#define PXA255_DSADR3 (PXA255_DMA_BASE_ADDR + 0x00000234)
#define PXA255_DTADR3 (PXA255_DMA_BASE_ADDR + 0x00000238)
#define PXA255_DCMD3 (PXA255_DMA_BASE_ADDR + 0x0000023c)
#define PXA255_DDADR4 (PXA255_DMA_BASE_ADDR + 0x00000240)
#define PXA255_DSADR4 (PXA255_DMA_BASE_ADDR + 0x00000244)
#define PXA255_DTADR4 (PXA255_DMA_BASE_ADDR + 0x00000248)
#define PXA255_DCMD4 (PXA255_DMA_BASE_ADDR + 0x0000024c)
#define PXA255_DDADR5 (PXA255_DMA_BASE_ADDR + 0x00000250)
#define PXA255_DSADR5 (PXA255_DMA_BASE_ADDR + 0x00000254)
#define PXA255_DTADR5 (PXA255_DMA_BASE_ADDR + 0x00000258)
#define PXA255_DCMD5 (PXA255_DMA_BASE_ADDR + 0x0000025c)
#define PXA255_DDADR6 (PXA255_DMA_BASE_ADDR + 0x00000260)
#define PXA255_DSADR6 (PXA255_DMA_BASE_ADDR + 0x00000264)
#define PXA255_DTADR6 (PXA255_DMA_BASE_ADDR + 0x00000268)
#define PXA255_DCMD6 (PXA255_DMA_BASE_ADDR + 0x0000026c)
#define PXA255_DDADR7 (PXA255_DMA_BASE_ADDR + 0x00000270)
#define PXA255_DSADR7 (PXA255_DMA_BASE_ADDR + 0x00000274)
#define PXA255_DTADR7 (PXA255_DMA_BASE_ADDR + 0x00000278)
#define PXA255_DCMD7 (PXA255_DMA_BASE_ADDR + 0x0000027c)
#define PXA255_DDADR8 (PXA255_DMA_BASE_ADDR + 0x00000280)
#define PXA255_DSADR8 (PXA255_DMA_BASE_ADDR + 0x00000284)
#define PXA255_DTADR8 (PXA255_DMA_BASE_ADDR + 0x00000288)
#define PXA255_DCMD8 (PXA255_DMA_BASE_ADDR + 0x0000028c)
#define PXA255_DDADR9 (PXA255_DMA_BASE_ADDR + 0x00000290)
#define PXA255_DSADR9 (PXA255_DMA_BASE_ADDR + 0x00000294)
#define PXA255_DTADR9 (PXA255_DMA_BASE_ADDR + 0x00000298)
#define PXA255_DCMD9 (PXA255_DMA_BASE_ADDR + 0x0000029c)
#define PXA255_DDADR10 (PXA255_DMA_BASE_ADDR + 0x000002a0)
#define PXA255_DSADR10 (PXA255_DMA_BASE_ADDR + 0x000002a4)
#define PXA255_DTADR10 (PXA255_DMA_BASE_ADDR + 0x000002a8)
#define PXA255_DCMD10 (PXA255_DMA_BASE_ADDR + 0x000002ac)
#define PXA255_DDADR11 (PXA255_DMA_BASE_ADDR + 0x000002b0)
#define PXA255_DSADR11 (PXA255_DMA_BASE_ADDR + 0x000002b4)
#define PXA255_DTADR11 (PXA255_DMA_BASE_ADDR + 0x000002b8)
#define PXA255_DCMD11 (PXA255_DMA_BASE_ADDR + 0x000002bc)
#define PXA255_DDADR12 (PXA255_DMA_BASE_ADDR + 0x000002c0)
#define PXA255_DSADR12 (PXA255_DMA_BASE_ADDR + 0x000002c4)
#define PXA255_DTADR12 (PXA255_DMA_BASE_ADDR + 0x000002c8)
#define PXA255_DCMD12 (PXA255_DMA_BASE_ADDR + 0x000002cc)
#define PXA255_DDADR13 (PXA255_DMA_BASE_ADDR + 0x000002d0)
#define PXA255_DSADR13 (PXA255_DMA_BASE_ADDR + 0x000002d4)
#define PXA255_DTADR13 (PXA255_DMA_BASE_ADDR + 0x000002d8)
#define PXA255_DCMD13 (PXA255_DMA_BASE_ADDR + 0x000002dc)
#define PXA255_DDADR14 (PXA255_DMA_BASE_ADDR + 0x000002e0)
#define PXA255_DSADR14 (PXA255_DMA_BASE_ADDR + 0x000002e4)
#define PXA255_DTADR14 (PXA255_DMA_BASE_ADDR + 0x000002e8)
#define PXA255_DCMD14 (PXA255_DMA_BASE_ADDR + 0x000002ec)
#define PXA255_DDADR15 (PXA255_DMA_BASE_ADDR + 0x000002f0)
#define PXA255_DDADR_STOP (0x00000001)
#define PXA255_DSADR15 (PXA255_DMA_BASE_ADDR + 0x000002f4)
#define PXA255_DTADR15 (PXA255_DMA_BASE_ADDR + 0x000002f8)
#define PXA255_DCMD15 (PXA255_DMA_BASE_ADDR + 0x000002fc)
#define PXA255_DCMD_INCSRCADDR (0x80000000)
#define PXA255_DCMD_INCTRGADDR (0x40000000)
#define PXA255_DCMD_FLOWSRC (0x20000000)
#define PXA255_DCMD_FLOWTRG (0x10000000)
#define PXA255_DCMD_STARTIRQEN (0x00400000)
#define PXA255_DCMD_ENDIRQEN (0x00200000)
#define PXA255_DCMD_ENDIAN (0x00040000)
#define PXA255_DCMD_SIZE_SHIFT (16)
#define PXA255_DCMD_SIZE_MASK (0x00000003)
#define PXA255_DCMD_SIZE_0 (0x00000000)
#define PXA255_DCMD_SIZE_8 (0x00000001)
#define PXA255_DCMD_SIZE_16 (0x00000002)
#define PXA255_DCMD_SIZE_32 (0x00000003)
#define PXA255_DCMD_WIDTH (0x0000c000)
#define PXA255_DCMD_WIDTH_0 (0x00000000)
#define PXA255_DCMD_WIDTH_1 (0x00004000)
#define PXA255_DCMD_WIDTH_2 (0x00008000)
#define PXA255_DCMD_WIDTH_4 (0x0000c000)
/*
PXA255 Inter-Integrated-Circuit Sound (I2S) Controller
pg. 489 to 504, PXA255 Processor Developers Manual [278693-002].pdf
*/
#define PXA255_I2S_BASE_ADDR (0x40400000)
#define PXA255_SACR0 (PXA255_I2S_BASE_ADDR + 0x00000000)
#define PXA255_SACR0_ENB (0x00000001) // Enable I2S function: 0 = Disable, 1 = Enable
#define PXA255_SACR0_BCKD (0x00000004) // Input/Output direction of BITCLK: 0 = Input, 1 = Output
#define PXA255_SACR0_RST (0x00000008) // Reset FIFO Logic and all registers: 0 = Not Reset, 1 = Reset is active
#define PXA255_SACR0_EFWR (0x00000010) // Special-purpose FIFO Write/Read Enable: 0 = Disable, 1 = Enable
#define PXA255_SACR0_STRF (0x00000020) // Select Transmit or Receive FIFO for EFWR-based special-purpose function: 0 = Xmit FIFO, 1 = Recv FIFO
#define PXA255_SACR0_TFTH (0x00000f00) // Transmit FIFO interrupt or DMA threshold
#define PXA255_SACR0_TFTH_S (8)
#define PXA255_SACR0_RFTH (0x0000f000) // Receive FIFO interrupt or DMA threshold
#define PXA255_SACR0_RFTH_S (12)
#define PXA255_SACR1 (PXA255_I2S_BASE_ADDR + 0x00000004)
#define PXA255_SACR1_AMSL (0x00000001) // Alternate Mode: 0 = I2S Operation Mode, 1 = MSB-Justified Operation Mode
#define PXA255_SACR1_DREC (0x00000008) // Disable Recording: 0 = Recording Function is enabled, 1 = Recording Function is disabled
#define PXA255_SACR1_DRPL (0x00000010) // Disable Replaying: 0 = Replaying Function is enabled, 1 = Recording Function is disabled
#define PXA255_SACR1_ENLBF (0x00000020) // Enable I2S/MSB Interface Loopback
#define PXA255_SASR0 (PXA255_I2S_BASE_ADDR + 0x0000000c)
#define PXA255_SASR0_TNF (0x00000001)
#define PXA255_SASR0_RNE (0x00000002)
#define PXA255_SASR0_BSY (0x00000004)
#define PXA255_SASR0_TFS (0x00000008)
#define PXA255_SASR0_RFS (0x00000010)
#define PXA255_SASR0_TUR (0x00000020)
#define PXA255_SASR0_ROR (0x00000040)
#define PXA255_SASR0_TFL (0x00000f00)
#define PXA255_SASR0_RFL (0x0000f000)
#define PXA255_SAIMR (PXA255_I2S_BASE_ADDR + 0x00000014)
#define PXA255_SAIMR_TFS (0x00000008)
#define PXA255_SAIMR_RFS (0x00000010)
#define PXA255_SAIMR_TUR (0x00000020)
#define PXA255_SAIMR_ROR (0x00000040)
#define PXA255_SAICR (PXA255_I2S_BASE_ADDR + 0x00000018)
#define PXA255_SAICR_TUR (0x00000020)
#define PXA255_SAICR_ROR (0x00000040)
#define PXA255_SADIV (PXA255_I2S_BASE_ADDR + 0x00000060)
#define PXA255_SADR (PXA255_I2S_BASE_ADDR + 0x00000080)
/*
PXA255 Real-Time Clock
pg. 132 to 138, PXA255 Processor Developers Manual [278693-002].pdf
*/
#define PXA255_RTC_BASE_ADDR (0x40900000)
#define PXA255_RCNR (PXA255_RTC_BASE_ADDR + 0x00000000)
#define PXA255_RTAR (PXA255_RTC_BASE_ADDR + 0x00000004)
#define PXA255_RTSR (PXA255_RTC_BASE_ADDR + 0x00000008)
#define PXA255_RTTR (PXA255_RTC_BASE_ADDR + 0x0000000c)
/*
PXA255 OS Timer register
pg. 138 to 142, PXA255 Processor Developers Manual [278693-002].pdf
*/
#define PXA255_OSTMR_BASE_ADDR (0x40a00000)
#define PXA255_OSMR0 (PXA255_OSTMR_BASE_ADDR + 0x00000000)
#define PXA255_OSMR1 (PXA255_OSTMR_BASE_ADDR + 0x00000004)
#define PXA255_OSMR2 (PXA255_OSTMR_BASE_ADDR + 0x00000008)
#define PXA255_OSMR3 (PXA255_OSTMR_BASE_ADDR + 0x0000000c)
#define PXA255_OSCR (PXA255_OSTMR_BASE_ADDR + 0x00000010)
#define PXA255_OSSR (PXA255_OSTMR_BASE_ADDR + 0x00000014)
#define PXA255_OSSR_M0 (0x00000001)
#define PXA255_OSSR_M1 (0x00000002)
#define PXA255_OSSR_M2 (0x00000004)
#define PXA255_OSSR_M3 (0x00000008)
#define PXA255_OWER (PXA255_OSTMR_BASE_ADDR + 0x00000018)
#define PXA255_OIER (PXA255_OSTMR_BASE_ADDR + 0x0000001c)
#define PXA255_OIER_E0 (0x00000001)
#define PXA255_OIER_E1 (0x00000002)
#define PXA255_OIER_E2 (0x00000004)
#define PXA255_OIER_E3 (0x00000008)
/*
PXA255 Interrupt registers
pg. 124 to 132, PXA255 Processor Developers Manual [278693-002].pdf
*/
#define PXA255_INTC_BASE_ADDR (0x40d00000)
#define PXA255_ICIP (PXA255_INTC_BASE_ADDR + 0x00000000)
#define PXA255_ICMR (PXA255_INTC_BASE_ADDR + 0x00000004)
#define PXA255_ICLR (PXA255_INTC_BASE_ADDR + 0x00000008)
#define PXA255_ICFP (PXA255_INTC_BASE_ADDR + 0x0000000c)
#define PXA255_ICPR (PXA255_INTC_BASE_ADDR + 0x00000010)
#define PXA255_ICCR (PXA255_INTC_BASE_ADDR + 0x00000014)
#define PXA255_INT_HUART (1 << 7)
#define PXA255_INT_GPIO0 (1 << 8)
#define PXA255_INT_GPIO1 (1 << 9)
#define PXA255_INT_GPIO84_2 (1 << 10)
#define PXA255_INT_USB (1 << 11)
#define PXA255_INT_PMU (1 << 12)
#define PXA255_INT_I2S (1 << 13)
#define PXA255_INT_AC97 (1 << 14)
#define PXA255_INT_NETWORK (1 << 16)
#define PXA255_INT_LCD (1 << 17)
#define PXA255_INT_I2C (1 << 18)
#define PXA255_INT_ICP (1 << 19)
#define PXA255_INT_STUART (1 << 20)
#define PXA255_INT_BTUART (1 << 21)
#define PXA255_INT_FFUART (1 << 22)
#define PXA255_INT_MMC (1 << 23)
#define PXA255_INT_SSP (1 << 24)
#define PXA255_INT_DMA (1 << 25)
#define PXA255_INT_OSTIMER0 (1 << 26)
#define PXA255_INT_OSTIMER1 (1 << 27)
#define PXA255_INT_OSTIMER2 (1 << 28)
#define PXA255_INT_OSTIMER3 (1 << 29)
#define PXA255_INT_RTC_HZ (1 << 30)
#define PXA255_INT_RTC_ALARM (1 << 31)
/*
PXA255 General-Purpose I/O registers
pg. 105 to 124, PXA255 Processor Developers Manual [278693-002].pdf
*/
#define PXA255_GPIO_BASE_ADDR (0x40e00000)
#define PXA255_GPLR0 (PXA255_GPIO_BASE_ADDR + 0x00000000)
#define PXA255_GPLR1 (PXA255_GPIO_BASE_ADDR + 0x00000004)
#define PXA255_GPLR2 (PXA255_GPIO_BASE_ADDR + 0x00000008)
#define PXA255_GPDR0 (PXA255_GPIO_BASE_ADDR + 0x0000000c)
#define PXA255_GPDR1 (PXA255_GPIO_BASE_ADDR + 0x00000010)
#define PXA255_GPDR2 (PXA255_GPIO_BASE_ADDR + 0x00000014)
#define PXA255_GPSR0 (PXA255_GPIO_BASE_ADDR + 0x00000018)
#define PXA255_GPSR1 (PXA255_GPIO_BASE_ADDR + 0x0000001c)
#define PXA255_GPSR2 (PXA255_GPIO_BASE_ADDR + 0x00000020)
#define PXA255_GPCR0 (PXA255_GPIO_BASE_ADDR + 0x00000024)
#define PXA255_GPCR1 (PXA255_GPIO_BASE_ADDR + 0x00000028)
#define PXA255_GPCR2 (PXA255_GPIO_BASE_ADDR + 0x0000002c)
#define PXA255_GRER0 (PXA255_GPIO_BASE_ADDR + 0x00000030)
#define PXA255_GRER1 (PXA255_GPIO_BASE_ADDR + 0x00000034)
#define PXA255_GRER2 (PXA255_GPIO_BASE_ADDR + 0x00000038)
#define PXA255_GFER0 (PXA255_GPIO_BASE_ADDR + 0x0000003c)
#define PXA255_GFER1 (PXA255_GPIO_BASE_ADDR + 0x00000040)
#define PXA255_GFER2 (PXA255_GPIO_BASE_ADDR + 0x00000044)
#define PXA255_GEDR0 (PXA255_GPIO_BASE_ADDR + 0x00000048)
#define PXA255_GEDR1 (PXA255_GPIO_BASE_ADDR + 0x0000004c)
#define PXA255_GEDR2 (PXA255_GPIO_BASE_ADDR + 0x00000050)
#define PXA255_GAFR0_L (PXA255_GPIO_BASE_ADDR + 0x00000054)
#define PXA255_GAFR0_U (PXA255_GPIO_BASE_ADDR + 0x00000058)
#define PXA255_GAFR1_L (PXA255_GPIO_BASE_ADDR + 0x0000005c)
#define PXA255_GAFR1_U (PXA255_GPIO_BASE_ADDR + 0x00000060)
#define PXA255_GAFR2_L (PXA255_GPIO_BASE_ADDR + 0x00000064)
#define PXA255_GAFR2_U (PXA255_GPIO_BASE_ADDR + 0x00000068)
/*
PXA255 LCD Controller
pg. 265 to 310, PXA255 Processor Developers Manual [278693-002].pdf
*/
#define PXA255_LCD_BASE_ADDR (0x44000000)
#define PXA255_LCCR0 (PXA255_LCD_BASE_ADDR + 0x00000000)
#define PXA255_LCCR0_OUM (0x00200000)
#define PXA255_LCCR0_BM (0x00100000)
#define PXA255_LCCR0_PDD (0x000ff000)
#define PXA255_LCCR0_QDM (0x00000800)
#define PXA255_LCCR0_DIS (0x00000400)
#define PXA255_LCCR0_DPD (0x00000200)
#define PXA255_LCCR0_PAS (0x00000080)
#define PXA255_LCCR0_EFM (0x00000040)
#define PXA255_LCCR0_IUM (0x00000020)
#define PXA255_LCCR0_SFM (0x00000010)
#define PXA255_LCCR0_LDM (0x00000008)
#define PXA255_LCCR0_SDS (0x00000004)
#define PXA255_LCCR0_CMS (0x00000002)
#define PXA255_LCCR0_ENB (0x00000001)
#define PXA255_LCCR1 (PXA255_LCD_BASE_ADDR + 0x00000004)
#define PXA255_LCCR1_PPL (0x000003ff)
#define PXA255_LCCR2 (PXA255_LCD_BASE_ADDR + 0x00000008)
#define PXA255_LCCR2_LPP (0x000003ff)
#define PXA255_LCCR3 (PXA255_LCD_BASE_ADDR + 0x0000000c)
#define PXA255_FBR0 (PXA255_LCD_BASE_ADDR + 0x00000020)
#define PXA255_FBR_BAR (0x00000001)
#define PXA255_FBR_BINT (0x00000003)
#define PXA255_FBR1 (PXA255_LCD_BASE_ADDR + 0x00000024)
#define PXA255_LCSR (PXA255_LCD_BASE_ADDR + 0x00000038)
#define PXA255_LCSR_LDD (0x00000001)
#define PXA255_LCSR_SOF (0x00000002)
#define PXA255_LCSR_BER (0x00000004)
#define PXA255_LCSR_ABC (0x00000008)
#define PXA255_LCSR_IUL (0x00000010)
#define PXA255_LCSR_IUU (0x00000020)
#define PXA255_LCSR_OU (0x00000040)
#define PXA255_LCSR_QD (0x00000080)
#define PXA255_LCSR_EOF (0x00000100)
#define PXA255_LCSR_BS (0x00000200)
#define PXA255_LCSR_SINT (0x00000400)
#define PXA255_LIIDR (PXA255_LCD_BASE_ADDR + 0x0000003c)
#define PXA255_TRGBR (PXA255_LCD_BASE_ADDR + 0x00000040)
#define PXA255_TCR (PXA255_LCD_BASE_ADDR + 0x00000044)
#define PXA255_FDADR0 (PXA255_LCD_BASE_ADDR + 0x00000200)
#define PXA255_FSADR0 (PXA255_LCD_BASE_ADDR + 0x00000204)
#define PXA255_FIDR0 (PXA255_LCD_BASE_ADDR + 0x00000208)
#define PXA255_LDCMD0 (PXA255_LCD_BASE_ADDR + 0x0000020c)
#define PXA255_LDCMD_EOFINT (0x00200000)
#define PXA255_LDCMD_SOFINT (0x00400000)
#define PXA255_LDCMD_PAL (0x04000000)
#define PXA255_FDADR1 (PXA255_LCD_BASE_ADDR + 0x00000210)
#define PXA255_FSADR1 (PXA255_LCD_BASE_ADDR + 0x00000214)
#define PXA255_FIDR1 (PXA255_LCD_BASE_ADDR + 0x00000218)
#define PXA255_LDCMD1 (PXA255_LCD_BASE_ADDR + 0x0000021c)
/*
PXA255 Power controller
pg. 85 to 96, PXA255 Processor Developers Manual [278693-002].pdf
*/
#define PXA255_POWER_BASE_ADDR (0x40f00000)
#define PXA255_PMCR (PXA255_POWER_BASE_ADDR + 0x00000000)
#define PXA255_PSSR (PXA255_POWER_BASE_ADDR + 0x00000004)
#define PXA255_PSPR (PXA255_POWER_BASE_ADDR + 0x00000008)
#define PXA255_PWER (PXA255_POWER_BASE_ADDR + 0x0000000c)
#define PXA255_PRER (PXA255_POWER_BASE_ADDR + 0x00000010)
#define PXA255_PFER (PXA255_POWER_BASE_ADDR + 0x00000014)
#define PXA255_PEDR (PXA255_POWER_BASE_ADDR + 0x00000018)
#define PXA255_PCFR (PXA255_POWER_BASE_ADDR + 0x0000001c)
#define PXA255_PGSR0 (PXA255_POWER_BASE_ADDR + 0x00000020)
#define PXA255_PGSR1 (PXA255_POWER_BASE_ADDR + 0x00000024)
#define PXA255_PGSR2 (PXA255_POWER_BASE_ADDR + 0x00000028)
#define PXA255_RCSR (PXA255_POWER_BASE_ADDR + 0x00000030)
#define PXA255_PMFW (PXA255_POWER_BASE_ADDR + 0x00000034)
/*
PXA255 Clock controller
pg. 96 to 100, PXA255 Processor Developers Manual [278693-002].pdf
*/
#define PXA255_CLOCKS_BASE_ADDR (0x41300000)
#define PXA255_CCCR (PXA255_CLOCKS_BASE_ADDR + 0x00000000)
#define PXA255_CKEN (PXA255_CLOCKS_BASE_ADDR + 0x00000004)
#define PXA255_OSCC (PXA255_CLOCKS_BASE_ADDR + 0x00000008)
#endif // MAME_MACHINE_PXA255DEFS

118
src/mame/misc/39in1.cpp
View File

@ -62,6 +62,7 @@ public:
, m_eeprom(*this, "eeprom")
, m_ram(*this, "ram")
, m_mcu_ipt(*this, "MCUIPT")
, m_dsw(*this, "DSW")
{ }
void _39in1(machine_config &config);
@ -83,49 +84,50 @@ public:
void init_plutus();
void init_pokrwild();
DECLARE_INPUT_CHANGED_MEMBER(set_flip_dip);
DECLARE_INPUT_CHANGED_MEMBER(set_res_dip);
DECLARE_INPUT_CHANGED_MEMBER(set_hiscore_dip);
protected:
virtual void machine_reset() override;
private:
uint32_t m_seed;
uint32_t m_magic;
uint32_t m_state;
uint32_t m_mcu_ipt_pc;
u32 m_seed;
u32 m_magic;
u32 m_state;
u32 m_mcu_ipt_pc;
required_device<cpu_device> m_maincpu;
required_device<pxa255_periphs_device> m_pxa_periphs;
required_device<eeprom_serial_93cxx_device> m_eeprom;
required_shared_ptr<uint32_t> m_ram;
required_device<eeprom_serial_93c66_16bit_device> m_eeprom;
required_shared_ptr<u32> m_ram;
required_ioport m_mcu_ipt;
required_ioport m_dsw;
uint32_t eeprom_r();
void eeprom_w(uint32_t data, uint32_t mem_mask = ~0);
uint32_t _39in1_cpld_r(offs_t offset);
void _39in1_cpld_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
uint32_t _39in1_prot_cheater_r();
u32 cpld_r(offs_t offset);
void cpld_w(offs_t offset, u32 data, u32 mem_mask = ~0);
u32 prot_cheater_r();
void _39in1_map(address_map &map);
void base_map(address_map &map);
void decrypt(uint8_t xor00, uint8_t xor02, uint8_t xor04, uint8_t xor08, uint8_t xor10, uint8_t xor20, uint8_t xor40, uint8_t xor80, uint8_t bit7, uint8_t bit6, uint8_t bit5, uint8_t bit4, uint8_t bit3, uint8_t bit2, uint8_t bit1, uint8_t bit0);
void further_decrypt(uint8_t xor400, uint8_t xor800, uint8_t xor1000, uint8_t xor2000, uint8_t xor4000, uint8_t xor8000);
void decrypt(u8 xor00, u8 xor02, u8 xor04, u8 xor08, u8 xor10, u8 xor20, u8 xor40, u8 xor80, u8 bit7, u8 bit6, u8 bit5, u8 bit4, u8 bit3, u8 bit2, u8 bit1, u8 bit0);
void further_decrypt(u8 xor400, u8 xor800, u8 xor1000, u8 xor2000, u8 xor4000, u8 xor8000);
};
uint32_t _39in1_state::eeprom_r()
void _39in1_state::machine_reset()
{
return (m_eeprom->do_read() << 5) | (1 << 1); // Must be on. Probably a DIP switch.
m_pxa_periphs->gpio_in<1>(1);
const u32 dsw = m_dsw->read();
m_pxa_periphs->gpio_in<53>(BIT(dsw, 0));
m_pxa_periphs->gpio_in<54>(BIT(dsw, 1));
m_pxa_periphs->gpio_in<56>(BIT(dsw, 2));
m_eeprom->di_write(ASSERT_LINE);
}
void _39in1_state::eeprom_w(uint32_t data, uint32_t mem_mask)
{
if (BIT(mem_mask, 2))
m_eeprom->cs_write(ASSERT_LINE);
if (BIT(mem_mask, 3))
m_eeprom->clk_write(BIT(data, 3) ? ASSERT_LINE : CLEAR_LINE);
if (BIT(mem_mask, 4))
m_eeprom->di_write(BIT(data, 4));
}
uint32_t _39in1_state::_39in1_cpld_r(offs_t offset)
u32 _39in1_state::cpld_r(offs_t offset)
{
// if (m_maincpu->pc() != m_mcu_ipt_pc) printf("CPLD read @ %x (PC %x state %d)\n", offset, m_maincpu->pc(), m_state);
@ -160,8 +162,8 @@ uint32_t _39in1_state::_39in1_cpld_r(offs_t offset)
}
else if (m_state == 2) // 29c0: 53 ac 0c 2b a2 07 e6 be 31
{
uint32_t seed = m_seed;
uint32_t magic = m_magic;
u32 seed = m_seed;
u32 magic = m_magic;
magic = ( (((~(seed >> 16)) ^ (magic >> 1)) & 0x01) |
(((~((seed >> 19) << 1)) ^ ((magic >> 5) << 1)) & 0x02) |
@ -180,7 +182,7 @@ uint32_t _39in1_state::_39in1_cpld_r(offs_t offset)
return 0;
}
void _39in1_state::_39in1_cpld_w(offs_t offset, uint32_t data, uint32_t mem_mask)
void _39in1_state::cpld_w(offs_t offset, u32 data, u32 mem_mask)
{
if (mem_mask == 0xffff)
{
@ -207,7 +209,7 @@ void _39in1_state::_39in1_cpld_w(offs_t offset, uint32_t data, uint32_t mem_mask
#endif
}
uint32_t _39in1_state::_39in1_prot_cheater_r()
u32 _39in1_state::prot_cheater_r()
{
return 0x37;
}
@ -216,12 +218,7 @@ void _39in1_state::base_map(address_map &map)
{
map(0x00000000, 0x0007ffff).rom();
map(0x00400000, 0x007fffff).rom().region("data", 0);
map(0x40000000, 0x400002ff).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::dma_r), FUNC(pxa255_periphs_device::dma_w));
map(0x40400000, 0x40400083).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::i2s_r), FUNC(pxa255_periphs_device::i2s_w));
map(0x40a00000, 0x40a0001f).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::ostimer_r), FUNC(pxa255_periphs_device::ostimer_w));
map(0x40d00000, 0x40d00017).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::intc_r), FUNC(pxa255_periphs_device::intc_w));
map(0x40e00000, 0x40e0006b).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::gpio_r), FUNC(pxa255_periphs_device::gpio_w));
map(0x44000000, 0x4400021f).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::lcd_r), FUNC(pxa255_periphs_device::lcd_w));
map(0x40000000, 0x47ffffff).m(m_pxa_periphs, FUNC(pxa255_periphs_device::map));
map(0xa0000000, 0xa07fffff).ram().share("ram");
}
@ -229,8 +226,8 @@ void _39in1_state::_39in1_map(address_map &map)
{
base_map(map);
map(0x04000000, 0x047fffff).rw(FUNC(_39in1_state::_39in1_cpld_r), FUNC(_39in1_state::_39in1_cpld_w));
map(0xa0151648, 0xa015164b).r(FUNC(_39in1_state::_39in1_prot_cheater_r));
map(0x04000000, 0x047fffff).rw(FUNC(_39in1_state::cpld_r), FUNC(_39in1_state::cpld_w));
map(0xa0151648, 0xa015164b).r(FUNC(_39in1_state::prot_cheater_r));
}
static INPUT_PORTS_START( 39in1 )
@ -271,23 +268,35 @@ static INPUT_PORTS_START( 39in1 )
// The following dips apply to 39in1 and 48in1. 60in1 is the same but the last unused dipsw#4 is test mode off/on.
PORT_START("DSW") // 1x 4-position DIP switch labelled SW3
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW3:1")
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW3:1") PORT_CHANGED_MEMBER(DEVICE_SELF, _39in1_state, set_flip_dip, 0)
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x02, 0x00, "Display Mode" ) PORT_DIPLOCATION("SW3:2")
PORT_DIPNAME( 0x02, 0x00, "Display Mode" ) PORT_DIPLOCATION("SW3:2") PORT_CHANGED_MEMBER(DEVICE_SELF, _39in1_state, set_res_dip, 0)
PORT_DIPSETTING( 0x02, "VGA 31.5kHz" )
PORT_DIPSETTING( 0x00, "CGA 15.75kHz" )
PORT_DIPNAME( 0x04, 0x04, "High Score Saver" ) PORT_DIPLOCATION("SW3:3")
PORT_DIPNAME( 0x04, 0x04, "High Score Saver" ) PORT_DIPLOCATION("SW3:3") PORT_CHANGED_MEMBER(DEVICE_SELF, _39in1_state, set_hiscore_dip, 0)
PORT_DIPSETTING( 0x04, "Disabled" )
PORT_DIPSETTING( 0x00, "Enabled" )
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unused ) ) PORT_DIPLOCATION("SW3:4")
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
INPUT_PORTS_END
void _39in1_state::decrypt(uint8_t xor00, uint8_t xor02, uint8_t xor04, uint8_t xor08, uint8_t xor10, uint8_t xor20, uint8_t xor40, uint8_t xor80, uint8_t bit7, uint8_t bit6, uint8_t bit5, uint8_t bit4, uint8_t bit3, uint8_t bit2, uint8_t bit1, uint8_t bit0)
INPUT_CHANGED_MEMBER(_39in1_state::set_flip_dip)
{
uint8_t *rom = memregion("maincpu")->base();
m_pxa_periphs->gpio_in<53>(BIT(m_dsw->read(), 0));
}
INPUT_CHANGED_MEMBER(_39in1_state::set_res_dip)
{
m_pxa_periphs->gpio_in<54>(BIT(m_dsw->read(), 1));
}
INPUT_CHANGED_MEMBER(_39in1_state::set_hiscore_dip)
{
m_pxa_periphs->gpio_in<56>(BIT(m_dsw->read(), 2));
}
void _39in1_state::decrypt(u8 xor00, u8 xor02, u8 xor04, u8 xor08, u8 xor10, u8 xor20, u8 xor40, u8 xor80, u8 bit7, u8 bit6, u8 bit5, u8 bit4, u8 bit3, u8 bit2, u8 bit1, u8 bit0)
{
u8 *rom = memregion("maincpu")->base();
for (int i = 0; i < 0x80000; i += 2)
{
@ -310,9 +319,9 @@ void _39in1_state::decrypt(uint8_t xor00, uint8_t xor02, uint8_t xor04, uint8_t
}
}
void _39in1_state::further_decrypt(uint8_t xor400, uint8_t xor800, uint8_t xor1000, uint8_t xor2000, uint8_t xor4000, uint8_t xor8000) // later versions have more conditional XORs
void _39in1_state::further_decrypt(u8 xor400, u8 xor800, u8 xor1000, u8 xor2000, u8 xor4000, u8 xor8000) // later versions have more conditional XORs
{
uint8_t *rom = memregion("maincpu")->base();
u8 *rom = memregion("maincpu")->base();
for (int i = 0; i < 0x80000; i += 2)
{
@ -353,12 +362,13 @@ void _39in1_state::base(machine_config &config)
PXA255(config, m_maincpu, 200'000'000);
m_maincpu->set_addrmap(AS_PROGRAM, &_39in1_state::base_map);
EEPROM_93C66_16BIT(config, "eeprom");
EEPROM_93C66_16BIT(config, m_eeprom);
m_eeprom->do_callback().set(m_pxa_periphs, FUNC(pxa255_periphs_device::gpio_in<5>));
PXA255_PERIPHERALS(config, m_pxa_periphs, 200'000'000, m_maincpu);
m_pxa_periphs->gpio0_write().set(FUNC(_39in1_state::eeprom_w));
m_pxa_periphs->gpio0_read().set(FUNC(_39in1_state::eeprom_r));
m_pxa_periphs->gpio1_read().set_ioport("DSW").lshift(21);
m_pxa_periphs->gpio_out<4>().set(m_eeprom, FUNC(eeprom_serial_93c66_16bit_device::di_write));
m_pxa_periphs->gpio_out<2>().set(m_eeprom, FUNC(eeprom_serial_93c66_16bit_device::cs_write));
m_pxa_periphs->gpio_out<3>().set(m_eeprom, FUNC(eeprom_serial_93c66_16bit_device::clk_write));
}
void _39in1_state::_39in1(machine_config &config)

12
src/mame/sharp/zaurus.cpp
View File

@ -1505,15 +1505,7 @@ void zaurus_sa_state::main_map(address_map &map)
void zaurus_pxa_state::main_map(address_map &map)
{
map(0x00000000, 0x001fffff).rom().region("firmware", 0);
map(0x40000000, 0x400002ff).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::dma_r), FUNC(pxa255_periphs_device::dma_w));
map(0x40400000, 0x40400083).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::i2s_r), FUNC(pxa255_periphs_device::i2s_w));
map(0x40900000, 0x4090000f).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::rtc_r), FUNC(pxa255_periphs_device::rtc_w));
map(0x40a00000, 0x40a0001f).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::ostimer_r), FUNC(pxa255_periphs_device::ostimer_w));
map(0x40d00000, 0x40d00017).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::intc_r), FUNC(pxa255_periphs_device::intc_w));
map(0x40e00000, 0x40e0006b).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::gpio_r), FUNC(pxa255_periphs_device::gpio_w));
map(0x40f00000, 0x40f00037).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::power_r), FUNC(pxa255_periphs_device::power_w));
map(0x41300000, 0x4130000b).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::clocks_r), FUNC(pxa255_periphs_device::clocks_w));
map(0x44000000, 0x4400021f).rw(m_pxa_periphs, FUNC(pxa255_periphs_device::lcd_r), FUNC(pxa255_periphs_device::lcd_w));
map(0x40000000, 0x47ffffff).m(m_pxa_periphs, FUNC(pxa255_periphs_device::map));
map(0xa0000000, 0xa07fffff).ram().share("ram");
}
@ -1527,7 +1519,7 @@ void zaurus_sa_state::device_reset_after_children()
INPUT_CHANGED_MEMBER( zaurus_pxa_state::system_start )
{
m_pxa_periphs->gpio_bit_w(10, m_power->read());
m_pxa_periphs->gpio_in<10>(BIT(m_power->read(), 0));
}
static INPUT_PORTS_START( zaurus_sa )