mirror of
https://github.com/holub/mame
synced 2025-05-18 19:49:35 +03:00
Added HD61700 CPU core used for emulate Casio PB-1000/PB-2000c in MESS [Sandro Ronco]
This commit is contained in:
Miodrag Milanovic
parent
e884b694b2
commit
0cc1b379e5
3
.gitattributes
vendored
3
.gitattributes
vendored
@ -142,6 +142,9 @@ src/emu/cpu/hcd62121/hcd62121.c svneol=native#text/plain
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src/emu/cpu/hcd62121/hcd62121.h svneol=native#text/plain
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src/emu/cpu/hcd62121/hcd62121.h svneol=native#text/plain
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src/emu/cpu/hcd62121/hcd62121_ops.h svneol=native#text/plain
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src/emu/cpu/hcd62121/hcd62121_ops.h svneol=native#text/plain
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src/emu/cpu/hcd62121/hcd62121d.c svneol=native#text/plain
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src/emu/cpu/hcd62121/hcd62121d.c svneol=native#text/plain
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src/emu/cpu/hd61700/hd61700.c svneol=native#text/plain
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src/emu/cpu/hd61700/hd61700.h svneol=native#text/plain
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src/emu/cpu/hd61700/hd61700d.c svneol=native#text/plain
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src/emu/cpu/hd6309/6309dasm.c svneol=native#text/plain
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src/emu/cpu/hd6309/6309dasm.c svneol=native#text/plain
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src/emu/cpu/hd6309/6309ops.c svneol=native#text/plain
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src/emu/cpu/hd6309/6309ops.c svneol=native#text/plain
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src/emu/cpu/hd6309/6309tbl.c svneol=native#text/plain
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src/emu/cpu/hd6309/6309tbl.c svneol=native#text/plain
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@ -1784,3 +1784,16 @@ endif
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$(CPUOBJ)/pps4/pps4.o: $(CPUSRC)/pps4/pps4.c \
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$(CPUOBJ)/pps4/pps4.o: $(CPUSRC)/pps4/pps4.c \
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$(CPUSRC)/pps4/pps4.h
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$(CPUSRC)/pps4/pps4.h
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#-------------------------------------------------
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# Hitachi HD61700
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#-------------------------------------------------
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ifneq ($(filter HD61700,$(CPUS)),)
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OBJDIRS += $(CPUOBJ)/hd61700
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CPUOBJS += $(CPUOBJ)/hd61700/hd61700.o
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DASMOBJS += $(CPUOBJ)/hd61700/hd61700d.o
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endif
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$(CPUOBJ)/hd61700/hd61700.o: $(CPUSRC)/hd61700/hd61700.c \
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$(CPUSRC)/hd61700/hd61700.h
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3062
src/emu/cpu/hd61700/hd61700.c
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3062
src/emu/cpu/hd61700/hd61700.c
Normal file
File diff suppressed because it is too large
Load Diff
192
src/emu/cpu/hd61700/hd61700.h
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192
src/emu/cpu/hd61700/hd61700.h
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@ -0,0 +1,192 @@
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/**********************************************************************
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Hitachi HD61700
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**********************************************************************/
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#pragma once
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#ifndef __HD61700_H__
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#define __HD61700_H__
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//**************************************************************************
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// INTERFACE CONFIGURATION MACROS
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//**************************************************************************
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#define MCFG_HD61700_CONFIG(_config) \
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hd61700_cpu_device_config::static_set_config(device, _config); \
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//**************************************************************************
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// DEVICE TYPE DEFINITION
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//**************************************************************************
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extern const device_type HD61700;
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//**************************************************************************
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// DEFINITIONS
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//**************************************************************************
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// class definition
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class hd61700_cpu_device;
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class hd61700_cpu_device_config;
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// cpu port callbacks types
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typedef void (*hd61700_lcd_control_func)(hd61700_cpu_device &device, UINT8 data);
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typedef UINT8 (*hd61700_lcd_data_r_func)(hd61700_cpu_device &device);
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typedef void (*hd61700_lcd_data_w_func)(hd61700_cpu_device &device, UINT8 data);
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typedef UINT16 (*hd61700_kb_r_func)(hd61700_cpu_device &device);
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typedef void (*hd61700_kb_w_func)(hd61700_cpu_device &device, UINT8 matrix);
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typedef UINT8 (*hd61700_port_r_func)(hd61700_cpu_device &device);
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typedef void (*hd61700_port_w_func)(hd61700_cpu_device &device, UINT8 data);
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// device config
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struct hd61700_config
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{
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hd61700_lcd_control_func m_lcd_control; //lcd control
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hd61700_lcd_data_r_func m_lcd_data_r; //lcd data read
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hd61700_lcd_data_w_func m_lcd_data_w; //lcd data write
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hd61700_kb_r_func m_kb_r; //keyboard matrix read
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hd61700_kb_w_func m_kb_w; //keyboard matrix write
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hd61700_port_r_func m_port_r; //8 bit port read
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hd61700_port_w_func m_port_w; //8 bit port write
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};
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// registers
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enum
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{
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HD61700_PC=1, HD61700_F, HD61700_SX, HD61700_SY, HD61700_SZ, HD61700_PE, HD61700_PD,
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HD61700_IB, HD61700_UA, HD61700_IA, HD61700_IE, HD61700_TM, HD61700_IX,
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HD61700_IY, HD61700_IZ, HD61700_US, HD61700_SS, HD61700_KY, HD61700_MAINREG,
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};
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// input lines
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enum
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{
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HD61700_ON_INT,
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HD61700_TIMER_INT,
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HD61700_INT2,
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HD61700_KEY_INT,
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HD61700_INT1,
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HD61700_SW
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};
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// ======================> hd61700_cpu_device_config
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class hd61700_cpu_device_config : public cpu_device_config,
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public hd61700_config
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{
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friend class hd61700_cpu_device;
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protected:
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// construction/destruction
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hd61700_cpu_device_config(const machine_config &mconfig, device_type _type, const char *_tag, const device_config *_owner, UINT32 _clock);
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public:
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static device_config *static_alloc_device_config(const machine_config &mconfig, const char *tag, const device_config *owner, UINT32 clock);
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virtual device_t *alloc_device(running_machine &machine) const;
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// inline configuration helpers
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static void static_set_config(device_config *device, const hd61700_config &config);
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protected:
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// device_config_execute_interface overrides
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virtual UINT32 execute_min_cycles() const { return 1; }
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virtual UINT32 execute_max_cycles() const { return 52; }
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virtual UINT32 execute_input_lines() const { return 6; }
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// device_config_memory_interface overrides
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virtual const address_space_config *memory_space_config(int spacenum = 0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; }
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// device_config_disasm_interface overrides
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virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
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virtual UINT32 disasm_max_opcode_bytes() const { return 16; }
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// internal state
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address_space_config m_program_config;
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};
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// ======================> hd61700_cpu_device
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class hd61700_cpu_device : public cpu_device
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{
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friend class hd61700_cpu_device_config;
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protected:
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// construction/destruction
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hd61700_cpu_device(running_machine &machine, const hd61700_cpu_device_config &config);
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// device-level overrides
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virtual void device_start();
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virtual void device_reset();
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virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
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// device_execute_interface overrides
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virtual void execute_run();
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virtual void execute_set_input(int inputnum, int state);
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// device_state_interface overrides
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virtual void state_import(const device_state_entry &entry);
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void state_string_export(const device_state_entry &entry, astring &string);
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// device_disasm_interface overrides
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virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
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// interrupts
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bool check_irqs(void);
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// inline helpers
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inline void set_pc(INT32 new_pc);
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inline UINT8 read_op();
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inline UINT8 mem_readbyte(UINT8 segment, UINT16 offset);
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inline void mem_writebyte(UINT8 segment, UINT16 offset, UINT8 data);
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inline UINT32 make_18bit_addr(UINT8 segment, UINT16 offset);
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inline int check_cond( UINT32 op );
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inline void push(UINT16 &offset, UINT8 data);
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inline UINT8 pop(UINT16 &offset);
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inline UINT8 make_logic(UINT8 type, UINT8 d1, UINT8 d2);
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inline void check_optional_jr(UINT8 arg);
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inline UINT8 get_sir_im8(UINT8 arg);
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inline UINT8 get_sir_im8(UINT8 arg, UINT8 arg1);
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inline int get_sign_mreg(UINT8 op1);
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inline int get_sign_im8(UINT8 op1);
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inline int get_im_7(UINT8 data);
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inline UINT16 make_bcd_sub(UINT8 arg1, UINT8 arg2);
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inline UINT16 make_bcd_add(UINT8 arg1, UINT8 arg2);
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protected:
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// internal state
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const hd61700_cpu_device_config &m_cpu_config; // reference to the config
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static const device_timer_id SEC_TIMER = 1;
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emu_timer *m_sec_timer;
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offs_t m_ppc;
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offs_t m_curpc;
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UINT16 m_pc;
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UINT8 m_flags;
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UINT32 m_fetch_addr;
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UINT8 m_regsir[3]; // 5bit register (sx, sy, sz)
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UINT8 m_reg8bit[8]; // 8bit register (pe, pd, ib, ua, ia, ie, tm, tm)
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UINT16 m_reg16bit[8]; // 16bit register (ix, iy, iz, us, ss, ky, ky, ky)
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UINT8 m_regmain[0x20]; // main registers
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UINT8 m_irq_status;
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UINT8 m_state;
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UINT8 prev_ua;
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int m_lines_status[6];
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int m_icount;
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address_space *m_program;
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// flag definitions
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static const int FLAG_Z = 0x80;
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static const int FLAG_C = 0x40;
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static const int FLAG_LZ = 0x20;
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static const int FLAG_UZ = 0x10;
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static const int FLAG_SW = 0x08;
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static const int FLAG_APO = 0x04;
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};
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#endif /* __HD61700_H__ */
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437
src/emu/cpu/hd61700/hd61700d.c
Normal file
437
src/emu/cpu/hd61700/hd61700d.c
Normal file
@ -0,0 +1,437 @@
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#include "emu.h"
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#include "debugger.h"
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#include "hd61700.h"
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#define EXT_ROM (pc > 0x0c00)
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#define INC_POS pos += (type+1)
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#define POS (pos + type)
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static const char *const reg_5b[4] = {"sx", "sy", "sz", "sz"};
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static const char *const reg_8b[8] = {"pe", "pd", "ib", "ua", "ia", "ie", "tm", "tm"};
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static const char *const reg_16b[8] = {"ix", "iy", "iz", "us", "ss", "ky", "ky", "ky"};
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static const char *const jp_cond[8] = {"z", "nc", "lz", "uz", "nz", "c", "nlz"};
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enum
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{
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OP_NULL=0,
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OP_IM16,
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OP_IM16A,
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OP_IM3,
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OP_IM5,
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OP_IM7,
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OP_IM8,
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OP_IM8I,
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OP_IM8_,
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OP_IR_IM3,
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OP_IR_IM8,
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OP_IR_IM8_,
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OP_JX_COND,
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OP_MREG,
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OP_MREG2,
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OP_MR_SIR,
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OP_MR_SIRI,
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OP_REG16,
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OP_REG16_,
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OP_REG8,
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OP_REG8_,
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OP_REGIM8,
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OP_RMSIM3,
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OP_RSIR,
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};
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typedef struct
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{
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const char *str;
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UINT8 arg1;
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UINT8 arg2;
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bool optjr;
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} hd61700_dasm;
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static const hd61700_dasm hd61700_ops[256] =
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{
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// 0x00
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{ "adc", OP_MREG, OP_MR_SIR, 1 }, { "sbc", OP_MREG, OP_MR_SIR, 1 },
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{ "ld", OP_MREG, OP_MR_SIR, 1 }, { "illegal", OP_NULL, OP_NULL, 0 },
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{ "anc", OP_MREG, OP_MR_SIR, 1 }, { "nac", OP_MREG, OP_MR_SIR, 1 },
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{ "orc", OP_MREG, OP_MR_SIR, 1 }, { "xrc", OP_MREG, OP_MR_SIR, 1 },
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{ "ad", OP_MREG, OP_MR_SIR, 1 }, { "sb", OP_MREG, OP_MR_SIR, 1 },
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{ "adb", OP_MREG, OP_MR_SIR, 1 }, { "sbb", OP_MREG, OP_MR_SIR, 1 },
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{ "an", OP_MREG, OP_MR_SIR, 1 }, { "na", OP_MREG, OP_MR_SIR, 1 },
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{ "or", OP_MREG, OP_MR_SIR, 1 }, { "xr", OP_MREG, OP_MR_SIR, 1 },
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// 0x10
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{ "st", OP_MREG, OP_MR_SIRI, 1 }, { "ld", OP_MREG, OP_MR_SIRI,1 },
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{ "stl", OP_MREG2, OP_NULL, 1 }, { "ldl", OP_MREG2, OP_NULL, 1 },
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{ "???", OP_MREG2, OP_NULL, 1 }, { "psr", OP_RSIR, OP_MREG2, 1 },
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{ "pst", OP_REG8, OP_MREG2, 1 }, { "pst", OP_REG8, OP_MREG2, 1 },
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{ "???", OP_MREG2, OP_NULL, 1 }, { "illegal", OP_NULL, OP_NULL, 0 },
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{ "???", OP_MREG2, OP_NULL, 1 }, { "???", OP_MREG2, OP_NULL, 1 },
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{ "???", OP_MREG2, OP_NULL, 1 }, { "gsr", OP_RSIR, OP_MREG2, 1 },
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{ "gst", OP_REG8, OP_MREG2, 1 }, { "gst", OP_REG8, OP_MREG2, 1 },
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// 0x20
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{ "st", OP_MREG, OP_IR_IM8_, 0 }, { "st", OP_MREG, OP_IR_IM8_,0 },
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{ "sti", OP_MREG, OP_IR_IM8_, 0 }, { "sti", OP_MREG, OP_IR_IM8_,0 },
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{ "std", OP_MREG, OP_IR_IM8_, 0 }, { "std", OP_MREG, OP_IR_IM8_,0 },
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{ "phs", OP_MREG2, OP_NULL, 0 }, { "phu", OP_MREG2, OP_NULL, 0 },
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{ "ld", OP_MREG, OP_IR_IM8_, 0 }, { "ld", OP_MREG, OP_IR_IM8_,0 },
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{ "ldi", OP_MREG, OP_IR_IM8_, 0 }, { "ldi", OP_MREG, OP_IR_IM8_,0 },
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{ "ldd", OP_MREG, OP_IR_IM8_, 0 }, { "ldd", OP_MREG, OP_IR_IM8_,0 },
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{ "pps", OP_MREG2, OP_NULL, 0 }, { "ppu", OP_MREG2, OP_NULL, 0 },
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// 0x30
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{ "jp", OP_JX_COND, OP_IM16A, 0 }, { "jp", OP_JX_COND, OP_IM16A, 0 },
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{ "jp", OP_JX_COND, OP_IM16A, 0 }, { "jp", OP_JX_COND, OP_IM16A, 0 },
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{ "jp", OP_JX_COND, OP_IM16A, 0 }, { "jp", OP_JX_COND, OP_IM16A, 0 },
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{ "jp", OP_JX_COND, OP_IM16A, 0 }, { "jp", OP_IM16A, OP_NULL, 0 },
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{ "adc", OP_IR_IM8, OP_MREG2, 0 }, { "adc", OP_IR_IM8, OP_MREG2, 0 },
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||||||
|
{ "sbc", OP_IR_IM8, OP_MREG2, 0 }, { "sbc", OP_IR_IM8, OP_MREG2, 0 },
|
||||||
|
{ "ad", OP_IR_IM8, OP_MREG2, 0 }, { "ad", OP_IR_IM8, OP_MREG2, 0 },
|
||||||
|
{ "sb", OP_IR_IM8, OP_MREG2, 0 }, { "sb", OP_IR_IM8, OP_MREG2, 0 },
|
||||||
|
|
||||||
|
// 0x40
|
||||||
|
{ "adc", OP_MREG2, OP_IM8, 1 }, { "sbc", OP_MREG2, OP_IM8, 1 },
|
||||||
|
{ "ld", OP_MREG2, OP_IM8, 1 }, { "illegal", OP_NULL, OP_NULL, 0 },
|
||||||
|
{ "anc", OP_MREG2, OP_IM8, 1 }, { "nac", OP_MREG2, OP_IM8, 1 },
|
||||||
|
{ "orc", OP_MREG2, OP_IM8, 1 }, { "xrc", OP_MREG2, OP_IM8, 1 },
|
||||||
|
{ "ad", OP_MREG2, OP_IM8, 1 }, { "sb", OP_MREG2, OP_IM8, 1 },
|
||||||
|
{ "adb", OP_MREG2, OP_IM8, 1 }, { "sbb", OP_MREG2, OP_IM8, 1 },
|
||||||
|
{ "an", OP_MREG2, OP_IM8, 1 }, { "na", OP_MREG2, OP_IM8, 1 },
|
||||||
|
{ "or", OP_MREG2, OP_IM8, 1 }, { "xr", OP_MREG2, OP_IM8, 1 },
|
||||||
|
|
||||||
|
// 0x50
|
||||||
|
{ "st", OP_IM8I, OP_MREG2, 0 }, { "st", OP_IM8, OP_MREG2,0 },
|
||||||
|
{ "stl", OP_IM8_, OP_NULL, 0 }, { "illegal", OP_NULL, OP_NULL, 0 },
|
||||||
|
{ "???", OP_IM8_, OP_NULL, 0 }, { "psr", OP_RSIR, OP_IM5, 0 },
|
||||||
|
{ "pst", OP_REG8_, OP_IM8, 0 }, { "pst", OP_REG8_, OP_IM8, 0 },
|
||||||
|
{ "bups", OP_IM8_, OP_NULL, 0 }, { "bdns", OP_IM8_, OP_NULL, 0 },
|
||||||
|
{ "illegal", OP_NULL, OP_NULL, 0 }, { "illegal", OP_NULL, OP_NULL, 0 },
|
||||||
|
{ "sup", OP_IM8_, OP_NULL, 0 }, { "sdn", OP_IM8_, OP_NULL, 0 },
|
||||||
|
{ "illegal", OP_NULL, OP_NULL, 0 }, { "illegal", OP_NULL, OP_NULL, 0 },
|
||||||
|
|
||||||
|
// 0x60
|
||||||
|
{ "st", OP_MREG2, OP_REGIM8, 0 }, { "st", OP_MREG2, OP_REGIM8, 0 },
|
||||||
|
{ "sti", OP_MREG2, OP_REGIM8, 0 }, { "sti", OP_MREG2, OP_REGIM8, 0 },
|
||||||
|
{ "std", OP_MREG2, OP_REGIM8, 0 }, { "std", OP_MREG2, OP_REGIM8, 0 },
|
||||||
|
{ "illegal", OP_NULL, OP_NULL, 0 }, { "illegal", OP_NULL, OP_NULL, 0 },
|
||||||
|
{ "ld", OP_MREG2, OP_REGIM8, 0 }, { "ld", OP_MREG2, OP_REGIM8, 0 },
|
||||||
|
{ "ldi", OP_MREG2, OP_REGIM8, 0 }, { "ldi", OP_MREG2, OP_REGIM8, 0 },
|
||||||
|
{ "ldd", OP_MREG2, OP_REGIM8, 0 }, { "ldd", OP_MREG2, OP_REGIM8, 0 },
|
||||||
|
{ "illegal", OP_NULL, OP_NULL, 0 }, { "illegal", OP_NULL, OP_NULL, 0 },
|
||||||
|
|
||||||
|
// 0x70
|
||||||
|
{ "cal", OP_JX_COND, OP_IM16A, 0 }, { "cal", OP_JX_COND, OP_IM16A, 0 },
|
||||||
|
{ "cal", OP_JX_COND, OP_IM16A, 0 }, { "cal", OP_JX_COND, OP_IM16A, 0 },
|
||||||
|
{ "cal", OP_JX_COND, OP_IM16A, 0 }, { "cal", OP_JX_COND, OP_IM16A, 0 },
|
||||||
|
{ "cal", OP_JX_COND, OP_IM16A, 0 }, { "cal", OP_IM16A, OP_NULL, 0 },
|
||||||
|
{ "adc", OP_REGIM8, OP_MREG2, 0 }, { "adc", OP_REGIM8, OP_MREG2, 0 },
|
||||||
|
{ "sbc", OP_REGIM8, OP_MREG2, 0 }, { "sbc", OP_REGIM8, OP_MREG2, 0 },
|
||||||
|
{ "ad", OP_REGIM8, OP_MREG2, 0 }, { "ad ", OP_REGIM8, OP_MREG2, 0 },
|
||||||
|
{ "sb", OP_REGIM8, OP_MREG2, 0 }, { "sb", OP_REGIM8, OP_MREG2, 0 },
|
||||||
|
|
||||||
|
// 0x80
|
||||||
|
{ "adcw", OP_MREG, OP_MR_SIR, 1 }, { "sbcw", OP_MREG, OP_MR_SIR, 1 },
|
||||||
|
{ "ldw", OP_MREG, OP_MR_SIR, 1 }, { "illegal", OP_NULL, OP_NULL, 0 },
|
||||||
|
{ "ancw", OP_MREG, OP_MR_SIR, 1 }, { "nacw", OP_MREG, OP_MR_SIR, 1 },
|
||||||
|
{ "orcw", OP_MREG, OP_MR_SIR, 1 }, { "xrcw", OP_MREG, OP_MR_SIR, 1 },
|
||||||
|
{ "adw", OP_MREG, OP_MR_SIR, 1 }, { "sbw", OP_MREG, OP_MR_SIR, 1 },
|
||||||
|
{ "adbw", OP_MREG, OP_MR_SIR, 1 }, { "sbbw", OP_MREG, OP_MR_SIR, 1 },
|
||||||
|
{ "anw", OP_MREG, OP_MR_SIR, 1 }, { "naw", OP_MREG, OP_MR_SIR, 1 },
|
||||||
|
{ "orw", OP_MREG, OP_MR_SIR, 1 }, { "xrw", OP_MREG, OP_MR_SIR, 1 },
|
||||||
|
|
||||||
|
// 0x90
|
||||||
|
{ "stw", OP_MREG, OP_MR_SIRI,1 }, { "ldw", OP_MREG, OP_MR_SIRI,1 },
|
||||||
|
{ "stlw", OP_MREG2, OP_NULL, 1 }, { "ldlw", OP_MREG2, OP_NULL, 1 },
|
||||||
|
{ "illegal", OP_NULL, OP_NULL, 0 }, { "illegal", OP_NULL, OP_NULL, 0 },
|
||||||
|
{ "pre", OP_REG16, OP_MREG2, 1 }, { "pre", OP_REG16, OP_MREG2, 1 },
|
||||||
|
{ "???", OP_MREG2, OP_NULL, 1 }, { "illegal", OP_NULL, OP_NULL, 0 },
|
||||||
|
{ "???", OP_MREG2, OP_NULL, 1 }, { "???", OP_MREG2, OP_NULL, 1 },
|
||||||
|
{ "???", OP_MREG2, OP_NULL, 1 }, { "illegal", OP_NULL, OP_NULL, 0 },
|
||||||
|
{ "gre", OP_REG16, OP_MREG2, 1 }, { "gre", OP_REG16, OP_MREG2, 1 },
|
||||||
|
|
||||||
|
// 0xa0
|
||||||
|
{ "stw", OP_MREG, OP_IR_IM8_, 0 }, { "stw", OP_MREG, OP_IR_IM8_, 0 },
|
||||||
|
{ "stiw", OP_MREG, OP_IR_IM8_, 0 }, { "stiw", OP_MREG, OP_IR_IM8_, 0 },
|
||||||
|
{ "stdw", OP_MREG, OP_IR_IM8_, 0 }, { "stdw", OP_MREG, OP_IR_IM8_, 0 },
|
||||||
|
{ "phsw", OP_MREG2, OP_NULL, 0 }, { "phuw", OP_MREG2, OP_NULL, 0 },
|
||||||
|
{ "ldw", OP_MREG, OP_IR_IM8_, 0 }, { "ldw", OP_MREG, OP_IR_IM8_, 0 },
|
||||||
|
{ "ldiw", OP_MREG, OP_IR_IM8_, 0 }, { "ldiw", OP_MREG, OP_IR_IM8_, 0 },
|
||||||
|
{ "lddw", OP_MREG, OP_IR_IM8_, 0 }, { "lddw", OP_MREG, OP_IR_IM8_, 0 },
|
||||||
|
{ "ppsw", OP_MREG2, OP_NULL, 0 }, { "ppuw", OP_MREG2, OP_NULL, 0 },
|
||||||
|
|
||||||
|
// 0xb0
|
||||||
|
{ "jr", OP_JX_COND, OP_IM7, 0 }, { "jr", OP_JX_COND, OP_IM7, 0 },
|
||||||
|
{ "jr", OP_JX_COND, OP_IM7, 0 }, { "jr", OP_JX_COND, OP_IM7, 0 },
|
||||||
|
{ "jr", OP_JX_COND, OP_IM7, 0 }, { "jr", OP_JX_COND, OP_IM7, 0 },
|
||||||
|
{ "jr", OP_JX_COND, OP_IM7, 0 }, { "jr", OP_IM7, OP_NULL, 0 },
|
||||||
|
{ "adcw", OP_IR_IM8, OP_MREG, 0 }, { "adcw", OP_IR_IM8, OP_MREG, 0 },
|
||||||
|
{ "sbcw", OP_IR_IM8, OP_MREG, 0 }, { "sbcw", OP_IR_IM8, OP_MREG, 0 },
|
||||||
|
{ "adw", OP_IR_IM8, OP_MREG, 0 }, { "adw", OP_IR_IM8, OP_MREG, 0 },
|
||||||
|
{ "sbw", OP_IR_IM8, OP_MREG, 0 }, { "sbw", OP_IR_IM8, OP_MREG, 0 },
|
||||||
|
|
||||||
|
// 0xc0
|
||||||
|
{ "adbcm",OP_MREG, OP_RMSIM3, 1 }, { "sdbcm",OP_MREG, OP_RMSIM3, 1 },
|
||||||
|
{ "ldm", OP_MREG, OP_RMSIM3, 1 }, { "illegal", OP_NULL, OP_NULL, 0 },
|
||||||
|
{ "ancm", OP_MREG, OP_RMSIM3, 1 }, { "nacm", OP_MREG, OP_RMSIM3, 1 },
|
||||||
|
{ "orcm", OP_MREG, OP_RMSIM3, 1 }, { "xrcm", OP_MREG, OP_RMSIM3, 1 },
|
||||||
|
{ "adbm", OP_MREG, OP_RMSIM3, 1 }, { "sbbm", OP_MREG, OP_RMSIM3, 1 },
|
||||||
|
{ "adbm", OP_MREG, OP_RMSIM3, 1 }, { "sbbm", OP_MREG, OP_RMSIM3, 1 },
|
||||||
|
{ "anm", OP_MREG, OP_RMSIM3, 1 }, { "nam", OP_MREG, OP_RMSIM3, 1 },
|
||||||
|
{ "orm", OP_MREG, OP_RMSIM3, 1 }, { "xrm", OP_MREG, OP_RMSIM3, 1 },
|
||||||
|
|
||||||
|
// 0xd0
|
||||||
|
{ "stw", OP_IM16, OP_MR_SIR, 0 }, { "ldw", OP_MREG2, OP_IM16, 0 },
|
||||||
|
{ "stlm", OP_MREG2, OP_IM3, 0 }, { "ldlm", OP_MREG2, OP_IM3, 0 },
|
||||||
|
{ "illegal", OP_NULL, OP_NULL, 0 }, { "illegal", OP_NULL, OP_NULL, 0 },
|
||||||
|
{ "pre", OP_REG16_, OP_IM16, 0 }, { "pre", OP_REG16_, OP_IM16, 0 },
|
||||||
|
{ "bup", OP_NULL, OP_NULL, 0 }, { "bnd", OP_NULL, OP_NULL, 0 },
|
||||||
|
{ "???", OP_MREG2, OP_IM3, 0 }, { "???", OP_MREG2, OP_IM3, 0 },
|
||||||
|
{ "sup", OP_MREG, OP_NULL, 0 }, { "sdn", OP_MREG, OP_NULL, 0 },
|
||||||
|
{ "jp", OP_MREG, OP_NULL, 0 }, { "jp", OP_MREG, OP_NULL, 0 },
|
||||||
|
|
||||||
|
// 0xe0
|
||||||
|
{ "stm", OP_MREG, OP_IR_IM3, 0 }, { "stm", OP_MREG, OP_IR_IM3, 0 },
|
||||||
|
{ "stim", OP_MREG, OP_IR_IM3, 0 }, { "stim", OP_MREG, OP_IR_IM3, 0 },
|
||||||
|
{ "stdm", OP_MREG, OP_IR_IM3, 0 }, { "stdm", OP_MREG, OP_IR_IM3, 0 },
|
||||||
|
{ "phsm", OP_MREG2, OP_IM3, 0 }, { "phum", OP_MREG2, OP_IM3, 0 },
|
||||||
|
{ "ldm", OP_MREG, OP_IR_IM3, 0 }, { "ldm", OP_MREG, OP_IR_IM3, 0 },
|
||||||
|
{ "ldim", OP_MREG, OP_IR_IM3, 0 }, { "ldim", OP_MREG, OP_IR_IM3, 0 },
|
||||||
|
{ "lddm", OP_MREG, OP_IR_IM3, 0 }, { "lddm", OP_MREG, OP_IR_IM3, 0 },
|
||||||
|
{ "ppsm", OP_MREG2, OP_IM3, 0 }, { "ppum", OP_MREG2, OP_IM3, 0 },
|
||||||
|
|
||||||
|
// 0xf0
|
||||||
|
{ "rtn", OP_JX_COND, OP_NULL, 0 }, { "rtn", OP_JX_COND, OP_NULL, 0 },
|
||||||
|
{ "rtn", OP_JX_COND, OP_NULL, 0 }, { "rtn", OP_JX_COND, OP_NULL, 0 },
|
||||||
|
{ "rtn", OP_JX_COND, OP_NULL, 0 }, { "rtn", OP_JX_COND, OP_NULL, 0 },
|
||||||
|
{ "rtn", OP_JX_COND, OP_NULL, 0 }, { "rtn", OP_NULL, OP_NULL, 0 },
|
||||||
|
{ "nop", OP_JX_COND, OP_NULL, 0 }, { "clt", OP_NULL, OP_NULL, 0 },
|
||||||
|
{ "fst", OP_NULL, OP_NULL, 0 }, { "slw", OP_NULL, OP_NULL, 0 },
|
||||||
|
{ "can", OP_NULL, OP_NULL, 0 }, { "rtni", OP_NULL, OP_NULL, 0 },
|
||||||
|
{ "off", OP_NULL, OP_NULL, 0 }, { "trp", OP_NULL, OP_NULL, 0 },
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
inline int dasm_im8(char *buffer, UINT16 pc, int arg, const UINT8 *oprom, int &pos, int type)
|
||||||
|
{
|
||||||
|
if (((arg>>5) & 0x03) == 0x03)
|
||||||
|
{
|
||||||
|
INC_POS;
|
||||||
|
UINT8 ret = sprintf( buffer, "0x%02x", oprom[POS] & 0x1f );
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return sprintf( buffer, "%s", reg_5b[(arg>>5) & 0x03] );
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
inline int dasm_im8(char *buffer, UINT16 pc, int arg, int arg1, const UINT8 *oprom, int &pos)
|
||||||
|
{
|
||||||
|
if (((arg>>5) & 0x03) == 0x03)
|
||||||
|
{
|
||||||
|
return sprintf( buffer, "0x%02x", arg1 & 0x1f );
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return sprintf( buffer, "%s", reg_5b[(arg>>5) & 0x03] );
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
int dasm_arg(char *buffer, UINT8 op, UINT16 pc, int arg, const UINT8 *oprom, int &pos)
|
||||||
|
{
|
||||||
|
char* buffer_start = buffer;
|
||||||
|
int type = EXT_ROM;
|
||||||
|
|
||||||
|
switch( arg )
|
||||||
|
{
|
||||||
|
case OP_MREG:
|
||||||
|
case OP_MREG2:
|
||||||
|
buffer += sprintf( buffer, "$%02u", oprom[POS] & 0x1f );
|
||||||
|
if (arg == OP_MREG2) INC_POS;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case OP_RSIR:
|
||||||
|
buffer += sprintf( buffer, "%s", reg_5b[(oprom[POS]>>5) & 0x03] );
|
||||||
|
break;
|
||||||
|
|
||||||
|
case OP_REG8:
|
||||||
|
case OP_REG8_:
|
||||||
|
buffer += sprintf( buffer, "%s", reg_8b[(BIT(op,0)<<2) + ((oprom[POS]>>5&3))]);
|
||||||
|
if (arg == OP_REG8_) INC_POS;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case OP_MR_SIR:
|
||||||
|
buffer += dasm_im8(buffer, pc, oprom[POS], oprom, pos, type);
|
||||||
|
INC_POS;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case OP_IR_IM8:
|
||||||
|
case OP_IR_IM8_:
|
||||||
|
buffer += sprintf( buffer, "(%s%s", (op&1) ? "iz": "ix", (oprom[POS]&0x80) ? "-": "+");
|
||||||
|
buffer += dasm_im8(buffer, pc, oprom[POS], oprom, pos, type);
|
||||||
|
buffer += sprintf( buffer, ")");
|
||||||
|
if (arg == OP_IR_IM8_) INC_POS;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case OP_IM8_:
|
||||||
|
INC_POS;
|
||||||
|
case OP_IM8:
|
||||||
|
buffer += sprintf( buffer, "0x%02x", oprom[POS] );
|
||||||
|
INC_POS;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case OP_IM8I:
|
||||||
|
buffer += sprintf( buffer, "(0x%02x)", oprom[POS] );
|
||||||
|
INC_POS;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case OP_REGIM8:
|
||||||
|
buffer += sprintf( buffer, "(%s%s", (op&1) ? "iz": "ix", (oprom[POS]&0x80) ? "-": "+");
|
||||||
|
buffer += sprintf( buffer, "%x)", oprom[POS] & 0x1f);
|
||||||
|
INC_POS;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case OP_JX_COND:
|
||||||
|
buffer += sprintf( buffer, "%s", jp_cond[op & 0x07] );
|
||||||
|
break;
|
||||||
|
|
||||||
|
|
||||||
|
case OP_RMSIM3:
|
||||||
|
{
|
||||||
|
UINT8 tmp = oprom[POS];
|
||||||
|
INC_POS;
|
||||||
|
buffer += dasm_im8(buffer, pc, tmp, oprom[POS], oprom, pos);
|
||||||
|
buffer += sprintf( buffer, ", 0x%02x", ((tmp>>5)&7)+1);
|
||||||
|
INC_POS;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case OP_IR_IM3:
|
||||||
|
{
|
||||||
|
UINT8 tmp = oprom[POS];
|
||||||
|
INC_POS;
|
||||||
|
buffer += sprintf( buffer, "(%s%s", (op&1) ? "iz": "ix", (tmp&0x80) ? "-": "+");
|
||||||
|
buffer += dasm_im8(buffer, pc, tmp, oprom[POS], oprom, pos);
|
||||||
|
buffer += sprintf( buffer, "), 0x%02x", ((oprom[POS]>>5)&7)+1 );
|
||||||
|
INC_POS;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case OP_IM3:
|
||||||
|
buffer += sprintf( buffer, "0x%02x", ((oprom[POS]>>5)&7)+1 );
|
||||||
|
INC_POS;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case OP_MR_SIRI:
|
||||||
|
buffer += sprintf( buffer, "(");
|
||||||
|
buffer += dasm_im8(buffer, pc, oprom[POS], oprom, pos, type);
|
||||||
|
buffer += sprintf( buffer, ")");
|
||||||
|
INC_POS;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case OP_IM7:
|
||||||
|
{
|
||||||
|
int tmp = oprom[POS];
|
||||||
|
if (tmp&0x80) tmp = 0x80 - tmp;
|
||||||
|
|
||||||
|
buffer += sprintf( buffer, "0x%04x", (pc + tmp) & 0xffff );
|
||||||
|
INC_POS;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case OP_IM5:
|
||||||
|
buffer += sprintf( buffer, "0x%02x", oprom[POS]&0x1f );
|
||||||
|
INC_POS;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case OP_REG16:
|
||||||
|
case OP_REG16_:
|
||||||
|
buffer += sprintf( buffer, "%s", reg_16b[(BIT(op,0)<<2) + ((oprom[POS]>>5&3))]);
|
||||||
|
if (arg == OP_REG16_) INC_POS;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case OP_IM16:
|
||||||
|
case OP_IM16A:
|
||||||
|
{
|
||||||
|
UINT8 tmp1 = oprom[POS];
|
||||||
|
INC_POS;
|
||||||
|
if (!EXT_ROM && arg == OP_IM16A) INC_POS;
|
||||||
|
UINT8 tmp2 = oprom[POS];
|
||||||
|
buffer += sprintf( buffer, "0x%04x", ((tmp2<<8) | tmp1));
|
||||||
|
INC_POS;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case OP_NULL:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return buffer - buffer_start;
|
||||||
|
}
|
||||||
|
|
||||||
|
UINT32 get_dasmflags(UINT8 op)
|
||||||
|
{
|
||||||
|
switch (op)
|
||||||
|
{
|
||||||
|
case 0x30: case 0x31: case 0x32: case 0x33: //jp
|
||||||
|
case 0x34: case 0x35: case 0x36: case 0x37: //jp
|
||||||
|
case 0x70: case 0x71: case 0x72: case 0x73: //cal
|
||||||
|
case 0x74: case 0x75: case 0x76: case 0x77: //cal
|
||||||
|
case 0xb0: case 0xb1: case 0xb2: case 0xb3: //jr
|
||||||
|
case 0xb4: case 0xb5: case 0xb6: case 0xb7: //jr
|
||||||
|
case 0xde: //jp
|
||||||
|
case 0xdf: //jp
|
||||||
|
return DASMFLAG_STEP_OVER;
|
||||||
|
case 0xf0: case 0xf1: case 0xf2: case 0xf3: //rtn
|
||||||
|
case 0xf4: case 0xf5: case 0xf6: case 0xf7: //rtn
|
||||||
|
case 0xfd: //rtni
|
||||||
|
return DASMFLAG_STEP_OUT;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
CPU_DISASSEMBLE( hd61700 )
|
||||||
|
{
|
||||||
|
const hd61700_dasm *inst;
|
||||||
|
UINT32 dasmflags = 0;
|
||||||
|
UINT8 op, op1;
|
||||||
|
int pos = 0, type = EXT_ROM;
|
||||||
|
|
||||||
|
op = oprom[POS];
|
||||||
|
INC_POS;
|
||||||
|
|
||||||
|
dasmflags = get_dasmflags(op);
|
||||||
|
|
||||||
|
op1 = oprom[POS];
|
||||||
|
|
||||||
|
inst = &hd61700_ops[op];
|
||||||
|
|
||||||
|
buffer += sprintf(buffer,"%-8s", inst->str);
|
||||||
|
|
||||||
|
//dasm first arg
|
||||||
|
buffer += dasm_arg(buffer, op, pc, inst->arg1, oprom, pos);
|
||||||
|
|
||||||
|
//if present dasm second arg
|
||||||
|
if (inst->arg2 != OP_NULL)
|
||||||
|
{
|
||||||
|
buffer += sprintf(buffer,", ");
|
||||||
|
buffer += dasm_arg(buffer, op, pc, inst->arg2, oprom, pos);
|
||||||
|
}
|
||||||
|
|
||||||
|
//if required add the optional jr
|
||||||
|
if (inst->optjr == true && BIT(op1, 7))
|
||||||
|
{
|
||||||
|
buffer += sprintf( buffer, ", jr ");
|
||||||
|
buffer += dasm_arg(buffer, op, pc+1, OP_IM7, oprom, pos);
|
||||||
|
|
||||||
|
dasmflags = DASMFLAG_STEP_OVER;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (pos&1) INC_POS;
|
||||||
|
|
||||||
|
return (pos>>1) | dasmflags | DASMFLAG_SUPPORTED;
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue
Block a user