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debugger_access: Refactor [O. Galibert]

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This commit is contained in:
Olivier Galibert 2017-02-26 22:03:45 +01:00
parent 4e59ab6ffe
commit 0cdc64d36c
118 changed files with 433 additions and 509 deletions
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4
src/devices/bus/a2bus/a2bus.cpp
View File

@ -248,15 +248,11 @@ void a2bus_device::set_maincpu_halt(int state)
uint8_t a2bus_device::dma_r(address_space &space, uint16_t offset)
{
m_maincpu_space->set_debugger_access(space.debugger_access());
return m_maincpu_space->read_byte(offset);
}
void a2bus_device::dma_w(address_space &space, uint16_t offset, uint8_t data)
{
m_maincpu_space->set_debugger_access(space.debugger_access());
m_maincpu_space->write_byte(offset, data);
}

2
src/devices/bus/a2bus/pc_xporter.cpp
View File

@ -317,7 +317,7 @@ uint8_t a2bus_pcxporter_device::read_c800(address_space &space, uint16_t offset)
case 0x703: // read with increment
rv = m_ram[m_offset];
// don't increment if the debugger's reading
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
m_offset++;
}

2
src/devices/bus/amiga/keyboard/a500.cpp
View File

@ -450,7 +450,7 @@ WRITE8_MEMBER( a500_kbd_device::latch_w )
READ8_MEMBER( a500_kbd_device::counter_r )
{
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
m_control &= ~COUNTER_OVERFLOW;
update_irqs();

2
src/devices/bus/c64/currah_speech.cpp
View File

@ -214,7 +214,7 @@ uint8_t c64_currah_speech_cartridge_device::c64_cd_r(address_space &space, offs_
data = m_nsp->sby_r() << 7;
}
if (!space.debugger_access() && (offset == 0xa7f0))
if (!machine().side_effect_disabled() && (offset == 0xa7f0))
{
m_game = !m_game;
m_exrom = !m_exrom;

2
src/devices/bus/isa/ega.cpp
View File

@ -966,7 +966,7 @@ READ8_MEMBER( isa8_ega_device::read )
{
uint8_t data = 0xFF;
if ( !space.debugger_access() && ! ( m_sequencer.data[4] & 0x04 ) )
if ( !machine().side_effect_disabled() && ! ( m_sequencer.data[4] & 0x04 ) )
{
/* Fill read latches */
m_read_latch[0] = m_plane[0][offset & 0xffff];

2
src/devices/bus/isa/sb16.cpp
View File

@ -16,7 +16,7 @@ const device_type ISA16_SB16 = device_creator<sb16_lle_device>;
READ8_MEMBER( sb16_lle_device::dsp_data_r )
{
if(!space.debugger_access())
if(!machine().side_effect_disabled())
m_data_in = false;
return m_in_byte;

2
src/devices/bus/msx_cart/holy_quran.cpp
View File

@ -81,7 +81,7 @@ READ8_MEMBER(msx_cart_holy_quran::read_cart)
// The decryption should actually start working after the first M1 cycle executing something
// from the cartridge.
if (offset == ((m_rom[3] << 8) | m_rom[2]) && !space.debugger_access())
if (offset == ((m_rom[3] << 8) | m_rom[2]) && !machine().side_effect_disabled())
{
m_decrypt = true;
}

6
src/devices/bus/ti99_peb/bwg.cpp
View File

@ -137,7 +137,7 @@ WRITE_LINE_MEMBER( snug_bwg_device::fdc_drq_w )
SETADDRESS_DBIN_MEMBER( snug_bwg_device::setaddress_dbin )
{
// Do not allow setaddress for debugger
if (space.debugger_access()) return;
if (machine().side_effect_disabled()) return;
// Selection login in the PAL and some circuits on the board
@ -216,7 +216,7 @@ void snug_bwg_device::debug_write(offs_t offset, uint8_t data)
*/
READ8Z_MEMBER(snug_bwg_device::readz)
{
if (space.debugger_access())
if (machine().side_effect_disabled())
{
debug_read(offset, value);
return;
@ -286,7 +286,7 @@ READ8Z_MEMBER(snug_bwg_device::readz)
*/
WRITE8_MEMBER(snug_bwg_device::write)
{
if (space.debugger_access())
if (machine().side_effect_disabled())
{
debug_write(offset, data);
return;

2
src/devices/bus/ti99_peb/evpc.cpp
View File

@ -68,7 +68,7 @@ SETADDRESS_DBIN_MEMBER( snug_enhanced_video_device::setaddress_dbin )
{
// Do not allow setaddress for the debugger. It will mess up the
// setaddress/memory access pairs when the CPU enters wait states.
if (space.debugger_access()) return;
if (machine().side_effect_disabled()) return;
if (TRACE_ADDRESS) logerror("set address %04x, %s\n", offset, (state==ASSERT_LINE)? "read" : "write");

6
src/devices/bus/ti99_peb/hfdc.cpp
View File

@ -105,7 +105,7 @@ SETADDRESS_DBIN_MEMBER( myarc_hfdc_device::setaddress_dbin )
{
// Do not allow setaddress for the debugger. It will mess up the
// setaddress/memory access pairs when the CPU enters wait states.
if (space.debugger_access()) return;
if (machine().side_effect_disabled()) return;
// Selection login in the PAL and some circuits on the board
@ -197,7 +197,7 @@ void myarc_hfdc_device::debug_write(offs_t offset, uint8_t data)
*/
READ8Z_MEMBER(myarc_hfdc_device::readz)
{
if (space.debugger_access())
if (machine().side_effect_disabled())
{
debug_read(offset, value);
return;
@ -276,7 +276,7 @@ READ8Z_MEMBER(myarc_hfdc_device::readz)
*/
WRITE8_MEMBER( myarc_hfdc_device::write )
{
if (space.debugger_access())
if (machine().side_effect_disabled())
{
debug_write(offset, data);
return;

4
src/devices/bus/ti99_peb/hsgpl.cpp
View File

@ -342,7 +342,7 @@ void snug_high_speed_gpl_device::cartspace_readz(address_space& space, offs_t of
*/
void snug_high_speed_gpl_device::grom_readz(address_space& space, offs_t offset, uint8_t* value, uint8_t mem_mask)
{
if (space.debugger_access()) return;
if (machine().side_effect_disabled()) return;
//activedevice_adjust_icount(-4);
@ -528,7 +528,7 @@ void snug_high_speed_gpl_device::cartspace_write(address_space& space, offs_t of
*/
void snug_high_speed_gpl_device::grom_write(address_space& space, offs_t offset, uint8_t data, uint8_t mem_mask)
{
if (space.debugger_access()) return;
if (machine().side_effect_disabled()) return;
//activedevice_adjust_icount(-4);

4
src/devices/bus/ti99_peb/pcode.cpp
View File

@ -154,7 +154,7 @@ void ti_pcode_card_device::debugger_read(address_space& space, uint16_t offset,
READ8Z_MEMBER( ti_pcode_card_device::readz )
{
// Care for debugger
if (space.debugger_access())
if (machine().side_effect_disabled())
{
debugger_read(space, offset, *value);
}
@ -197,7 +197,7 @@ READ8Z_MEMBER( ti_pcode_card_device::readz )
*/
WRITE8_MEMBER( ti_pcode_card_device::write )
{
if (space.debugger_access()) return;
if (machine().side_effect_disabled()) return;
if (m_active && m_isgrom && m_selected)
{
for (auto & elem : m_grom) elem->write(space, m_address, data);

4
src/devices/bus/ti99_peb/spchsyn.cpp
View File

@ -47,7 +47,7 @@ ti_speech_synthesizer_device::ti_speech_synthesizer_device(const machine_config
READ8Z_MEMBER( ti_speech_synthesizer_device::readz )
{
if (space.debugger_access()) return;
if (machine().side_effect_disabled()) return;
if (m_sbe)
{
@ -66,7 +66,7 @@ READ8Z_MEMBER( ti_speech_synthesizer_device::readz )
*/
WRITE8_MEMBER( ti_speech_synthesizer_device::write )
{
if (space.debugger_access()) return;
if (machine().side_effect_disabled()) return;
if (m_sbe)
{

8
src/devices/bus/ti99_peb/ti_fdc.cpp
View File

@ -142,7 +142,7 @@ void ti_fdc_device::debug_read(offs_t offset, uint8_t* value)
READ8Z_MEMBER(ti_fdc_device::readz)
{
if (space.debugger_access())
if (machine().side_effect_disabled())
{
debug_read(offset, value);
return;
@ -156,7 +156,7 @@ READ8Z_MEMBER(ti_fdc_device::readz)
if (m_WDsel && ((m_address & 9)==0))
{
if (!space.debugger_access()) reply = m_fd1771->gen_r((offset >> 1)&0x03);
if (!machine().side_effect_disabled()) reply = m_fd1771->gen_r((offset >> 1)&0x03);
if (TRACE_DATA)
{
if ((m_address & 0xffff)==0x5ff6)
@ -183,7 +183,7 @@ READ8Z_MEMBER(ti_fdc_device::readz)
WRITE8_MEMBER(ti_fdc_device::write)
{
if (space.debugger_access()) return;
if (machine().side_effect_disabled()) return;
if (m_inDsrArea && m_selected)
{
@ -201,7 +201,7 @@ WRITE8_MEMBER(ti_fdc_device::write)
{
// As this is a memory-mapped access we must prevent the debugger
// from messing with the operation
if (!space.debugger_access()) m_fd1771->gen_w((offset >> 1)&0x03, data);
if (!machine().side_effect_disabled()) m_fd1771->gen_w((offset >> 1)&0x03, data);
}
}
}

4
src/devices/bus/ti99_peb/tn_ide.cpp
View File

@ -128,7 +128,7 @@ WRITE8_MEMBER(nouspikel_ide_interface_device::cruwrite)
READ8Z_MEMBER(nouspikel_ide_interface_device::readz)
{
uint8_t reply = 0;
if (space.debugger_access()) return;
if (machine().side_effect_disabled()) return;
if (((offset & m_select_mask)==m_select_value) && m_selected)
{
@ -194,7 +194,7 @@ READ8Z_MEMBER(nouspikel_ide_interface_device::readz)
*/
WRITE8_MEMBER(nouspikel_ide_interface_device::write)
{
if (space.debugger_access()) return;
if (machine().side_effect_disabled()) return;
if (((offset & m_select_mask)==m_select_value) && m_selected)
{

4
src/devices/bus/ti99_peb/tn_usbsm.cpp
View File

@ -180,7 +180,7 @@ WRITE8_MEMBER(nouspikel_usb_smartmedia_device::cruwrite)
*/
READ8Z_MEMBER(nouspikel_usb_smartmedia_device::readz)
{
if (space.debugger_access()) return;
if (machine().side_effect_disabled()) return;
if (((offset & m_select_mask)==m_select_value) && m_selected)
{
@ -231,7 +231,7 @@ READ8Z_MEMBER(nouspikel_usb_smartmedia_device::readz)
*/
WRITE8_MEMBER(nouspikel_usb_smartmedia_device::write)
{
if (space.debugger_access()) return;
if (machine().side_effect_disabled()) return;
if (((offset & m_select_mask)==m_select_value) && m_selected)
{

4
src/devices/bus/ti99x/datamux.cpp
View File

@ -322,7 +322,7 @@ READ16_MEMBER( ti99_datamux_device::read )
uint16_t value = 0;
// Care for debugger
if (space.debugger_access())
if (machine().side_effect_disabled())
{
return debugger_read(space, offset);
}
@ -371,7 +371,7 @@ READ16_MEMBER( ti99_datamux_device::read )
*/
WRITE16_MEMBER( ti99_datamux_device::write )
{
if (space.debugger_access())
if (machine().side_effect_disabled())
{
debugger_write(space, offset, data);
return;

18
src/devices/bus/ti99x/genboard.cpp
View File

@ -487,7 +487,7 @@ READ8_MEMBER( geneve_mapper_device::readm )
decdata debug;
// For the debugger, do the decoding here with no wait states
if (space.debugger_access())
if (machine().side_effect_disabled())
{
if (m_cpu->is_onchip(offset)) return m_cpu->debug_read_onchip_memory(offset&0xff);
dec = &debug;
@ -504,7 +504,7 @@ READ8_MEMBER( geneve_mapper_device::readm )
switch (dec->function)
{
case MLGVIDEO:
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
value = m_video->read(space, dec->offset>>1);
if (TRACE_READ) logerror("Read video %04x -> %02x\n", dec->offset, value);
@ -522,7 +522,7 @@ READ8_MEMBER( geneve_mapper_device::readm )
case MLGKEY:
// key
if (!space.debugger_access()) value = m_keyboard->get_recent_key();
if (!machine().side_effect_disabled()) value = m_keyboard->get_recent_key();
if (TRACE_READ) logerror("Read keyboard -> %02x\n", value);
break;
@ -542,7 +542,7 @@ READ8_MEMBER( geneve_mapper_device::readm )
case MLTKEY:
// key
if (!space.debugger_access()) value = m_keyboard->get_recent_key();
if (!machine().side_effect_disabled()) value = m_keyboard->get_recent_key();
if (TRACE_READ) logerror("Read keyboard -> %02x\n", value);
break;
@ -564,7 +564,7 @@ READ8_MEMBER( geneve_mapper_device::readm )
// video
// ++++ ++-- ---- ---+
// 1000 1000 0000 00x0
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
value = m_video->read(space, dec->offset>>1);
if (TRACE_READ) logerror("Read video %04x -> %02x\n", dec->offset, value);
@ -587,7 +587,7 @@ READ8_MEMBER( geneve_mapper_device::readm )
// grom simulation
// ++++ ++-- ---- ---+
// 1001 1000 0000 00x0
if (!space.debugger_access()) value = read_grom(space, dec->offset, 0xff);
if (!machine().side_effect_disabled()) value = read_grom(space, dec->offset, 0xff);
if (TRACE_READ) logerror("Read GROM %04x -> %02x\n", dec->offset, value);
break;
@ -674,7 +674,7 @@ WRITE8_MEMBER( geneve_mapper_device::writem )
decdata debug;
// For the debugger, do the decoding here with no wait states
if (space.debugger_access())
if (machine().side_effect_disabled())
{
dec = &debug;
m_debug_no_ws = true;
@ -694,7 +694,7 @@ WRITE8_MEMBER( geneve_mapper_device::writem )
// ++++ ++++ ++++ ---+
// 1111 0001 0000 .cc0
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
m_video->write(space, dec->offset>>1, data);
if (TRACE_WRITE) logerror("Write video %04x <- %02x\n", offset, data);
@ -740,7 +740,7 @@ WRITE8_MEMBER( geneve_mapper_device::writem )
// ++++ ++-- ---- ---+
// 1000 1100 0000 00c0
// Initialize waitstate timer
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
m_video->write(space, dec->offset>>1, data);
if (TRACE_WRITE) logerror("Write video %04x <- %02x\n", offset, data);

2
src/devices/bus/vcs/dpc.cpp
View File

@ -294,7 +294,7 @@ WRITE8_MEMBER(a26_rom_dpc_device::write_bank)
DIRECT_UPDATE_MEMBER(a26_rom_dpc_device::cart_opbase)
{
if (!direct.space().debugger_access())
if (!machine().side_effect_disabled())
{
uint8_t new_bit;
new_bit = (m_dpc->m_shift_reg & 0x80) ^ ((m_dpc->m_shift_reg & 0x20) << 2);

28
src/devices/bus/vcs/rom.cpp
View File

@ -360,7 +360,7 @@ READ8_MEMBER(a26_rom_f4_device::read_rom)
}
// update banks
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
switch (offset)
{
@ -426,7 +426,7 @@ READ8_MEMBER(a26_rom_f6_device::read_rom)
}
// update banks
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
switch (offset)
{
@ -469,7 +469,7 @@ DIRECT_UPDATE_MEMBER(a26_rom_f6_device::cart_opbase)
{
if ((address & 0x1fff) >= 0x1ff6 && (address & 0x1fff) <= 0x1ff9)
{
if (!direct.space().debugger_access())
if (!machine().side_effect_disabled())
write_bank(direct.space(), (address & 0x1fff) - 0x1ff6, 0);
}
return address;
@ -494,7 +494,7 @@ READ8_MEMBER(a26_rom_f8_device::read_rom)
}
// update banks
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
switch (offset)
{
@ -550,7 +550,7 @@ READ8_MEMBER(a26_rom_fa_device::read_rom)
}
// update banks
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
switch (offset)
{
@ -618,7 +618,7 @@ READ8_MEMBER(a26_rom_fe_device::read_rom)
data = m_rom[offset + (m_base_bank * 0x1000)];
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
if (m_trigger_on_next_access)
{
@ -643,7 +643,7 @@ READ8_MEMBER(a26_rom_fe_device::read_bank)
{
uint8_t data = space.read_byte(0xfe + offset);
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
switch (offset & 1)
{
@ -667,7 +667,7 @@ READ8_MEMBER(a26_rom_fe_device::read_bank)
WRITE8_MEMBER(a26_rom_fe_device::write_bank)
{
space.write_byte(0xfe, data);
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
// The next byte on the data bus determines which bank to switch to
m_trigger_on_next_access = 1;
@ -753,7 +753,7 @@ WRITE8_MEMBER(a26_rom_3f_device::write_bank)
READ8_MEMBER(a26_rom_e0_device::read_rom)
{
// update banks
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
if (offset >= 0xfe0 && offset <= 0xff8)
m_base_banks[(offset >> 3) & 3] = offset & 7;
@ -792,7 +792,7 @@ WRITE8_MEMBER(a26_rom_e0_device::write_bank)
READ8_MEMBER(a26_rom_e7_device::read_rom)
{
// update banks
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
if (offset >= 0xfe0 && offset <= 0xfe7)
m_base_bank = offset - 0xfe0;
@ -858,7 +858,7 @@ READ8_MEMBER(a26_rom_ua_device::read_rom)
READ8_MEMBER(a26_rom_ua_device::read_bank)
{
if (!space.debugger_access())
if (!machine().side_effect_disabled())
m_base_bank = offset >> 6;
return 0;
@ -913,7 +913,7 @@ WRITE8_MEMBER(a26_rom_cv_device::write_bank)
READ8_MEMBER(a26_rom_dc_device::read_rom)
{
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
if (offset == 0xff0)
m_base_bank = (m_base_bank + 1) & 0x0f;
@ -943,7 +943,7 @@ WRITE8_MEMBER(a26_rom_dc_device::write_bank)
READ8_MEMBER(a26_rom_fv_device::read_rom)
{
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
if (offset == 0xfd0)
{
@ -1027,7 +1027,7 @@ READ8_MEMBER(a26_rom_4in1_device::read_rom)
READ8_MEMBER(a26_rom_8in1_device::read_rom)
{
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
switch (offset)
{

2
src/devices/bus/vcs/scharger.cpp
View File

@ -116,7 +116,7 @@ inline uint8_t a26_rom_ss_device::read_byte(uint32_t offset)
READ8_MEMBER(a26_rom_ss_device::read_rom)
{
if (space.debugger_access())
if (machine().side_effect_disabled())
return read_byte(offset);
// Bankswitch

10
src/devices/cpu/alto2/a2hw.cpp
View File

@ -242,7 +242,7 @@ READ16_MEMBER( alto2_cpu_device::utilin_r )
data = m_hw.utilin;
if (!space.debugger_access()) {
if (!machine().side_effect_disabled()) {
LOG((this,LOG_HW,2," UTILIN rd %#o (%#o)\n", offset, data));
}
return data;
@ -258,7 +258,7 @@ READ16_MEMBER( alto2_cpu_device::xbus_r )
{
uint16_t data = m_hw.xbus[offset & 3];
if (!space.debugger_access()) {
if (!machine().side_effect_disabled()) {
LOG((this,LOG_HW,2," XBUS[%d] rd %#o (%#o)\n", offset & 3, offset, data));
}
return data;
@ -274,7 +274,7 @@ READ16_MEMBER( alto2_cpu_device::xbus_r )
*/
WRITE16_MEMBER( alto2_cpu_device::xbus_w )
{
if (!space.debugger_access()) {
if (!machine().side_effect_disabled()) {
LOG((this,LOG_HW,2," XBUS[%d] wr %#o (%#o)\n", offset & 3, offset, data));
}
m_hw.xbus[offset&3] = data;
@ -289,7 +289,7 @@ WRITE16_MEMBER( alto2_cpu_device::xbus_w )
READ16_MEMBER( alto2_cpu_device::utilout_r )
{
uint16_t data = m_hw.utilout ^ 0177777;
if (!space.debugger_access()) {
if (!machine().side_effect_disabled()) {
LOG((this,0,2," UTILOUT rd %#o (%#o)\n", offset, data));
}
return data;
@ -305,7 +305,7 @@ READ16_MEMBER( alto2_cpu_device::utilout_r )
*/
WRITE16_MEMBER( alto2_cpu_device::utilout_w )
{
if (!space.debugger_access()) {
if (!machine().side_effect_disabled()) {
LOG((this,LOG_HW,2," UTILOUT wr %#o (%#o)\n", offset, data));
}
m_hw.utilout = data ^ 0177777;

4
src/devices/cpu/alto2/a2kbd.cpp
View File

@ -32,11 +32,11 @@ READ16_MEMBER( alto2_cpu_device::kbd_ad_r )
break;
}
m_kbd.matrix[offset & 03] = data;
if (!space.debugger_access()) {
if (!machine().side_effect_disabled()) {
LOG((this,LOG_KBD,2," read KBDAD+%o (%#o)\n", offset & 3, data));
}
if (0 == (offset & 3) && (m_kbd.bootkey != 0177777)) {
if (!space.debugger_access()) {
if (!machine().side_effect_disabled()) {
LOG((this,0,2," boot keys (%#o & %#o)\n", data, m_kbd.bootkey));
}
data &= m_kbd.bootkey;

16
src/devices/cpu/alto2/a2mem.cpp
View File

@ -485,7 +485,7 @@ uint32_t alto2_cpu_device::hamming_code(bool write, uint32_t dw_addr, uint32_t d
READ16_MEMBER( alto2_cpu_device::mear_r )
{
int data = m_mem.error ? m_mem.mear : m_mem.mar;
if (!space.debugger_access()) {
if (!machine().side_effect_disabled()) {
LOG((this,LOG_MEM,2," MEAR read %07o\n", data));
}
return data;
@ -510,7 +510,7 @@ READ16_MEMBER( alto2_cpu_device::mear_r )
READ16_MEMBER( alto2_cpu_device::mesr_r )
{
uint16_t data = m_mem.mesr ^ 0177777;
if (!space.debugger_access()) {
if (!machine().side_effect_disabled()) {
LOG((this,LOG_MEM,2," MESR read %07o\n", data));
LOG((this,LOG_MEM,6," Hamming code read : %#o\n", GET_MESR_HAMMING(data)));
LOG((this,LOG_MEM,6," Parity error : %o\n", GET_MESR_PERR(data)));
@ -523,7 +523,7 @@ READ16_MEMBER( alto2_cpu_device::mesr_r )
WRITE16_MEMBER( alto2_cpu_device::mesr_w )
{
if (!space.debugger_access()) {
if (!machine().side_effect_disabled()) {
LOG((this,LOG_MEM,2," MESR write %07o (clear MESR; was %07o)\n", data, m_mem.mesr));
m_mem.mesr = 0; // set all bits to 0
m_mem.error = 0; // reset the error flag
@ -558,7 +558,7 @@ WRITE16_MEMBER( alto2_cpu_device::mecr_w )
// clear spare bits
X_WRBITS(m_mem.mecr,16, 0, 3,0);
X_WRBITS(m_mem.mecr,16,15,15,0);
if (!space.debugger_access()) {
if (!machine().side_effect_disabled()) {
LOG((this,LOG_MEM,2," MECR write %07o\n", data));
LOG((this,LOG_MEM,6," Test Hamming code : %#o\n", GET_MECR_TEST_CODE(m_mem.mecr)));
LOG((this,LOG_MEM,6," Test mode : %s\n", GET_MECR_TEST_MODE(m_mem.mecr) ? "on" : "off"));
@ -575,7 +575,7 @@ READ16_MEMBER( alto2_cpu_device::mecr_r )
{
uint16_t data = m_mem.mecr ^ 0177777;
// all spare bits are set
if (!space.debugger_access()) {
if (!machine().side_effect_disabled()) {
LOG((this,LOG_MEM,2," MECR read %07o\n", data));
LOG((this,LOG_MEM,6," Test Hamming code : %#o\n", GET_MECR_TEST_CODE(data)));
LOG((this,LOG_MEM,6," Test mode : %s\n", GET_MECR_TEST_MODE(data) ? "on" : "off"));
@ -772,9 +772,8 @@ uint16_t alto2_cpu_device::debug_read_mem(uint32_t addr)
int base_addr = addr & 0177777;
int data;
if (addr >= ALTO2_IO_PAGE_BASE && addr < ALTO2_RAM_SIZE) {
space(AS_2).set_debugger_access(true);
auto dis = machine().disable_side_effect();
data = m_iomem->read_word(m_iomem->address_to_byte(base_addr));
space(AS_2).set_debugger_access(false);
} else {
data = (addr & ALTO2_MEM_ODD) ? GET_ODD(m_mem.ram[addr/2]) : GET_EVEN(m_mem.ram[addr/2]);
}
@ -791,9 +790,8 @@ void alto2_cpu_device::debug_write_mem(uint32_t addr, uint16_t data)
{
int base_addr = addr & 0177777;
if (addr >= ALTO2_IO_PAGE_BASE && addr < ALTO2_RAM_SIZE) {
space(AS_2).set_debugger_access(true);
auto dis = machine().disable_side_effect();
m_iomem->write_word(m_iomem->address_to_byte(base_addr), data);
space(AS_2).set_debugger_access(false);
} else if (addr & ALTO2_MEM_ODD) {
PUT_ODD(m_mem.ram[addr/2], data);
} else {

4
src/devices/cpu/e0c6200/e0c6s46.cpp
View File

@ -628,7 +628,7 @@ READ8_MEMBER(e0c6s46_device::io_r)
{
// irq flags are reset(acked) when read
u8 flag = m_irqflag[offset];
if (!space.debugger_access())
if (!machine().side_effect_disabled())
m_irqflag[offset] = 0;
return flag;
}
@ -705,7 +705,7 @@ READ8_MEMBER(e0c6s46_device::io_r)
break;
default:
if (!space.debugger_access())
if (!machine().side_effect_disabled())
logerror("%s unknown io_r from $0F%02X at $%04X\n", tag(), offset, m_prev_pc);
break;
}

12
src/devices/cpu/lc8670/lc8670.cpp
View File

@ -914,7 +914,7 @@ WRITE8_MEMBER(lc8670_cpu_device::mram_w)
READ8_MEMBER(lc8670_cpu_device::xram_r)
{
if (!(REG_VCCR & 0x40) || space.debugger_access()) // XRAM access enabled
if (!(REG_VCCR & 0x40) || machine().side_effect_disabled()) // XRAM access enabled
{
uint8_t * xram_bank = m_xram + (REG_XBNK & 0x03) * 0x60;
@ -937,7 +937,7 @@ READ8_MEMBER(lc8670_cpu_device::xram_r)
WRITE8_MEMBER(lc8670_cpu_device::xram_w)
{
if (!(REG_VCCR & 0x40) || space.debugger_access()) // XRAM access enabled
if (!(REG_VCCR & 0x40) || machine().side_effect_disabled()) // XRAM access enabled
{
uint8_t * xram_bank = m_xram + (REG_XBNK & 0x03) * 0x60;
@ -977,7 +977,7 @@ READ8_MEMBER(lc8670_cpu_device::regs_r)
case 0x66:
{
uint8_t data = m_vtrbf[((REG_VRMAD2<<8) | REG_VRMAD1) & 0x1ff];
if (!space.debugger_access() && (REG_VSEL & 0x10))
if (!machine().side_effect_disabled() && (REG_VSEL & 0x10))
{
uint16_t vrmad = (REG_VRMAD1 | (REG_VRMAD2<<8)) + 1;
REG_VRMAD1 = vrmad & 0xff;
@ -989,7 +989,7 @@ READ8_MEMBER(lc8670_cpu_device::regs_r)
// write-only registers
case 0x20: case 0x23: case 0x24: case 0x27:
case 0x45: case 0x46: case 0x4d:
if(!space.debugger_access()) logerror("%s: read write-only SFR %04x\n", machine().describe_context(), offset);
if(!machine().side_effect_disabled()) logerror("%s: read write-only SFR %04x\n", machine().describe_context(), offset);
return 0xff;
}
return m_sfr[offset];
@ -1044,7 +1044,7 @@ WRITE8_MEMBER(lc8670_cpu_device::regs_w)
break;
case 0x66:
m_vtrbf[((REG_VRMAD2<<8) | REG_VRMAD1) & 0x1ff] = data;
if (!space.debugger_access() && (REG_VSEL & 0x10))
if (!machine().side_effect_disabled() && (REG_VSEL & 0x10))
{
uint16_t vrmad = (REG_VRMAD1 | (REG_VRMAD2<<8)) + 1;
REG_VRMAD1 = vrmad & 0xff;
@ -1058,7 +1058,7 @@ WRITE8_MEMBER(lc8670_cpu_device::regs_w)
// read-only registers
case 0x12: case 0x14: case 0x5c:
if(!space.debugger_access()) logerror("%s: write read-only SFR %04x = %02x\n", machine().describe_context(), offset, data);
if(!machine().side_effect_disabled()) logerror("%s: write read-only SFR %04x = %02x\n", machine().describe_context(), offset, data);
return;
}

18
src/devices/cpu/m6800/m6800.cpp
View File

@ -1341,7 +1341,7 @@ READ8_MEMBER( m6800_cpu_device::m6801_io_r )
break;
case IO_P3DATA:
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
if (m_p3csr_is3_flag_read)
{
@ -1362,7 +1362,7 @@ READ8_MEMBER( m6800_cpu_device::m6801_io_r )
data = (m_io->read_byte(M6801_PORT3) & (m_port3_ddr ^ 0xff))
| (m_port3_data & m_port3_ddr);
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
m_port3_latched = 0;
@ -1387,7 +1387,7 @@ READ8_MEMBER( m6800_cpu_device::m6801_io_r )
break;
case IO_CH:
if(!(m_pending_tcsr&TCSR_TOF) && !space.debugger_access())
if(!(m_pending_tcsr&TCSR_TOF) && !machine().side_effect_disabled())
{
m_tcsr &= ~TCSR_TOF;
MODIFIED_tcsr;
@ -1400,7 +1400,7 @@ READ8_MEMBER( m6800_cpu_device::m6801_io_r )
// HACK there should be a break here, but Coleco Adam won't boot with it present, proper fix required to the free-running counter
case IO_OCRH:
if(!(m_pending_tcsr&TCSR_OCF) && !space.debugger_access())
if(!(m_pending_tcsr&TCSR_OCF) && !machine().side_effect_disabled())
{
m_tcsr &= ~TCSR_OCF;
MODIFIED_tcsr;
@ -1409,7 +1409,7 @@ READ8_MEMBER( m6800_cpu_device::m6801_io_r )
break;
case IO_OCRL:
if(!(m_pending_tcsr&TCSR_OCF) && !space.debugger_access())
if(!(m_pending_tcsr&TCSR_OCF) && !machine().side_effect_disabled())
{
m_tcsr &= ~TCSR_OCF;
MODIFIED_tcsr;
@ -1418,7 +1418,7 @@ READ8_MEMBER( m6800_cpu_device::m6801_io_r )
break;
case IO_ICRH:
if(!(m_pending_tcsr&TCSR_ICF) && !space.debugger_access())
if(!(m_pending_tcsr&TCSR_ICF) && !machine().side_effect_disabled())
{
m_tcsr &= ~TCSR_ICF;
MODIFIED_tcsr;
@ -1431,7 +1431,7 @@ READ8_MEMBER( m6800_cpu_device::m6801_io_r )
break;
case IO_P3CSR:
if ((m_p3csr & M6801_P3CSR_IS3_FLAG) && !space.debugger_access())
if ((m_p3csr & M6801_P3CSR_IS3_FLAG) && !machine().side_effect_disabled())
{
m_p3csr_is3_flag_read = 1;
}
@ -1444,7 +1444,7 @@ READ8_MEMBER( m6800_cpu_device::m6801_io_r )
break;
case IO_TRCSR:
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
if (m_trcsr & M6800_TRCSR_TDRE)
{
@ -1466,7 +1466,7 @@ READ8_MEMBER( m6800_cpu_device::m6801_io_r )
break;
case IO_RDR:
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
if (m_trcsr_read_orfe)
{

14
src/devices/cpu/m6805/m68hc05.cpp
View File

@ -173,7 +173,7 @@ void m68hc05_device::set_port_interrupt(std::array<u8, PORT_COUNT> const &interr
READ8_MEMBER(m68hc05_device::port_r)
{
offset &= PORT_COUNT - 1;
if (!space.debugger_access() && !m_port_cb_r[offset].isnull())
if (!machine().side_effect_disabled() && !m_port_cb_r[offset].isnull())
{
u8 const newval(m_port_cb_r[offset](space, 0, ~m_port_ddr[offset] & m_port_bits[offset]) & m_port_bits[offset]);
u8 const diff(newval ^ m_port_input[offset]);
@ -257,7 +257,7 @@ WRITE8_MEMBER(m68hc05_device::tcr_w)
READ8_MEMBER(m68hc05_device::tsr_r)
{
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
u8 const events(m_tsr & ~m_tsr_seen);
if (events)
@ -276,7 +276,7 @@ READ8_MEMBER(m68hc05_device::icr_r)
// reading ICRL after reading TCR with ICF set clears ICF
u8 const low(BIT(offset, 0));
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
if (low)
{
@ -304,7 +304,7 @@ READ8_MEMBER(m68hc05_device::ocr_r)
// reading OCRL after reading TCR with OCF set clears OCF
u8 const low(BIT(offset, 0));
if (!space.debugger_access() && low && BIT(m_tsr_seen, 6))
if (!machine().side_effect_disabled() && low && BIT(m_tsr_seen, 6))
{
LOGTIMER("read OCRL, clear OCF\n");
m_tsr &= 0xbf;
@ -320,7 +320,7 @@ WRITE8_MEMBER(m68hc05_device::ocr_w)
// writing OCRL after reading TCR with OCF set clears OCF
u8 const low(BIT(offset, 0));
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
if (low)
{
@ -354,7 +354,7 @@ READ8_MEMBER(m68hc05_device::timer_r)
u8 const alt(BIT(offset, 1));
if (low)
{
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
if (m_trl_latched[alt]) LOGTIMER("read %sTRL, read sequence complete\n", alt ? "A" : "");
m_trl_latched[alt] = false;
@ -370,7 +370,7 @@ READ8_MEMBER(m68hc05_device::timer_r)
}
else
{
if (!space.debugger_access() && !m_trl_latched[alt])
if (!machine().side_effect_disabled() && !m_trl_latched[alt])
{
LOGTIMER("read %sTRH, latch %sTRL\n", alt ? "A" : "", alt ? "A" : "");
m_trl_latched[alt] = true;

4
src/devices/cpu/psx/psx.cpp
View File

@ -194,14 +194,14 @@ static const uint32_t mtc0_writemask[]=
READ32_MEMBER( psxcpu_device::berr_r )
{
if( !space.debugger_access() )
if( !machine().side_effect_disabled() )
m_berr = 1;
return 0;
}
WRITE32_MEMBER( psxcpu_device::berr_w )
{
if( !space.debugger_access() )
if( !machine().side_effect_disabled() )
m_berr = 1;
}

4
src/devices/cpu/tms32051/tms32051.cpp
View File

@ -513,7 +513,7 @@ READ16_MEMBER( tms32051_device::cpuregs_r )
return m_io->read_word(offset << 1);
default:
if (!space.debugger_access())
if (!machine().side_effect_disabled())
fatalerror("32051: cpuregs_r: unimplemented memory-mapped register %02X at %04X\n", offset, m_pc-1);
}
@ -625,7 +625,7 @@ WRITE16_MEMBER( tms32051_device::cpuregs_w )
break;
default:
if (!space.debugger_access())
if (!machine().side_effect_disabled())
fatalerror("32051: cpuregs_w: unimplemented memory-mapped register %02X, data %04X at %04X\n", offset, data, m_pc-1);
}
}

4
src/devices/cpu/tms7000/tms7000.cpp
View File

@ -506,7 +506,7 @@ READ8_MEMBER(tms7000_device::tms7000_pf_r)
{
// note: port B is write-only, reading it returns the output value as if ddr is 0xff
int port = offset / 2 - 2;
if (!space.debugger_access())
if (!machine().side_effect_disabled())
return (m_io->read_byte(port) & ~m_port_ddr[port]) | (m_port_latch[port] & m_port_ddr[port]);
break;
}
@ -516,7 +516,7 @@ READ8_MEMBER(tms7000_device::tms7000_pf_r)
return m_port_ddr[offset / 2 - 2];
default:
if (!space.debugger_access())
if (!machine().side_effect_disabled())
logerror("'%s' (%04X): tms7000_pf_r @ $%04x\n", tag(), m_pc, offset);
break;
}

4
src/devices/cpu/tms7000/tms7000.h
View File

@ -47,7 +47,7 @@ public:
tms7000_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
tms7000_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, address_map_constructor internal, uint32_t info_flags, const char *shortname, const char *source);
DECLARE_READ8_MEMBER(tms7000_unmapped_rf_r) { if (!space.debugger_access()) logerror("'%s' (%04X): unmapped_rf_r @ $%04x\n", tag(), m_pc, offset + 0x80); return 0; };
DECLARE_READ8_MEMBER(tms7000_unmapped_rf_r) { if (!machine().side_effect_disabled()) logerror("'%s' (%04X): unmapped_rf_r @ $%04x\n", tag(), m_pc, offset + 0x80); return 0; };
DECLARE_WRITE8_MEMBER(tms7000_unmapped_rf_w) { logerror("'%s' (%04X): unmapped_rf_w @ $%04x = $%02x\n", tag(), m_pc, offset + 0x80, data); };
DECLARE_READ8_MEMBER(tms7000_pf_r);
@ -317,7 +317,7 @@ public:
DECLARE_WRITE8_MEMBER(dockbus_data_w);
// access I/O port E if databus is disabled
DECLARE_READ8_MEMBER(e_bus_data_r) { return (space.debugger_access()) ? 0xff : ((m_control & 0x20) ? 0xff : m_io->read_byte(TMS7000_PORTE)); }
DECLARE_READ8_MEMBER(e_bus_data_r) { return machine().side_effect_disabled() ? 0xff : ((m_control & 0x20) ? 0xff : m_io->read_byte(TMS7000_PORTE)); }
DECLARE_WRITE8_MEMBER(e_bus_data_w) { if (~m_control & 0x20) m_io->write_byte(TMS7000_PORTE, data); }
protected:

6
src/devices/cpu/tms9900/tms9900.cpp
View File

@ -420,9 +420,8 @@ void tms99xx_device::state_string_export(const device_state_entry &entry, std::s
uint16_t tms99xx_device::read_workspace_register_debug(int reg)
{
int temp = m_icount;
m_prgspace->set_debugger_access(true);
auto dis = machine().disable_side_effect();
uint16_t value = m_prgspace->read_word((WP+(reg<<1)) & m_prgaddr_mask & 0xfffe);
m_prgspace->set_debugger_access(false);
m_icount = temp;
return value;
}
@ -430,9 +429,8 @@ uint16_t tms99xx_device::read_workspace_register_debug(int reg)
void tms99xx_device::write_workspace_register_debug(int reg, uint16_t data)
{
int temp = m_icount;
m_prgspace->set_debugger_access(true);
auto dis = machine().disable_side_effect();
m_prgspace->write_word((WP+(reg<<1)) & m_prgaddr_mask & 0xfffe, data);
m_prgspace->set_debugger_access(false);
m_icount = temp;
}

6
src/devices/cpu/tms9900/tms9995.cpp
View File

@ -473,10 +473,9 @@ uint16_t tms9995_device::read_workspace_register_debug(int reg)
}
else
{
m_prgspace->set_debugger_access(true);
auto dis = machine().disable_side_effect();
value = (m_prgspace->read_byte(addrb) << 8) & 0xff00;
value |= m_prgspace->read_byte(addrb+1);
m_prgspace->set_debugger_access(false);
}
m_icount = temp;
return value;
@ -494,10 +493,9 @@ void tms9995_device::write_workspace_register_debug(int reg, uint16_t data)
}
else
{
m_prgspace->set_debugger_access(true);
auto dis = machine().disable_side_effect();
m_prgspace->write_byte(addrb, (data >> 8) & 0xff);
m_prgspace->write_byte(addrb+1, data & 0xff);
m_prgspace->set_debugger_access(false);
}
m_icount = temp;
}

2
src/devices/machine/6522via.cpp
View File

@ -551,7 +551,7 @@ void via6522_device::output_pb()
READ8_MEMBER( via6522_device::read )
{
int val = 0;
if (space.debugger_access())
if (machine().side_effect_disabled())
return 0;
offset &= 0xf;

2
src/devices/machine/6532riot.cpp
View File

@ -233,7 +233,7 @@ void riot6532_device::reg_w(uint8_t offset, uint8_t data)
READ8_MEMBER( riot6532_device::read )
{
return reg_r(offset, space.debugger_access());
return reg_r(offset, machine().side_effect_disabled());
}
uint8_t riot6532_device::reg_r(uint8_t offset, bool debugger_access)

4
src/devices/machine/autoconfig.cpp
View File

@ -124,7 +124,7 @@ READ16_MEMBER( amiga_autoconfig::autoconfig_read )
{
uint16_t data = m_cfg[offset] | 0x0fff;
if (VERBOSE && !space.debugger_access())
if (VERBOSE && !space.machine().side_effect_disabled())
space.device().logerror("autoconfig_read %04x @ %02x [mask = %04x]\n", data, offset, mem_mask);
return data;
@ -132,7 +132,7 @@ READ16_MEMBER( amiga_autoconfig::autoconfig_read )
WRITE16_MEMBER( amiga_autoconfig::autoconfig_write )
{
if (VERBOSE && !space.debugger_access())
if (VERBOSE && !space.machine().side_effect_disabled())
space.device().logerror("autoconfig_write %04x @ %02x [mask = %04x]\n", data, offset, mem_mask);
switch (offset)

8
src/devices/machine/bankdev.cpp
View File

@ -36,49 +36,41 @@ ADDRESS_MAP_END
WRITE8_MEMBER(address_map_bank_device::write8)
{
m_program->set_debugger_access(space.debugger_access());
m_program->write_byte(m_offset + offset, data);
}
WRITE16_MEMBER(address_map_bank_device::write16)
{
m_program->set_debugger_access(space.debugger_access());
m_program->write_word(m_offset + (offset * 2), data, mem_mask);
}
WRITE32_MEMBER(address_map_bank_device::write32)
{
m_program->set_debugger_access(space.debugger_access());
m_program->write_dword(m_offset + (offset * 4), data, mem_mask);
}
WRITE64_MEMBER(address_map_bank_device::write64)
{
m_program->set_debugger_access(space.debugger_access());
m_program->write_qword(m_offset + (offset * 8), data, mem_mask);
}
READ8_MEMBER(address_map_bank_device::read8)
{
m_program->set_debugger_access(space.debugger_access());
return m_program->read_byte(m_offset + offset);
}
READ16_MEMBER(address_map_bank_device::read16)
{
m_program->set_debugger_access(space.debugger_access());
return m_program->read_word(m_offset + (offset * 2), mem_mask);
}
READ32_MEMBER(address_map_bank_device::read32)
{
m_program->set_debugger_access(space.debugger_access());
return m_program->read_dword(m_offset + (offset * 4), mem_mask);
}
READ64_MEMBER(address_map_bank_device::read64)
{
m_program->set_debugger_access(space.debugger_access());
return m_program->read_qword(m_offset + (offset * 8), mem_mask);
}

2
src/devices/machine/cdp1879.cpp
View File

@ -116,7 +116,7 @@ void cdp1879_device::update_rtc()
READ8_MEMBER(cdp1879_device::read)
{
if (offset == R_CTL_IRQSTATUS && !space.debugger_access())
if (offset == R_CTL_IRQSTATUS && !machine().side_effect_disabled())
{
// reading the IRQ status clears IRQ line and IRQ status
uint8_t data = m_regs[offset];

4
src/devices/machine/mb8421.cpp
View File

@ -69,7 +69,7 @@ READ8_MEMBER(mb8421_device::left_r)
{
offset &= 0x7ff;
if (offset == 0x7fe && !space.debugger_access())
if (offset == 0x7fe && !machine().side_effect_disabled())
m_intl_handler(0);
return m_ram[offset];
@ -88,7 +88,7 @@ READ8_MEMBER(mb8421_device::right_r)
{
offset &= 0x7ff;
if (offset == 0x7ff && !space.debugger_access())
if (offset == 0x7ff && !machine().side_effect_disabled())
m_intr_handler(0);
return m_ram[offset];

2
src/devices/machine/mm58167.cpp
View File

@ -184,7 +184,7 @@ READ8_MEMBER(mm58167_device::read)
{
// printf("read reg %x = %02x\n", offset, m_regs[offset]);
if (offset == R_CTL_IRQSTATUS && !space.debugger_access())
if (offset == R_CTL_IRQSTATUS && !machine().side_effect_disabled())
{
// reading the IRQ status clears IRQ line and IRQ status
uint8_t data = m_regs[offset];

2
src/devices/machine/mos6526.cpp
View File

@ -802,7 +802,7 @@ void mos6526_device::execute_run()
READ8_MEMBER( mos6526_device::read )
{
if (space.debugger_access())
if (machine().side_effect_disabled())
return 0xff;
uint8_t data = 0;

6
src/devices/machine/mos6530n.cpp
View File

@ -634,7 +634,7 @@ WRITE8_MEMBER( mos6530_base_t::pb_ddr_w )
READ8_MEMBER( mos6530_base_t::timer_off_r )
{
if (space.debugger_access())
if (machine().side_effect_disabled())
return 0;
return timer_r(false);
@ -642,7 +642,7 @@ READ8_MEMBER( mos6530_base_t::timer_off_r )
READ8_MEMBER( mos6530_base_t::timer_on_r )
{
if (space.debugger_access())
if (machine().side_effect_disabled())
return 0;
return timer_r(true);
@ -679,7 +679,7 @@ READ8_MEMBER( mos6530_base_t::irq_r )
{
uint8_t data = get_irq_flags();
if (!space.debugger_access()) {
if (!machine().side_effect_disabled()) {
if (m_irq_edge) {
m_irq_edge = false;
update_irq();

2
src/devices/machine/mos6551.cpp
View File

@ -378,7 +378,7 @@ void mos6551_device::write_command(uint8_t data)
READ8_MEMBER( mos6551_device::read )
{
if (space.debugger_access())
if (machine().side_effect_disabled())
return 0xff;
switch (offset & 0x03)

2
src/devices/machine/s2636.cpp
View File

@ -416,7 +416,7 @@ READ8_MEMBER( s2636_device::read_data )
{
case REG_COL_BG_CMPL:
case REG_VBL_COL_OBJ:
if (!space.debugger_access())
if (!machine().side_effect_disabled())
m_registers[offset] = 0x00; // collision/completion/VRESET flags reset on read
break;
}

2
src/devices/machine/smpc.cpp
View File

@ -877,7 +877,7 @@ READ8_MEMBER( saturn_state::saturn_SMPC_r )
{
uint8_t cur_ddr;
if (((m_ctrl1 && m_ctrl1->read_id(0) != 0x02) || (m_ctrl2 && m_ctrl2->read_id(0) != 0x02)) && !(space.debugger_access()))
if (((m_ctrl1 && m_ctrl1->read_id(0) != 0x02) || (m_ctrl2 && m_ctrl2->read_id(0) != 0x02)) && !(machine().side_effect_disabled()))
{
popmessage("Warning: read with SH-2 direct mode with a non-pad device");
return 0;

4
src/devices/sound/tms5220.cpp
View File

@ -2020,7 +2020,7 @@ WRITE8_MEMBER( tms5220_device::combined_rsq_wsq_w )
WRITE8_MEMBER( tms5220_device::data_w )
{
// prevent debugger from changing the internal state
if (space.debugger_access()) return;
if (machine().side_effect_disabled()) return;
#ifdef DEBUG_RS_WS
logerror("tms5220_data_w: data %02x\n", data);
@ -2053,7 +2053,7 @@ WRITE8_MEMBER( tms5220_device::data_w )
READ8_MEMBER( tms5220_device::status_r )
{
// prevent debugger from changing the internal state
if (space.debugger_access()) return 0;
if (machine().side_effect_disabled()) return 0;
if (!m_true_timing)
{

4
src/devices/video/315_5124.cpp
View File

@ -565,7 +565,7 @@ READ8_MEMBER( sega315_5124_device::vram_read )
/* Return read buffer contents */
temp = m_buffer;
if ( !space.debugger_access() )
if ( !machine().side_effect_disabled() )
{
/* Load read buffer */
m_buffer = this->space().read_byte(m_addr & 0x3fff);
@ -632,7 +632,7 @@ READ8_MEMBER( sega315_5124_device::register_read )
check_pending_flags();
temp = m_status;
if ( !space.debugger_access() )
if ( !machine().side_effect_disabled() )
{
/* Clear pending write flag */
m_pending_reg_write = 0;

2
src/devices/video/clgd542x.cpp
View File

@ -1268,7 +1268,7 @@ READ8_MEMBER(cirrus_gd5428_device::mem_r)
if(vga.sequencer.data[4] & 4)
{
int data;
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
vga.gc.latch[0]=vga.memory[(offset+addr) % vga.svga_intf.vram_size];
vga.gc.latch[1]=vga.memory[((offset+addr)+0x10000) % vga.svga_intf.vram_size];

8
src/devices/video/gb_lcd.cpp
View File

@ -2886,7 +2886,7 @@ void dmg_ppu_device::lcd_switch_on(uint8_t new_data)
READ8_MEMBER(dmg_ppu_device::vram_r)
{
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
update_state();
LOG(("vram_r: offset=0x%04x\n", offset));
@ -2908,7 +2908,7 @@ WRITE8_MEMBER(dmg_ppu_device::vram_w)
READ8_MEMBER(dmg_ppu_device::oam_r)
{
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
update_state();
LOG(("oam_r: offset=0x%02x\n", offset));
@ -2931,7 +2931,7 @@ WRITE8_MEMBER(dmg_ppu_device::oam_w)
READ8_MEMBER(dmg_ppu_device::video_r)
{
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
update_state();
if (offset == 1) LOG(("STAT read\n"));
@ -3203,7 +3203,7 @@ WRITE8_MEMBER(dmg_ppu_device::video_w)
READ8_MEMBER(cgb_ppu_device::video_r)
{
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
update_state();
if (offset == 1) LOG(("STAT read\n"));

6
src/devices/video/hd44780.cpp
View File

@ -487,7 +487,7 @@ READ8_MEMBER(hd44780_device::control_read)
{
if (m_data_len == 4)
{
if (!space.debugger_access())
if (!machine().side_effect_disabled())
update_nibble(0, 1);
if (m_nibble)
@ -549,7 +549,7 @@ READ8_MEMBER(hd44780_device::data_read)
if (m_data_len == 4)
{
if (!space.debugger_access())
if (!machine().side_effect_disabled())
update_nibble(1, 1);
if (m_nibble)
@ -558,7 +558,7 @@ READ8_MEMBER(hd44780_device::data_read)
data = (data << 4) & 0xf0;
}
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
update_ac(m_direction);
set_busy_flag(41);

2
src/devices/video/pc_vga.cpp
View File

@ -1988,7 +1988,7 @@ READ8_MEMBER(vga_device::mem_r)
if(vga.sequencer.data[4] & 4)
{
int data;
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
vga.gc.latch[0]=vga.memory[(offset)];
vga.gc.latch[1]=vga.memory[(offset)+0x10000];

2
src/devices/video/stvvdp1.cpp
View File

@ -175,7 +175,7 @@ READ16_MEMBER( saturn_state::saturn_vdp1_regs_r )
return modr;
default:
if(!space.debugger_access())
if(!machine().side_effect_disabled())
printf ("cpu %s (PC=%08X) VDP1: Read from Registers, Offset %04x\n", space.device().tag(), space.device().safe_pc(), offset*2);
break;
}

8
src/devices/video/stvvdp2.cpp
View File

@ -5721,7 +5721,7 @@ READ16_MEMBER ( saturn_state::saturn_vdp2_regs_r )
/* latch h/v signals through HV latch*/
if(!STV_VDP2_EXLTEN)
{
if(!space.debugger_access())
if(!machine().side_effect_disabled())
{
m_vdp2.h_count = get_hcounter();
m_vdp2.v_count = get_vcounter();
@ -5748,7 +5748,7 @@ READ16_MEMBER ( saturn_state::saturn_vdp2_regs_r )
m_vdp2_regs[offset] |= 1 << 3;
/* HV latches clears if this register is read */
if(!space.debugger_access())
if(!machine().side_effect_disabled())
{
m_vdp2.exltfg &= ~1;
m_vdp2.exsyfg &= ~1;
@ -5762,7 +5762,7 @@ READ16_MEMBER ( saturn_state::saturn_vdp2_regs_r )
/* Games basically r/w the entire VDP2 register area when this is tripped. (example: Silhouette Mirage)
Disable log for the time being. */
//if(!space.debugger_access())
//if(!machine().side_effect_disabled())
// printf("Warning: VDP2 version read\n");
break;
}
@ -5782,7 +5782,7 @@ READ16_MEMBER ( saturn_state::saturn_vdp2_regs_r )
}
default:
//if(!space.debugger_access())
//if(!machine().side_effect_disabled())
// printf("VDP2: read from register %08x %08x\n",offset*4,mem_mask);
break;
}

2
src/devices/video/t6a04.cpp
View File

@ -229,7 +229,7 @@ READ8_MEMBER(t6a04_device::data_read)
output_reg = ((((*ti82_video)<<8)+ti82_video[1])>>(10-pos_bit));
}
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
m_output_reg = output_reg;

8
src/devices/video/tms9928a.cpp
View File

@ -135,7 +135,7 @@ WRITE8_MEMBER( tms9928a_device::write )
READ8_MEMBER( tms9928a_device::vram_read )
{
// prevent debugger from changing the address base
if (space.debugger_access()) return 0;
if (machine().side_effect_disabled()) return 0;
uint8_t data = m_ReadAhead;
@ -150,7 +150,7 @@ READ8_MEMBER( tms9928a_device::vram_read )
WRITE8_MEMBER( tms9928a_device::vram_write )
{
// prevent debugger from changing the address base
if (space.debugger_access()) return;
if (machine().side_effect_disabled()) return;
m_vram_space->write_byte(m_Addr, data);
m_Addr = (m_Addr + 1) & (m_vram_size - 1);
@ -162,7 +162,7 @@ WRITE8_MEMBER( tms9928a_device::vram_write )
READ8_MEMBER( tms9928a_device::register_read )
{
// prevent debugger from changing the internal state
if (space.debugger_access()) return 0;
if (machine().side_effect_disabled()) return 0;
uint8_t data = m_StatusReg;
@ -290,7 +290,7 @@ void tms9928a_device::change_register(uint8_t reg, uint8_t val)
WRITE8_MEMBER( tms9928a_device::register_write )
{
// prevent debugger from changing the internal state
if (space.debugger_access()) return;
if (machine().side_effect_disabled()) return;
if (m_latch)
{

122
src/emu/debug/debugcpu.cpp
View File

@ -98,8 +98,8 @@ void debugger_cpu::configure_memory(symbol_table &table)
table.configure_memory(
&m_machine,
std::bind(&debugger_cpu::expression_validate, this, _1, _2, _3),
std::bind(&debugger_cpu::expression_read_memory, this, _1, _2, _3, _4, _5),
std::bind(&debugger_cpu::expression_write_memory, this, _1, _2, _3, _4, _5, _6));
std::bind(&debugger_cpu::expression_read_memory, this, _1, _2, _3, _4, _5, _6),
std::bind(&debugger_cpu::expression_write_memory, this, _1, _2, _3, _4, _5, _6, _7));
}
/*-------------------------------------------------
@ -370,10 +370,6 @@ u8 debugger_cpu::read_byte(address_space &space, offs_t address, bool apply_tran
/* mask against the logical byte mask */
address &= space.logbytemask();
/* all accesses from this point on are for the debugger */
m_debugger_access = true;
space.set_debugger_access(true);
/* translate if necessary; if not mapped, return 0xff */
u8 result;
if (apply_translation && !memory.translate(space.spacenum(), TRANSLATE_READ_DEBUG, address))
@ -385,9 +381,6 @@ u8 debugger_cpu::read_byte(address_space &space, offs_t address, bool apply_tran
result = space.read_byte(address);
}
/* no longer accessing via the debugger */
m_debugger_access = false;
space.set_debugger_access(false);
return result;
}
@ -418,10 +411,6 @@ u16 debugger_cpu::read_word(address_space &space, offs_t address, bool apply_tra
{ /* otherwise, this proceeds like the byte case */
device_memory_interface &memory = space.device().memory();
/* all accesses from this point on are for the debugger */
m_debugger_access = true;
space.set_debugger_access(true);
/* translate if necessary; if not mapped, return 0xffff */
if (apply_translation && !memory.translate(space.spacenum(), TRANSLATE_READ_DEBUG, address))
{
@ -431,10 +420,6 @@ u16 debugger_cpu::read_word(address_space &space, offs_t address, bool apply_tra
{ /* otherwise, call the byte reading function for the translated address */
result = space.read_word(address);
}
/* no longer accessing via the debugger */
m_debugger_access = false;
space.set_debugger_access(false);
}
return result;
@ -467,10 +452,6 @@ u32 debugger_cpu::read_dword(address_space &space, offs_t address, bool apply_tr
{ /* otherwise, this proceeds like the byte case */
device_memory_interface &memory = space.device().memory();
/* all accesses from this point on are for the debugger */
m_debugger_access = true;
space.set_debugger_access(true);
if (apply_translation && !memory.translate(space.spacenum(), TRANSLATE_READ_DEBUG, address))
{ /* translate if necessary; if not mapped, return 0xffffffff */
result = 0xffffffff;
@ -479,10 +460,6 @@ u32 debugger_cpu::read_dword(address_space &space, offs_t address, bool apply_tr
{ /* otherwise, call the byte reading function for the translated address */
result = space.read_dword(address);
}
/* no longer accessing via the debugger */
m_debugger_access = false;
space.set_debugger_access(false);
}
return result;
@ -515,10 +492,6 @@ u64 debugger_cpu::read_qword(address_space &space, offs_t address, bool apply_tr
{ /* otherwise, this proceeds like the byte case */
device_memory_interface &memory = space.device().memory();
/* all accesses from this point on are for the debugger */
m_debugger_access = true;
space.set_debugger_access(true);
/* translate if necessary; if not mapped, return 0xffffffffffffffff */
if (apply_translation && !memory.translate(space.spacenum(), TRANSLATE_READ_DEBUG, address))
{
@ -528,10 +501,6 @@ u64 debugger_cpu::read_qword(address_space &space, offs_t address, bool apply_tr
{ /* otherwise, call the byte reading function for the translated address */
result = space.read_qword(address);
}
/* no longer accessing via the debugger */
m_debugger_access = false;
space.set_debugger_access(false);
}
return result;
@ -569,10 +538,6 @@ void debugger_cpu::write_byte(address_space &space, offs_t address, u8 data, boo
/* mask against the logical byte mask */
address &= space.logbytemask();
/* all accesses from this point on are for the debugger */
m_debugger_access = true;
space.set_debugger_access(true);
/* translate if necessary; if not mapped, we're done */
if (apply_translation && !memory.translate(space.spacenum(), TRANSLATE_WRITE_DEBUG, address))
;
@ -581,10 +546,6 @@ void debugger_cpu::write_byte(address_space &space, offs_t address, u8 data, boo
else
space.write_byte(address, data);
/* no longer accessing via the debugger */
m_debugger_access = false;
space.set_debugger_access(false);
m_memory_modified = true;
}
@ -619,10 +580,6 @@ void debugger_cpu::write_word(address_space &space, offs_t address, u16 data, bo
{
device_memory_interface &memory = space.device().memory();
/* all accesses from this point on are for the debugger */
m_debugger_access = true;
space.set_debugger_access(true);
/* translate if necessary; if not mapped, we're done */
if (apply_translation && !memory.translate(space.spacenum(), TRANSLATE_WRITE_DEBUG, address))
;
@ -631,10 +588,6 @@ void debugger_cpu::write_word(address_space &space, offs_t address, u16 data, bo
else
space.write_word(address, data);
/* no longer accessing via the debugger */
m_debugger_access = false;
space.set_debugger_access(false);
m_memory_modified = true;
}
}
@ -670,9 +623,6 @@ void debugger_cpu::write_dword(address_space &space, offs_t address, u32 data, b
{
device_memory_interface &memory = space.device().memory();
/* all accesses from this point on are for the debugger */
space.set_debugger_access(m_debugger_access = true);
/* translate if necessary; if not mapped, we're done */
if (apply_translation && !memory.translate(space.spacenum(), TRANSLATE_WRITE_DEBUG, address))
;
@ -681,10 +631,6 @@ void debugger_cpu::write_dword(address_space &space, offs_t address, u32 data, b
else
space.write_dword(address, data);
/* no longer accessing via the debugger */
m_debugger_access = false;
space.set_debugger_access(false);
m_memory_modified = true;
}
}
@ -720,10 +666,6 @@ void debugger_cpu::write_qword(address_space &space, offs_t address, u64 data, b
{
device_memory_interface &memory = space.device().memory();
/* all accesses from this point on are for the debugger */
m_debugger_access = true;
space.set_debugger_access(true);
/* translate if necessary; if not mapped, we're done */
if (apply_translation && !memory.translate(space.spacenum(), TRANSLATE_WRITE_DEBUG, address))
;
@ -732,10 +674,6 @@ void debugger_cpu::write_qword(address_space &space, offs_t address, u64 data, b
else
space.write_qword(address, data);
/* no longer accessing via the debugger */
m_debugger_access = false;
space.set_debugger_access(false);
m_memory_modified = true;
}
}
@ -772,9 +710,6 @@ u64 debugger_cpu::read_opcode(address_space &space, offs_t address, int size)
/* keep in logical range */
address &= space.logbytemask();
m_debugger_access = true;
space.set_debugger_access(true);
/* if we're bigger than the address bus, break into smaller pieces */
if (size > space.data_width() / 8)
{
@ -848,13 +783,6 @@ u64 debugger_cpu::read_opcode(address_space &space, offs_t address, int size)
fatalerror("read_opcode: unknown type = %d\n", space.data_width() / 8 * 10 + size);
}
/* turn on debugger access */
if (!m_debugger_access)
{
m_debugger_access = true;
space.set_debugger_access(true);
}
/* switch off the size and handle unaligned accesses */
switch (size)
{
@ -902,10 +830,6 @@ u64 debugger_cpu::read_opcode(address_space &space, offs_t address, int size)
break;
}
/* no longer accessing via the debugger */
m_debugger_access = false;
space.set_debugger_access(false);
return result;
}
@ -1005,7 +929,7 @@ device_t* debugger_cpu::expression_get_device(const char *tag)
space
-------------------------------------------------*/
u64 debugger_cpu::expression_read_memory(void *param, const char *name, expression_space spacenum, u32 address, int size)
u64 debugger_cpu::expression_read_memory(void *param, const char *name, expression_space spacenum, u32 address, int size, bool with_se)
{
switch (spacenum)
{
@ -1027,7 +951,11 @@ u64 debugger_cpu::expression_read_memory(void *param, const char *name, expressi
if (memory->has_space(AS_PROGRAM + (spacenum - EXPSPACE_PROGRAM_LOGICAL)))
{
address_space &space = memory->space(AS_PROGRAM + (spacenum - EXPSPACE_PROGRAM_LOGICAL));
return read_memory(space, space.address_to_byte(address), size, true);
if (!with_se) {
auto dis = m_machine.disable_side_effect();
return read_memory(space, space.address_to_byte(address), size, true);
} else
return read_memory(space, space.address_to_byte(address), size, true);
}
break;
}
@ -1050,7 +978,11 @@ u64 debugger_cpu::expression_read_memory(void *param, const char *name, expressi
if (memory->has_space(AS_PROGRAM + (spacenum - EXPSPACE_PROGRAM_PHYSICAL)))
{
address_space &space = memory->space(AS_PROGRAM + (spacenum - EXPSPACE_PROGRAM_PHYSICAL));
return read_memory(space, space.address_to_byte(address), size, false);
if (!with_se) {
auto dis = m_machine.disable_side_effect();
return read_memory(space, space.address_to_byte(address), size, false);
} else
return read_memory(space, space.address_to_byte(address), size, false);
}
break;
}
@ -1068,7 +1000,11 @@ u64 debugger_cpu::expression_read_memory(void *param, const char *name, expressi
device = get_visible_cpu();
memory = &device->memory();
}
return expression_read_program_direct(memory->space(AS_PROGRAM), (spacenum == EXPSPACE_OPCODE), address, size);
if (!with_se) {
auto dis = m_machine.disable_side_effect();
return expression_read_program_direct(memory->space(AS_PROGRAM), (spacenum == EXPSPACE_OPCODE), address, size);
} else
return expression_read_program_direct(memory->space(AS_PROGRAM), (spacenum == EXPSPACE_OPCODE), address, size);
break;
}
@ -1192,7 +1128,7 @@ u64 debugger_cpu::expression_read_memory_region(const char *rgntag, offs_t addre
space
-------------------------------------------------*/
void debugger_cpu::expression_write_memory(void *param, const char *name, expression_space spacenum, u32 address, int size, u64 data)
void debugger_cpu::expression_write_memory(void *param, const char *name, expression_space spacenum, u32 address, int size, u64 data, bool with_se)
{
device_t *device = nullptr;
device_memory_interface *memory;
@ -1213,7 +1149,11 @@ void debugger_cpu::expression_write_memory(void *param, const char *name, expres
if (memory->has_space(AS_PROGRAM + (spacenum - EXPSPACE_PROGRAM_LOGICAL)))
{
address_space &space = memory->space(AS_PROGRAM + (spacenum - EXPSPACE_PROGRAM_LOGICAL));
write_memory(space, space.address_to_byte(address), data, size, true);
if (!with_se) {
auto dis = m_machine.disable_side_effect();
write_memory(space, space.address_to_byte(address), data, size, true);
} else
write_memory(space, space.address_to_byte(address), data, size, true);
}
break;
@ -1231,7 +1171,11 @@ void debugger_cpu::expression_write_memory(void *param, const char *name, expres
if (memory->has_space(AS_PROGRAM + (spacenum - EXPSPACE_PROGRAM_PHYSICAL)))
{
address_space &space = memory->space(AS_PROGRAM + (spacenum - EXPSPACE_PROGRAM_PHYSICAL));
write_memory(space, space.address_to_byte(address), data, size, false);
if (!with_se) {
auto dis = m_machine.disable_side_effect();
write_memory(space, space.address_to_byte(address), data, size, false);
} else
write_memory(space, space.address_to_byte(address), data, size, false);
}
break;
@ -1244,7 +1188,11 @@ void debugger_cpu::expression_write_memory(void *param, const char *name, expres
device = get_visible_cpu();
memory = &device->memory();
}
expression_write_program_direct(memory->space(AS_PROGRAM), (spacenum == EXPSPACE_OPCODE), address, size, data);
if (!with_se) {
auto dis = m_machine.disable_side_effect();
expression_write_program_direct(memory->space(AS_PROGRAM), (spacenum == EXPSPACE_OPCODE), address, size, data);
} else
expression_write_program_direct(memory->space(AS_PROGRAM), (spacenum == EXPSPACE_OPCODE), address, size, data);
break;
case EXPSPACE_REGION:
@ -2859,7 +2807,7 @@ void device_debug::watchpoint_check(address_space& space, int type, offs_t addre
void debugger_cpu::watchpoint_check(address_space& space, int type, offs_t address, u64 value_to_write, u64 mem_mask, device_debug::watchpoint** wplist)
{
// if we're within debugger code, don't stop
if (m_within_instruction_hook || m_debugger_access)
if (m_within_instruction_hook || m_machine.side_effect_disabled())
return;
m_within_instruction_hook = true;

5
src/emu/debug/debugcpu.h
View File

@ -577,10 +577,10 @@ private:
static const size_t NUM_TEMP_VARIABLES;
/* expression handlers */
u64 expression_read_memory(void *param, const char *name, expression_space space, u32 address, int size);
u64 expression_read_memory(void *param, const char *name, expression_space space, u32 address, int size, bool with_se);
u64 expression_read_program_direct(address_space &space, int opcode, offs_t address, int size);
u64 expression_read_memory_region(const char *rgntag, offs_t address, int size);
void expression_write_memory(void *param, const char *name, expression_space space, u32 address, int size, u64 data);
void expression_write_memory(void *param, const char *name, expression_space space, u32 address, int size, u64 data, bool with_se);
void expression_write_program_direct(address_space &space, int opcode, offs_t address, int size, u64 data);
void expression_write_memory_region(const char *rgntag, offs_t address, int size, u64 data);
expression_error::error_code expression_validate(void *param, const char *name, expression_space space);
@ -608,7 +608,6 @@ private:
bool m_within_instruction_hook;
bool m_vblank_occurred;
bool m_memory_modified;
bool m_debugger_access;
int m_execution_state;
device_t * m_stop_when_not_device; // stop execution when the device ceases to be this

2
src/emu/debug/dvdisasm.cpp
View File

@ -335,6 +335,8 @@ void debug_view_disasm::generate_bytes(offs_t pcbyte, int numbytes, int minbytes
bool debug_view_disasm::recompute(offs_t pc, int startline, int lines)
{
auto dis = machine().disable_side_effect();
util::ovectorstream buffer;
bool changed = false;
const debug_view_disasm_source &source = downcast<const debug_view_disasm_source &>(*m_source);

4
src/emu/debug/dvmemory.cpp
View File

@ -741,6 +741,8 @@ bool debug_view_memory::read(u8 size, offs_t offs, u64 &data)
{
offs_t dummyaddr = offs;
auto dis = machine().disable_side_effect();
bool ismapped = m_no_translation ? true : source.m_memintf->translate(source.m_space->spacenum(), TRANSLATE_READ_DEBUG, dummyaddr);
data = ~u64(0);
if (ismapped)
@ -817,6 +819,8 @@ void debug_view_memory::write(u8 size, offs_t offs, u64 data)
// if no raw data, just use the standard debug routines
if (source.m_space != nullptr)
{
auto dis = machine().disable_side_effect();
switch (size)
{
case 1: machine().debugger().cpu().write_byte(*source.m_space, offs, data, !m_no_translation); break;

26
src/emu/debug/express.cpp
View File

@ -517,7 +517,7 @@ expression_error::error_code symbol_table::memory_valid(const char *name, expres
// memory_value - return a value read from memory
//-------------------------------------------------
u64 symbol_table::memory_value(const char *name, expression_space space, u32 offset, int size)
u64 symbol_table::memory_value(const char *name, expression_space space, u32 offset, int size, bool with_se)
{
// walk up the table hierarchy to find the owner
for (symbol_table *symtable = this; symtable != nullptr; symtable = symtable->m_parent)
@ -525,7 +525,7 @@ u64 symbol_table::memory_value(const char *name, expression_space space, u32 off
{
expression_error::error_code err = symtable->m_memory_valid(symtable->m_memory_param, name, space);
if (err != expression_error::NO_SUCH_MEMORY_SPACE && symtable->m_memory_read != nullptr)
return symtable->m_memory_read(symtable->m_memory_param, name, space, offset, size);
return symtable->m_memory_read(symtable->m_memory_param, name, space, offset, size, with_se);
return 0;
}
return 0;
@ -536,7 +536,7 @@ u64 symbol_table::memory_value(const char *name, expression_space space, u32 off
// set_memory_value - write a value to memory
//-------------------------------------------------
void symbol_table::set_memory_value(const char *name, expression_space space, u32 offset, int size, u64 value)
void symbol_table::set_memory_value(const char *name, expression_space space, u32 offset, int size, u64 value, bool with_se)
{
// walk up the table hierarchy to find the owner
for (symbol_table *symtable = this; symtable != nullptr; symtable = symtable->m_parent)
@ -544,7 +544,7 @@ void symbol_table::set_memory_value(const char *name, expression_space space, u3
{
expression_error::error_code err = symtable->m_memory_valid(symtable->m_memory_param, name, space);
if (err != expression_error::NO_SUCH_MEMORY_SPACE && symtable->m_memory_write != nullptr)
symtable->m_memory_write(symtable->m_memory_param, name, space, offset, size, value);
symtable->m_memory_write(symtable->m_memory_param, name, space, offset, size, value, with_se);
return;
}
}
@ -684,7 +684,7 @@ void parsed_expression::print_tokens(FILE *out)
case TVL_ASSIGNBXOR: fprintf(out, "^=\n"); break;
case TVL_ASSIGNBOR: fprintf(out, "|=\n"); break;
case TVL_COMMA: fprintf(out, ",\n"); break;
case TVL_MEMORYAT: fprintf(out, "mem@\n"); break;
case TVL_MEMORYAT: fprintf(out, token.memory_size_effect() ? "mem!\n" : "mem@\n");break;
case TVL_EXECUTEFUNC: fprintf(out, "execute\n"); break;
default: fprintf(out, "INVALID OPERATOR\n"); break;
}
@ -874,10 +874,11 @@ void parsed_expression::parse_symbol_or_number(parse_token &token, const char *&
}
// check for memory @ operators
if (string[0] == '@')
if (string[0] == '@' || string[0] == '!')
{
bool with_se = string[0] == '!';
string += 1;
return parse_memory_operator(token, buffer.c_str());
return parse_memory_operator(token, buffer.c_str(), with_se);
}
// empty string is automatically invalid
@ -1097,7 +1098,7 @@ void parsed_expression::parse_quoted_string(parse_token &token, const char *&str
// forms of memory operators
//-------------------------------------------------
void parsed_expression::parse_memory_operator(parse_token &token, const char *string)
void parsed_expression::parse_memory_operator(parse_token &token, const char *string, bool with_se)
{
// if there is a '.', it means we have a name
const char *startstring = string;
@ -1174,7 +1175,7 @@ void parsed_expression::parse_memory_operator(parse_token &token, const char *st
}
// configure the token
token.configure_operator(TVL_MEMORYAT, 2).set_memory_size(memsize).set_memory_space(memspace).set_memory_source(namestring);
token.configure_operator(TVL_MEMORYAT, 2).set_memory_size(memsize).set_memory_space(memspace).set_memory_source(namestring).set_memory_side_effect(with_se);
}
@ -1717,8 +1718,9 @@ u64 parsed_expression::parse_token::get_lval_value(symbol_table *table)
return m_symbol->value();
// or get the value from the memory callbacks
else if (is_memory() && table != nullptr)
return table->memory_value(m_string, memory_space(), address(), 1 << memory_size());
else if (is_memory() && table != nullptr) {
return table->memory_value(m_string, memory_space(), address(), 1 << memory_size(), memory_side_effect());
}
return 0;
}
@ -1737,7 +1739,7 @@ inline void parsed_expression::parse_token::set_lval_value(symbol_table *table,
// or set the value via the memory callbacks
else if (is_memory() && table != nullptr)
table->set_memory_value(m_string, memory_space(), address(), 1 << memory_size(), value);
table->set_memory_value(m_string, memory_space(), address(), 1 << memory_size(), value, memory_side_effect());
}

18
src/emu/debug/express.h
View File

@ -161,8 +161,8 @@ public:
// callback functions for memory reads/writes
typedef std::function<expression_error::error_code(void *cbparam, const char *name, expression_space space)> valid_func;
typedef std::function<u64(void *cbparam, const char *name, expression_space space, u32 offset, int size)> read_func;
typedef std::function<void(void *cbparam, const char *name, expression_space space, u32 offset, int size, u64 value)> write_func;
typedef std::function<u64(void *cbparam, const char *name, expression_space space, u32 offset, int size, bool with_se)> read_func;
typedef std::function<void(void *cbparam, const char *name, expression_space space, u32 offset, int size, u64 value, bool with_se)> write_func;
enum read_write
{
@ -195,8 +195,8 @@ public:
// memory accessors
expression_error::error_code memory_valid(const char *name, expression_space space);
u64 memory_value(const char *name, expression_space space, u32 offset, int size);
void set_memory_value(const char *name, expression_space space, u32 offset, int size, u64 value);
u64 memory_value(const char *name, expression_space space, u32 offset, int size, bool with_se);
void set_memory_value(const char *name, expression_space space, u32 offset, int size, u64 value, bool with_se);
private:
// internal state
@ -255,8 +255,10 @@ private:
TIN_MEMORY_SIZE_MASK = 3 << TIN_MEMORY_SIZE_SHIFT,
TIN_MEMORY_SPACE_SHIFT = 20, // 4 bits (20-23)
TIN_MEMORY_SPACE_MASK = 0xf << TIN_MEMORY_SPACE_SHIFT,
TIN_PRECEDENCE_SHIFT = 24, // 8 bits (24-31)
TIN_PRECEDENCE_MASK = 0xff << TIN_PRECEDENCE_SHIFT
TIN_PRECEDENCE_SHIFT = 24, // 5 bits (24-28)
TIN_PRECEDENCE_MASK = 0x1f << TIN_PRECEDENCE_SHIFT,
TIN_SIDE_EFFECT_SHIFT = 29, // 1 bit (29)
TIN_SIDE_EFFECT_MASK = 1 << TIN_SIDE_EFFECT_SHIFT
};
// types of tokens
@ -295,6 +297,7 @@ private:
bool right_to_left() const { assert(m_type == OPERATOR); return ((m_flags & TIN_RIGHT_TO_LEFT_MASK) != 0); }
expression_space memory_space() const { assert(m_type == OPERATOR || m_type == MEMORY); return expression_space((m_flags & TIN_MEMORY_SPACE_MASK) >> TIN_MEMORY_SPACE_SHIFT); }
int memory_size() const { assert(m_type == OPERATOR || m_type == MEMORY); return (m_flags & TIN_MEMORY_SIZE_MASK) >> TIN_MEMORY_SIZE_SHIFT; }
bool memory_side_effect() const { assert(m_type == OPERATOR || m_type == MEMORY); return (m_flags & TIN_SIDE_EFFECT_MASK) >> TIN_SIDE_EFFECT_SHIFT; }
// setters
parse_token &set_offset(int offset) { m_offset = offset; return *this; }
@ -311,6 +314,7 @@ private:
parse_token &set_right_to_left() { assert(m_type == OPERATOR); m_flags |= TIN_RIGHT_TO_LEFT_MASK; return *this; }
parse_token &set_memory_space(expression_space space) { assert(m_type == OPERATOR || m_type == MEMORY); m_flags = (m_flags & ~TIN_MEMORY_SPACE_MASK) | ((space << TIN_MEMORY_SPACE_SHIFT) & TIN_MEMORY_SPACE_MASK); return *this; }
parse_token &set_memory_size(int log2ofbits) { assert(m_type == OPERATOR || m_type == MEMORY); m_flags = (m_flags & ~TIN_MEMORY_SIZE_MASK) | ((log2ofbits << TIN_MEMORY_SIZE_SHIFT) & TIN_MEMORY_SIZE_MASK); return *this; }
parse_token &set_memory_side_effect(bool with_se) { assert(m_type == OPERATOR || m_type == MEMORY); m_flags = with_se ? m_flags | TIN_SIDE_EFFECT_MASK : m_flags & ~TIN_SIDE_EFFECT_MASK; return *this; }
parse_token &set_memory_source(const char *string) { assert(m_type == OPERATOR || m_type == MEMORY); m_string = string; return *this; }
// access
@ -359,7 +363,7 @@ private:
void parse_number(parse_token &token, const char *string, int base, expression_error::error_code errcode);
void parse_quoted_char(parse_token &token, const char *&string);
void parse_quoted_string(parse_token &token, const char *&string);
void parse_memory_operator(parse_token &token, const char *string);
void parse_memory_operator(parse_token &token, const char *string, bool with_se);
void normalize_operator(parse_token *prevtoken, parse_token &thistoken);
void infix_to_postfix();

5
src/emu/emumem.cpp
View File

@ -714,7 +714,7 @@ private:
template<typename _UintType>
_UintType unmap_r(address_space &space, offs_t offset, _UintType mask)
{
if (m_space.log_unmap() && !m_space.debugger_access())
if (m_space.log_unmap() && !m_space.machine().side_effect_disabled())
{
m_space.device().logerror(
m_space.is_octal()
@ -785,7 +785,7 @@ private:
template<typename _UintType>
void unmap_w(address_space &space, offs_t offset, _UintType data, _UintType mask)
{
if (m_space.log_unmap() && !m_space.debugger_access())
if (m_space.log_unmap() && !m_space.machine().side_effect_disabled())
{
m_space.device().logerror(
m_space.is_octal()
@ -1739,7 +1739,6 @@ address_space::address_space(memory_manager &manager, device_memory_interface &m
m_logbytemask(address_to_byte_end(m_logaddrmask)),
m_unmap(0),
m_spacenum(spacenum),
m_debugger_access(false),
m_log_unmap(true),
m_direct(std::make_unique<direct_read_data>(*this)),
m_name(memory.space_config(spacenum)->name()),

30
src/emu/emumem.h
View File

@ -290,8 +290,6 @@ public:
// debug helpers
const char *get_handler_string(read_or_write readorwrite, offs_t byteaddress);
bool debugger_access() const { return m_debugger_access; }
void set_debugger_access(bool debugger) { m_debugger_access = debugger; }
bool log_unmap() const { return m_log_unmap; }
void set_log_unmap(bool log) { m_log_unmap = log; }
void dump_map(FILE *file, read_or_write readorwrite);
@ -462,7 +460,6 @@ protected:
offs_t m_logbytemask; // byte-converted logical address mask
u64 m_unmap; // unmapped value
address_spacenum m_spacenum; // address space index
bool m_debugger_access; // treat accesses as coming from the debugger
bool m_log_unmap; // log unmapped accesses in this space?
std::unique_ptr<direct_read_data> m_direct; // fast direct-access read info
const char * m_name; // friendly name of the address space
@ -475,33 +472,6 @@ private:
};
// ======================> address_space_debug_wrapper
// wrapper for temporarily setting the debug flag on a memory space (especially one being accessed through another space)
class address_space_debug_wrapper
{
public:
// construction
address_space_debug_wrapper(address_space &space, bool debugger_access)
: m_target(space)
, m_prev_debugger_access(space.debugger_access())
{
space.set_debugger_access(debugger_access);
}
// destruction
~address_space_debug_wrapper() { m_target.set_debugger_access(m_prev_debugger_access); }
// getter
address_space &space() const { return m_target; }
private:
// internal state
address_space &m_target;
const bool m_prev_debugger_access;
};
// ======================> memory_block
// a memory block is a chunk of RAM associated with a range of memory in a device's address space

1
src/emu/machine.cpp
View File

@ -112,6 +112,7 @@ osd_interface &running_machine::osd() const
running_machine::running_machine(const machine_config &_config, machine_manager &manager)
: firstcpu(nullptr),
primary_screen(nullptr),
m_side_effect_disabled(0),
debug_flags(0),
m_config(_config),
m_system(_config.gamedrv()),

28
src/emu/machine.h
View File

@ -167,8 +167,11 @@ class running_machine
{
DISABLE_COPYING(running_machine);
struct side_effect_disabler;
friend class sound_manager;
friend class memory_manager;
friend struct side_effect_disabler;
typedef std::function<void(const char*)> logerror_callback;
@ -219,6 +222,10 @@ public:
bool save_or_load_pending() const { return !m_saveload_pending_file.empty(); }
screen_device *first_screen() const { return primary_screen; }
// RAII-based side effect disable
side_effect_disabler disable_side_effect() { return side_effect_disabler(this); }
bool side_effect_disabled() const { return m_side_effect_disabled != 0; }
// additional helpers
emu_options &options() const { return m_config.options(); }
attotime time() const { return m_scheduler.time(); }
@ -274,11 +281,32 @@ private:
// video-related information
screen_device * primary_screen; // the primary screen device, or nullptr if screenless
// side effect disable counter
u32 m_side_effect_disabled;
public:
// debugger-related information
u32 debug_flags; // the current debug flags
private:
struct side_effect_disabler {
running_machine *m_machine;
side_effect_disabler(running_machine *m) : m_machine(m) {
m_machine->disable_side_effect_count();
}
~side_effect_disabler() {
m_machine->enable_side_effect_count();
}
side_effect_disabler(const side_effect_disabler &) = delete;
side_effect_disabler(side_effect_disabler &&) = default;
};
void disable_side_effect_count() { m_side_effect_disabled++; }
void enable_side_effect_count() { m_side_effect_disabled--; }
// internal helpers
template <typename T> struct is_null { template <typename U> static bool value(U &&x) { return false; } };
template <typename T> struct is_null<T *> { template <typename U> static bool value(U &&x) { return !x; } };

4
src/mame/drivers/a2600.cpp
View File

@ -120,7 +120,7 @@ ADDRESS_MAP_END
READ8_MEMBER(a2600_state::cart_over_all_r)
{
if (!space.debugger_access())
if (!machine().side_effect_disabled())
m_cart->write_bank(space, offset, 0);
int masked_offset = offset &~ 0x0d00;
@ -342,7 +342,7 @@ WRITE16_MEMBER(a2600_state::a2600_tia_vsync_callback_pal)
// TODO: is this the correct behavior for the real hardware?!?
READ8_MEMBER(a2600_state::cart_over_riot_r)
{
if (!space.debugger_access())
if (!machine().side_effect_disabled())
m_cart->write_bank(space, offset, 0);
return m_riot_ram[0x20 + offset];
}

12
src/mame/drivers/apple2.cpp
View File

@ -472,7 +472,7 @@ uint32_t napple2_state::screen_update_jp(screen_device &screen, bitmap_ind16 &bi
// most softswitches don't care about read vs write, so handle them here
void napple2_state::do_io(address_space &space, int offset)
{
if(space.debugger_access())
if(machine().side_effect_disabled())
{
return;
}
@ -641,7 +641,7 @@ WRITE8_MEMBER(napple2_state::c000_w)
READ8_MEMBER(napple2_state::c080_r)
{
if(!space.debugger_access())
if(!machine().side_effect_disabled())
{
int slot;
@ -678,7 +678,7 @@ READ8_MEMBER(napple2_state::c100_r)
if (m_slotdevice[slotnum] != nullptr)
{
if ((m_slotdevice[slotnum]->take_c800()) && (!space.debugger_access()))
if ((m_slotdevice[slotnum]->take_c800()) && (!machine().side_effect_disabled()))
{
m_cnxx_slot = slotnum;
}
@ -697,7 +697,7 @@ WRITE8_MEMBER(napple2_state::c100_w)
if (m_slotdevice[slotnum] != nullptr)
{
if ((m_slotdevice[slotnum]->take_c800()) && (!space.debugger_access()))
if ((m_slotdevice[slotnum]->take_c800()) && (!machine().side_effect_disabled()))
{
m_cnxx_slot = slotnum;
}
@ -710,7 +710,7 @@ READ8_MEMBER(napple2_state::c800_r)
{
if (offset == 0x7ff)
{
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
m_cnxx_slot = -1;
}
@ -730,7 +730,7 @@ WRITE8_MEMBER(napple2_state::c800_w)
{
if (offset == 0x7ff)
{
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
m_cnxx_slot = -1;
}

26
src/mame/drivers/apple2e.cpp
View File

@ -1084,7 +1084,7 @@ void apple2e_state::lc_update(int offset, int access)
// most softswitches don't care about read vs write, so handle them here
void apple2e_state::do_io(address_space &space, int offset, bool is_iic)
{
if(space.debugger_access()) return;
if(machine().side_effect_disabled()) return;
// Handle C058-C05F according to IOUDIS
if ((offset & 0x58) == 0x58)
@ -1285,7 +1285,7 @@ void apple2e_state::do_io(address_space &space, int offset, bool is_iic)
READ8_MEMBER(apple2e_state::c000_r)
{
if(space.debugger_access()) return read_floatingbus();
if(machine().side_effect_disabled()) return read_floatingbus();
switch (offset)
{
@ -1396,7 +1396,7 @@ READ8_MEMBER(apple2e_state::c000_r)
WRITE8_MEMBER(apple2e_state::c000_w)
{
if(space.debugger_access()) return;
if(machine().side_effect_disabled()) return;
switch (offset)
{
@ -1514,7 +1514,7 @@ WRITE8_MEMBER(apple2e_state::c000_w)
READ8_MEMBER(apple2e_state::c000_iic_r)
{
if(space.debugger_access()) return read_floatingbus();
if(machine().side_effect_disabled()) return read_floatingbus();
switch (offset)
{
@ -1658,7 +1658,7 @@ READ8_MEMBER(apple2e_state::c000_iic_r)
WRITE8_MEMBER(apple2e_state::c000_iic_w)
{
if(space.debugger_access()) return;
if(machine().side_effect_disabled()) return;
switch (offset)
{
@ -1856,7 +1856,7 @@ void apple2e_state::update_iic_mouse()
READ8_MEMBER(apple2e_state::c080_r)
{
if(!space.debugger_access())
if(!machine().side_effect_disabled())
{
int slot;
@ -1905,7 +1905,7 @@ uint8_t apple2e_state::read_slot_rom(address_space &space, int slotbias, int off
if (m_slotdevice[slotnum] != nullptr)
{
if ((m_cnxx_slot == CNXX_UNCLAIMED) && (m_slotdevice[slotnum]->take_c800()) && (!space.debugger_access()))
if ((m_cnxx_slot == CNXX_UNCLAIMED) && (m_slotdevice[slotnum]->take_c800()) && (!machine().side_effect_disabled()))
{
m_cnxx_slot = slotnum;
update_slotrom_banks();
@ -1923,7 +1923,7 @@ void apple2e_state::write_slot_rom(address_space &space, int slotbias, int offse
if (m_slotdevice[slotnum] != nullptr)
{
if ((m_cnxx_slot == CNXX_UNCLAIMED) && (m_slotdevice[slotnum]->take_c800()) && (!space.debugger_access()))
if ((m_cnxx_slot == CNXX_UNCLAIMED) && (m_slotdevice[slotnum]->take_c800()) && (!machine().side_effect_disabled()))
{
m_cnxx_slot = slotnum;
update_slotrom_banks();
@ -1936,7 +1936,7 @@ void apple2e_state::write_slot_rom(address_space &space, int slotbias, int offse
uint8_t apple2e_state::read_int_rom(address_space &space, int slotbias, int offset)
{
#if 0
if ((m_cnxx_slot == CNXX_UNCLAIMED) && (!space.debugger_access()))
if ((m_cnxx_slot == CNXX_UNCLAIMED) && (!machine().side_effect_disabled()))
{
m_cnxx_slot = CNXX_INTROM;
update_slotrom_banks();
@ -2021,7 +2021,7 @@ READ8_MEMBER(apple2e_state::c800_r)
if (offset == 0x7ff)
{
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
m_cnxx_slot = CNXX_UNCLAIMED;
update_slotrom_banks();
@ -2045,7 +2045,7 @@ READ8_MEMBER(apple2e_state::c800_int_r)
return m_iicplus_ce00[offset-0x600];
}
if ((offset == 0x7ff) && !space.debugger_access())
if ((offset == 0x7ff) && !machine().side_effect_disabled())
{
m_cnxx_slot = CNXX_UNCLAIMED;
m_intc8rom = false;
@ -2062,7 +2062,7 @@ READ8_MEMBER(apple2e_state::c800_b2_int_r)
return m_iicplus_ce00[offset-0x600];
}
if ((offset == 0x7ff) && !space.debugger_access())
if ((offset == 0x7ff) && !machine().side_effect_disabled())
{
m_cnxx_slot = CNXX_UNCLAIMED;
m_intc8rom = false;
@ -2082,7 +2082,7 @@ WRITE8_MEMBER(apple2e_state::c800_w)
if (offset == 0x7ff)
{
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
m_cnxx_slot = CNXX_UNCLAIMED;
m_intc8rom = false;

2
src/mame/drivers/atarist.cpp
View File

@ -433,7 +433,7 @@ WRITE16_MEMBER( st_state::berr_w )
READ16_MEMBER( st_state::berr_r )
{
if(!space.debugger_access()) {
if(!machine().side_effect_disabled()) {
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
}

5
src/mame/drivers/c65.cpp
View File

@ -186,7 +186,7 @@ READ8_MEMBER(c65_state::vic4567_dummy_r)
return m_VIC3_ControlB;
}
if(!space.debugger_access())
if(!machine().side_effect_disabled())
printf("%02x\n",offset); // TODO: PC
return res;
}
@ -221,8 +221,7 @@ WRITE8_MEMBER(c65_state::vic4567_dummy_w)
m_VIC3_ControlB = data;
break;
default:
if(!space.debugger_access())
printf("%02x %02x\n",offset,data);
printf("%02x %02x\n",offset,data);
break;
}

4
src/mame/drivers/cdi.cpp
View File

@ -370,7 +370,7 @@ MACHINE_RESET_MEMBER( cdi_state, quizard4 )
READ8_MEMBER( cdi_state::servo_io_r )
{
if (space.debugger_access())
if (space.machine().side_effect_disabled())
{
return 0;
}
@ -570,7 +570,7 @@ WRITE8_MEMBER( cdi_state::servo_io_w )
READ8_MEMBER( cdi_state::slave_io_r )
{
if (space.debugger_access())
if (space.machine().side_effect_disabled())
{
return 0;
}

12
src/mame/drivers/cmi.cpp
View File

@ -836,7 +836,7 @@ void cmi_state::video_write(int offset)
READ8_MEMBER( cmi_state::video_r )
{
if (space.debugger_access())
if (machine().side_effect_disabled())
return m_video_data;
m_video_data = m_video_ram[m_y_pos * (512 / 8) + (m_x_pos / 8)];
@ -882,7 +882,7 @@ WRITE8_MEMBER( cmi_state::vram_w )
READ8_MEMBER( cmi_state::vram_r )
{
if (space.debugger_access())
if (machine().side_effect_disabled())
return m_video_ram[offset];
/* Latch the current video position */
@ -951,7 +951,7 @@ READ8_MEMBER( cmi_state::irq_ram_r )
{
int cpunum = (&space.device() == m_maincpu1) ? 0 : 1;
if (space.debugger_access())
if (machine().side_effect_disabled())
return m_scratch_ram[cpunum][0xf8 + offset];
if (m_m6809_bs_hack_cnt > 0 && m_m6809_bs_hack_cpu == cpunum)
@ -1587,7 +1587,7 @@ WRITE8_MEMBER( cmi_state::fdc_w )
READ8_MEMBER( cmi_state::fdc_r )
{
if (space.debugger_access())
if (machine().side_effect_disabled())
return 0;
if (offset == 0)
@ -2009,7 +2009,7 @@ WRITE8_MEMBER( cmi01a_device::write )
READ8_MEMBER( cmi01a_device::read )
{
if (space.debugger_access())
if (machine().side_effect_disabled())
return 0;
uint8_t data = 0;
@ -2083,7 +2083,7 @@ WRITE_LINE_MEMBER( cmi_state::cmi02_ptm_o1 )
READ8_MEMBER( cmi_state::cmi02_r )
{
if (space.debugger_access())
if (machine().side_effect_disabled())
return 0;
if (offset <= 0x1f)

4
src/mame/drivers/esq5505.cpp
View File

@ -341,7 +341,7 @@ READ16_MEMBER(esq5505_state::lower_r)
m_ram = (uint16_t *)(void *)memshare("osram")->ptr();
}
if (!space.debugger_access() && m_maincpu->get_fc() == 0x6) // supervisor mode = ROM
if (!machine().side_effect_disabled() && m_maincpu->get_fc() == 0x6) // supervisor mode = ROM
{
return m_rom[offset];
}
@ -357,7 +357,7 @@ WRITE16_MEMBER(esq5505_state::lower_w)
if (offset < 0x4000)
{
if (space.debugger_access() || m_maincpu->get_fc() != 0x6) // if not supervisor mode, RAM
if (m_maincpu->get_fc() != 0x6) // if not supervisor mode, RAM
{
COMBINE_DATA(&m_ram[offset]);
}

2
src/mame/drivers/fm7.cpp
View File

@ -374,7 +374,7 @@ READ8_MEMBER(fm7_state::fm7_fd04_r)
*/
READ8_MEMBER(fm7_state::fm7_rom_en_r)
{
if(!space.debugger_access())
if(!machine().side_effect_disabled())
{
uint8_t* RAM = memregion("maincpu")->base();

4
src/mame/drivers/hyperscan.cpp
View File

@ -224,7 +224,7 @@ READ32_MEMBER(hyperscan_state::spg290_regs_r)
#if LOG_SPG290_REGISTER_ACCESS
//else
{
if (!space.debugger_access())
if (!machine().side_effect_disabled())
log_spg290_regs(this,(offset >> 14) & 0xff, (offset<<2) & 0xffff, mem_mask, false);
}
#endif
@ -387,7 +387,7 @@ WRITE32_MEMBER(hyperscan_state::spg290_regs_w)
#if LOG_SPG290_REGISTER_ACCESS
//else
{
if (!space.debugger_access())
if (!machine().side_effect_disabled())
log_spg290_regs(this,(offset >> 14) & 0xff, (offset<<2) & 0xffff, mem_mask, true, data);
}
#endif

10
src/mame/drivers/lwriter.cpp
View File

@ -251,10 +251,10 @@ READ16_MEMBER(lwriter_state::bankedarea_r)
}
else if (offset <= 0x01ffff)
{
if ((offset > 0x7ff) && !space.debugger_access()) { logerror("Attempt to read banked area (with overlay off) past end of SRAM from offset %08X!\n",offset<<1); }
if ((offset > 0x7ff) && !machine().side_effect_disabled()) { logerror("Attempt to read banked area (with overlay off) past end of SRAM from offset %08X!\n",offset<<1); }
return m_sram_ptr[offset&0x7FF];
}
if(!space.debugger_access()) { logerror("Attempt to read banked area (with overlay off) past end of SRAM from offset %08X! Returning 0xFFFF!\n",offset<<1); }
if(!machine().side_effect_disabled()) { logerror("Attempt to read banked area (with overlay off) past end of SRAM from offset %08X! Returning 0xFFFF!\n",offset<<1); }
return 0xFFFF;
}
@ -262,16 +262,16 @@ WRITE16_MEMBER(lwriter_state::bankedarea_w)
{
if (m_overlay)
{
if(!space.debugger_access()) { logerror("Attempt to write banked area (with overlay ON) with data %04X to offset %08X IGNORED!\n",data, offset<<1); }
if(!machine().side_effect_disabled()) { logerror("Attempt to write banked area (with overlay ON) with data %04X to offset %08X IGNORED!\n",data, offset<<1); }
return;
}
else if (offset <= 0x01ffff)
{
if ((offset > 0x7ff) && !space.debugger_access()) { logerror("Attempt to write banked area (with overlay off) with data %04X to offset %08X!\n",data, offset<<1); }
if ((offset > 0x7ff) && !machine().side_effect_disabled()) { logerror("Attempt to write banked area (with overlay off) with data %04X to offset %08X!\n",data, offset<<1); }
COMBINE_DATA(&m_sram_ptr[offset&0x7FF]);
return;
}
if(!space.debugger_access()) { logerror("Attempt to write banked area (with overlay off) with data %04X to offset %08X IGNORED!\n", data, offset<<1); }
if(!machine().side_effect_disabled()) { logerror("Attempt to write banked area (with overlay off) with data %04X to offset %08X IGNORED!\n", data, offset<<1); }
}
/* 4 diagnostic LEDs, plus 4 i/o lines for the printer */

12
src/mame/drivers/megasys1.cpp
View File

@ -4210,7 +4210,7 @@ READ16_MEMBER(megasys1_state::megasys1A_mcu_hs_r)
{
if(m_mcu_hs && ((m_mcu_hs_ram[8/2] << 6) & 0x3ffc0) == ((offset*2) & 0x3ffc0))
{
if(MCU_HS_LOG && !space.debugger_access())
if(MCU_HS_LOG && !machine().side_effect_disabled())
printf("MCU HS R (%04x) <- [%02x]\n",mem_mask,offset*2);
return 0x889e;
@ -4238,7 +4238,7 @@ WRITE16_MEMBER(megasys1_state::megasys1A_mcu_hs_w)
else
m_mcu_hs = 0;
if(MCU_HS_LOG && !space.debugger_access())
if(MCU_HS_LOG && !machine().side_effect_disabled())
printf("MCU HS W %04x (%04x) -> [%02x]\n",data,mem_mask,offset*2);
}
@ -4357,7 +4357,7 @@ READ16_MEMBER(megasys1_state::iganinju_mcu_hs_r)
{
if(m_mcu_hs && ((m_mcu_hs_ram[8/2] << 6) & 0x3ffc0) == ((offset*2) & 0x3ffc0))
{
if(MCU_HS_LOG && !space.debugger_access())
if(MCU_HS_LOG && !machine().side_effect_disabled())
printf("MCU HS R (%04x) <- [%02x]\n",mem_mask,offset*2);
return 0x835d;
@ -4382,7 +4382,7 @@ WRITE16_MEMBER(megasys1_state::iganinju_mcu_hs_w)
else
m_mcu_hs = 0;
if(MCU_HS_LOG && !space.debugger_access())
if(MCU_HS_LOG && !machine().side_effect_disabled())
printf("MCU HS W %04x (%04x) -> [%02x]\n",data,mem_mask,offset*2);
}
@ -4506,7 +4506,7 @@ READ16_MEMBER(megasys1_state::stdragon_mcu_hs_r)
{
if(m_mcu_hs && ((m_mcu_hs_ram[8/2] << 6) & 0x3ffc0) == ((offset*2) & 0x3ffc0))
{
if(MCU_HS_LOG && !space.debugger_access())
if(MCU_HS_LOG && !machine().side_effect_disabled())
printf("MCU HS R (%04x) <- [%02x]\n",mem_mask,offset*2);
return 0x835d;
@ -4524,7 +4524,7 @@ WRITE16_MEMBER(megasys1_state::stdragon_mcu_hs_w)
else
m_mcu_hs = 0;
if(MCU_HS_LOG && !space.debugger_access())
if(MCU_HS_LOG && !machine().side_effect_disabled())
printf("MCU HS W %04x (%04x) -> [%02x]\n",data,mem_mask,offset*2);
}

5
src/mame/drivers/model2.cpp
View File

@ -1243,10 +1243,7 @@ WRITE32_MEMBER(model2_state::model2o_serial_w)
{
if(mem_mask == 0xffff0000)
{
if (!space.debugger_access())
{
//m_soundack++;
}
//m_soundack++;
}
if (mem_mask == 0x0000ffff)
{

10
src/mame/drivers/next.cpp
View File

@ -84,7 +84,7 @@ uint32_t next_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap,
/* Dummy catcher for any unknown r/w */
READ8_MEMBER( next_state::io_r )
{
if(!space.debugger_access())
if(!machine().side_effect_disabled())
printf("io_r %08x (%08x)\n",offset+0x02000000, space.device().safe_pc());
if(offset == 0xc0)
@ -95,21 +95,21 @@ READ8_MEMBER( next_state::io_r )
WRITE8_MEMBER( next_state::io_w )
{
if(!space.debugger_access())
if(!machine().side_effect_disabled())
printf("io_w %08x, %02x (%08x)\n",offset+0x02000000,data, space.device().safe_pc());
}
/* map ROM at 0x01000000-0x0101ffff? */
READ32_MEMBER( next_state::rom_map_r )
{
if(0 && !space.debugger_access())
if(0 && !machine().side_effect_disabled())
printf("%08x ROM MAP?\n",space.device().safe_pc());
return 0x01000000;
}
READ32_MEMBER( next_state::scr2_r )
{
if(0 && !space.debugger_access())
if(0 && !machine().side_effect_disabled())
printf("%08x\n",space.device().safe_pc());
/*
x--- ---- ---- ---- ---- ---- ---- ---- dsp reset
@ -146,7 +146,7 @@ READ32_MEMBER( next_state::scr2_r )
WRITE32_MEMBER( next_state::scr2_w )
{
if(0 && !space.debugger_access())
if(0 && !machine().side_effect_disabled())
printf("scr2_w %08x (%08x)\n", data, space.device().safe_pc());
COMBINE_DATA(&scr2);

4
src/mame/drivers/pc8801.cpp
View File

@ -1066,7 +1066,7 @@ READ8_MEMBER(pc8801_state::pc8801_mem_r)
if(m_misc_ctrl & 0x40)
{
if(!space.debugger_access())
if(!machine().side_effect_disabled())
m_vram_sel = 3;
if(m_alu_ctrl2 & 0x80)
@ -1128,7 +1128,7 @@ WRITE8_MEMBER(pc8801_state::pc8801_mem_w)
{
if(m_misc_ctrl & 0x40)
{
if(!space.debugger_access())
if(!machine().side_effect_disabled())
m_vram_sel = 3;
if(m_alu_ctrl2 & 0x80)

2
src/mame/drivers/pc9801.cpp
View File

@ -1468,7 +1468,7 @@ READ16_MEMBER(pc9801_state::upd7220_grcg_r)
{
uint16_t res = 0;
if(!(m_grcg.mode & 0x80) || space.debugger_access())
if(!(m_grcg.mode & 0x80) || machine().side_effect_disabled())
res = m_video_ram_2[offset];
else if(m_ex_video_ff[2])
res = egc_blit_r(offset, mem_mask);

8
src/mame/drivers/pcd.cpp
View File

@ -162,7 +162,7 @@ WRITE_LINE_MEMBER( pcd_state::i186_timer1_w )
READ8_MEMBER( pcd_state::nmi_io_r )
{
if(space.debugger_access())
if(machine().side_effect_disabled())
return 0;
logerror("%s: unmapped %s %04x\n", machine().describe_context(), space.name(), offset);
m_stat |= 0xfd;
@ -172,7 +172,7 @@ READ8_MEMBER( pcd_state::nmi_io_r )
WRITE8_MEMBER( pcd_state::nmi_io_w )
{
if(space.debugger_access())
if(machine().side_effect_disabled())
return;
logerror("%s: unmapped %s %04x\n", machine().describe_context(), space.name(), offset);
m_stat |= 0xfd;
@ -394,7 +394,7 @@ WRITE16_MEMBER(pcd_state::mem_w)
reg = m_mmu.regs[((offset >> 10) & 0xff) | ((m_mmu.ctl & 0x18) << 5)];
else
reg = m_mmu.regs[((offset >> 10) & 0x7f) | ((m_mmu.ctl & 0x1c) << 5)];
if(!reg && !space.debugger_access())
if(!reg && !machine().side_effect_disabled())
{
offset <<= 1;
logerror("%s: Null mmu entry %06x\n", machine().describe_context(), offset);
@ -416,7 +416,7 @@ READ16_MEMBER(pcd_state::mem_r)
reg = m_mmu.regs[((offset >> 10) & 0xff) | ((m_mmu.ctl & 0x18) << 5)];
else
reg = m_mmu.regs[((offset >> 10) & 0x7f) | ((m_mmu.ctl & 0x1c) << 5)];
if(!reg && !space.debugger_access())
if(!reg && !machine().side_effect_disabled())
{
offset <<= 1;
logerror("%s: Null mmu entry %06x\n", machine().describe_context(), offset);

2
src/mame/drivers/psion.cpp
View File

@ -138,7 +138,7 @@ READ8_MEMBER( psion_state::hd63701_int_reg_r )
/* Read/Write common */
void psion_state::io_rw(address_space &space, uint16_t offset)
{
if (space.debugger_access())
if (machine().side_effect_disabled())
return;
switch (offset & 0xffc0)

2
src/mame/drivers/rainbow.cpp
View File

@ -2859,7 +2859,7 @@ WRITE_LINE_MEMBER(rainbow_state::irq_hi_w)
READ16_MEMBER(rainbow_state::vram_r)
{
if((!(m_GDC_MODE_REGISTER & GDC_MODE_VECTOR)) || space.debugger_access()) // (NOT VECTOR MODE)
if((!(m_GDC_MODE_REGISTER & GDC_MODE_VECTOR)) || machine().side_effect_disabled()) // (NOT VECTOR MODE)
{
// SCROLL_MAP IN BITMAP MODE ONLY...?
if(m_GDC_MODE_REGISTER & GDC_MODE_HIGHRES)

2
src/mame/drivers/sc2.cpp
View File

@ -47,7 +47,7 @@ public:
READ8_MEMBER( sc2_state::sc2_beep )
{
//if (!space.debugger_access())
//if (!machine().side_effect_disabled())
{
m_beep_state = ~m_beep_state;

4
src/mame/drivers/skylncr.cpp
View File

@ -434,8 +434,8 @@ READ_LINE_MEMBER(skylncr_state::mbutrfly_prot_r)
READ8_MEMBER(skylncr_state::bdream97_opcode_r)
{
address_space_debug_wrapper program(m_maincpu->space(AS_PROGRAM), space.debugger_access());
return program.space().read_byte(offset) ^ 0x80;
auto dis = machine().disable_side_effect();
return m_maincpu->space(AS_PROGRAM).read_byte(offset) ^ 0x80;
}

4
src/mame/drivers/snk.cpp
View File

@ -286,7 +286,7 @@ TODO:
READ8_MEMBER(snk_state::snk_cpuA_nmi_trigger_r)
{
if(!space.debugger_access())
if(!machine().side_effect_disabled())
{
m_maincpu->set_input_line(INPUT_LINE_NMI, ASSERT_LINE);
}
@ -300,7 +300,7 @@ WRITE8_MEMBER(snk_state::snk_cpuA_nmi_ack_w)
READ8_MEMBER(snk_state::snk_cpuB_nmi_trigger_r)
{
if(!space.debugger_access())
if(!machine().side_effect_disabled())
{
m_subcpu->set_input_line(INPUT_LINE_NMI, ASSERT_LINE);
}

14
src/mame/drivers/stv.cpp
View File

@ -100,7 +100,7 @@ READ8_MEMBER(stv_state::stv_ioga_r)
uint8_t res;
res = 0xff;
if(offset & 0x20 && !space.debugger_access())
if(offset & 0x20 && !machine().side_effect_disabled())
printf("Reading from mirror %08x?\n",offset);
offset &= 0x1f; // mirror?
@ -121,7 +121,7 @@ READ8_MEMBER(stv_state::stv_ioga_r)
WRITE8_MEMBER(stv_state::stv_ioga_w)
{
if(offset & 0x20 && !space.debugger_access())
if(offset & 0x20 && !machine().side_effect_disabled())
printf("Writing to mirror %08x %02x?\n",offset,data);
offset &= 0x1f; // mirror?
@ -278,7 +278,7 @@ READ32_MEMBER(stv_state::critcrsh_ioga_r32)
res |= critcrsh_ioga_r(space,offset*4+3);
if(ACCESSING_BITS_8_15 || ACCESSING_BITS_24_31)
if(!(ACCESSING_BITS_16_23 || ACCESSING_BITS_0_7))
if(!space.debugger_access())
if(!machine().side_effect_disabled())
printf("Warning: IOGA reads from odd offset %02x %08x!\n",offset*4,mem_mask);
return res;
@ -295,7 +295,7 @@ READ32_MEMBER(stv_state::stvmp_ioga_r32)
res |= stvmp_ioga_r(space,offset*4+3);
if(ACCESSING_BITS_8_15 || ACCESSING_BITS_24_31)
if(!(ACCESSING_BITS_16_23 || ACCESSING_BITS_0_7))
if(!space.debugger_access())
if(!machine().side_effect_disabled())
printf("Warning: IOGA reads from odd offset %02x %08x!\n",offset*4,mem_mask);
return res;
@ -309,7 +309,7 @@ WRITE32_MEMBER(stv_state::stvmp_ioga_w32)
stvmp_ioga_w(space,offset*4+3,data);
if(ACCESSING_BITS_8_15 || ACCESSING_BITS_24_31)
if(!(ACCESSING_BITS_16_23 || ACCESSING_BITS_0_7))
if(!space.debugger_access())
if(!machine().side_effect_disabled())
printf("Warning: IOGA writes to odd offset %02x (%08x) -> %08x!",offset*4,mem_mask,data);
}
@ -324,7 +324,7 @@ READ32_MEMBER(stv_state::magzun_ioga_r32)
res |= magzun_ioga_r(space,offset*4+3);
if(ACCESSING_BITS_8_15 || ACCESSING_BITS_24_31)
if(!(ACCESSING_BITS_16_23 || ACCESSING_BITS_0_7))
if(!space.debugger_access())
if(!machine().side_effect_disabled())
printf("Warning: IOGA reads from odd offset %02x %08x!\n",offset*4,mem_mask);
return res;
@ -338,7 +338,7 @@ WRITE32_MEMBER(stv_state::magzun_ioga_w32)
magzun_ioga_w(space,offset*4+3,data);
if(ACCESSING_BITS_8_15 || ACCESSING_BITS_24_31)
if(!(ACCESSING_BITS_16_23 || ACCESSING_BITS_0_7))
if(!space.debugger_access())
if(!machine().side_effect_disabled())
printf("Warning: IOGA writes to odd offset %02x (%08x) -> %08x!",offset*4,mem_mask,data);
}

14
src/mame/drivers/sun2.cpp
View File

@ -195,7 +195,7 @@ READ16_MEMBER( sun2_state::tl_mmu_r )
{
uint8_t fc = m_maincpu->get_fc();
if ((fc == 3) && !space.debugger_access())
if ((fc == 3) && !machine().side_effect_disabled())
{
if (offset & 0x4) // set for CPU space
{
@ -254,7 +254,7 @@ READ16_MEMBER( sun2_state::tl_mmu_r )
}
// debugger hack
if ((space.debugger_access()) && (offset >= (0xef0000>>1)) && (offset <= (0xef8000>>1)))
if (machine().side_effect_disabled() && (offset >= (0xef0000>>1)) && (offset <= (0xef8000>>1)))
{
return m_rom_ptr[offset & 0x3fff];
}
@ -274,7 +274,7 @@ READ16_MEMBER( sun2_state::tl_mmu_r )
uint32_t tmp = (m_pagemap[entry] & 0xfff) << 10;
tmp |= (offset & 0x3ff);
// if (!space.debugger_access())
// if (!machine().side_effect_disabled())
// printf("sun2: Translated addr: %08x, type %d (page %d page entry %08x, orig virt %08x, FC %d)\n", tmp << 1, (m_pagemap[entry] >> 22) & 7, entry, m_pagemap[entry], offset<<1, fc);
switch ((m_pagemap[entry] >> 22) & 7)
@ -317,10 +317,10 @@ READ16_MEMBER( sun2_state::tl_mmu_r )
}
else
{
if (!space.debugger_access()) printf("sun2: pagemap entry not valid!\n");
if (!machine().side_effect_disabled()) printf("sun2: pagemap entry not valid!\n");
}
if (!space.debugger_access()) printf("sun2: Unmapped read @ %08x (FC %d, mask %04x, PC=%x, seg %x)\n", offset<<1, fc, mem_mask, m_maincpu->pc, offset>>15);
if (!machine().side_effect_disabled()) printf("sun2: Unmapped read @ %08x (FC %d, mask %04x, PC=%x, seg %x)\n", offset<<1, fc, mem_mask, m_maincpu->pc, offset>>15);
return 0xffff;
}
@ -420,7 +420,7 @@ WRITE16_MEMBER( sun2_state::tl_mmu_w )
uint32_t tmp = (m_pagemap[entry] & 0xfff) << 10;
tmp |= (offset & 0x3ff);
//if (!space.debugger_access()) printf("sun2: Translated addr: %08x, type %d (page entry %08x, orig virt %08x)\n", tmp << 1, (m_pagemap[entry] >> 22) & 7, m_pagemap[entry], offset<<1);
//if (!machine().side_effect_disabled()) printf("sun2: Translated addr: %08x, type %d (page entry %08x, orig virt %08x)\n", tmp << 1, (m_pagemap[entry] >> 22) & 7, m_pagemap[entry], offset<<1);
switch ((m_pagemap[entry] >> 22) & 7)
{
@ -444,7 +444,7 @@ WRITE16_MEMBER( sun2_state::tl_mmu_w )
}
else
{
if (!space.debugger_access()) printf("sun2: pagemap entry not valid!\n");
if (!machine().side_effect_disabled()) printf("sun2: pagemap entry not valid!\n");
}
printf("sun2: Unmapped write %04x (FC %d, mask %04x, PC=%x) to %08x\n", data, fc, mem_mask, m_maincpu->pc, offset<<1);

14
src/mame/drivers/sun3.cpp
View File

@ -392,7 +392,7 @@ READ32_MEMBER( sun3_state::tl_mmu_r )
{
uint8_t fc = m_maincpu->get_fc();
if ((fc == 3) && !space.debugger_access())
if ((fc == 3) && !machine().side_effect_disabled())
{
int page;
@ -458,7 +458,7 @@ READ32_MEMBER( sun3_state::tl_mmu_r )
}
// debugger hack
if ((space.debugger_access()) && (offset >= (0xfef0000>>2)) && (offset <= (0xfefffff>>2)))
if (machine().side_effect_disabled() && (offset >= (0xfef0000>>2)) && (offset <= (0xfefffff>>2)))
{
return m_rom_ptr[offset & 0x3fff];
}
@ -487,7 +487,7 @@ READ32_MEMBER( sun3_state::tl_mmu_r )
//printf("pmeg %d, entry %d = %08x, virt %08x => tmp %08x\n", pmeg, entry, m_pagemap[entry], offset << 2, tmp);
// if (!space.debugger_access())
// if (!machine().side_effect_disabled())
//printf("sun3: Translated addr: %08x, type %d (page %d page entry %08x, orig virt %08x, FC %d)\n", tmp << 2, (m_pagemap[entry] >> 26) & 3, entry, m_pagemap[entry], offset<<2, fc);
switch ((m_pagemap[entry] >> 26) & 3)
@ -512,7 +512,7 @@ READ32_MEMBER( sun3_state::tl_mmu_r )
}
else
{
// if (!space.debugger_access()) printf("sun3: pagemap entry not valid! (PC=%x)\n", m_maincpu->pc);
// if (!machine().side_effect_disabled()) printf("sun3: pagemap entry not valid! (PC=%x)\n", m_maincpu->pc);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
m_buserr = BE_INVALID;
@ -520,7 +520,7 @@ READ32_MEMBER( sun3_state::tl_mmu_r )
return 0xffffffff;
}
if (!space.debugger_access()) logerror("sun3: Unmapped read @ %08x (FC %d, mask %08x, PC=%x, seg %x)\n", offset<<2, fc, mem_mask, m_maincpu->pc, offset>>15);
if (!machine().side_effect_disabled()) logerror("sun3: Unmapped read @ %08x (FC %d, mask %08x, PC=%x, seg %x)\n", offset<<2, fc, mem_mask, m_maincpu->pc, offset>>15);
return 0xffffffff;
}
@ -638,7 +638,7 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w )
uint32_t tmp = (m_pagemap[entry] & 0x7ffff) << 11;
tmp |= (offset & 0x7ff);
//if (!space.debugger_access()) printf("sun3: Translated addr: %08x, type %d (page entry %08x, orig virt %08x)\n", tmp << 2, (m_pagemap[entry] >> 26) & 3, m_pagemap[entry], offset<<2);
//if (!machine().side_effect_disabled()) printf("sun3: Translated addr: %08x, type %d (page entry %08x, orig virt %08x)\n", tmp << 2, (m_pagemap[entry] >> 26) & 3, m_pagemap[entry], offset<<2);
switch ((m_pagemap[entry] >> 26) & 3)
{
@ -662,7 +662,7 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w )
}
else
{
//if (!space.debugger_access()) printf("sun3: pagemap entry not valid!\n");
//if (!machine().side_effect_disabled()) printf("sun3: pagemap entry not valid!\n");
m_buserr = BE_INVALID;
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);

14
src/mame/drivers/sun4.cpp
View File

@ -716,7 +716,7 @@ uint32_t sun4_state::read_insn_data_4c(uint8_t asi, address_space &space, uint32
}
else
{
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
printf("sun4c: INVALID PTE entry %d %08x accessed! vaddr=%x PC=%x\n", entry, m_pagemap[entry], offset <<2, m_maincpu->pc());
//m_maincpu->trap(SPARC_DATA_ACCESS_EXCEPTION);
@ -783,7 +783,7 @@ READ32_MEMBER( sun4_state::sun4c_mmu_r )
uint32_t retval = 0;
// make debugger fetches emulate supervisor program for best compatibility with boot PROM execution
if (space.debugger_access()) asi = 9;
if (machine().side_effect_disabled()) asi = 9;
// supervisor program fetches in boot state are special
if ((!(m_system_enable & ENA_NOTBOOT)) && (asi == 9))
@ -862,7 +862,7 @@ READ32_MEMBER( sun4_state::sun4c_mmu_r )
return read_insn_data_4c(asi, space, offset, mem_mask);
default:
if (!space.debugger_access()) printf("sun4c: ASI %d unhandled read @ %x (PC=%x)\n", asi, offset<<2, m_maincpu->pc());
if (!machine().side_effect_disabled()) printf("sun4c: ASI %d unhandled read @ %x (PC=%x)\n", asi, offset<<2, m_maincpu->pc());
return 0;
}
@ -1007,7 +1007,7 @@ uint32_t sun4_state::read_insn_data(uint8_t asi, address_space &space, uint32_t
}
else
{
if (!space.debugger_access())
if (!machine().side_effect_disabled())
{
printf("sun4: INVALID PTE entry %d %08x accessed! vaddr=%x PC=%x\n", entry, m_pagemap[entry], offset <<2, m_maincpu->pc());
//m_maincpu->trap(SPARC_DATA_ACCESS_EXCEPTION);
@ -1064,7 +1064,7 @@ READ32_MEMBER( sun4_state::sun4_mmu_r )
int page;
// make debugger fetches emulate supervisor program for best compatibility with boot PROM execution
if (space.debugger_access()) asi = 9;
if (machine().side_effect_disabled()) asi = 9;
// supervisor program fetches in boot state are special
if ((!(m_system_enable & ENA_NOTBOOT)) && (asi == 9))
@ -1143,7 +1143,7 @@ READ32_MEMBER( sun4_state::sun4_mmu_r )
return read_insn_data(asi, space, offset, mem_mask);
default:
if (!space.debugger_access()) printf("sun4: ASI %d unhandled read @ %x (PC=%x)\n", asi, offset<<2, m_maincpu->pc());
if (!machine().side_effect_disabled()) printf("sun4: ASI %d unhandled read @ %x (PC=%x)\n", asi, offset<<2, m_maincpu->pc());
return 0;
}
@ -1478,7 +1478,7 @@ ADDRESS_MAP_END
READ8_MEMBER( sun4_state::fdc_r )
{
if (space.debugger_access())
if (machine().side_effect_disabled())
return 0;
switch(offset)

4
src/mame/drivers/superqix.cpp
View File

@ -407,7 +407,7 @@ WRITE8_MEMBER(superqix_state_base::sqixu_mcu_p2_w)
READ8_MEMBER(superqix_state_base::sqixu_mcu_p3_r)
{
// logerror("%04x: read Z80 command %02x\n",space.device().safe_pc(),m_fromZ80);
if(!space.debugger_access())
if(!machine().side_effect_disabled())
{
m_Z80HasWritten = 0;
}
@ -417,7 +417,7 @@ READ8_MEMBER(superqix_state_base::sqixu_mcu_p3_r)
READ8_MEMBER(superqix_state_base::nmi_ack_r)
{
if(!space.debugger_access())
if(!machine().side_effect_disabled())
{
m_maincpu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
}

26
src/mame/drivers/supracan.cpp
View File

@ -1134,7 +1134,6 @@ ADDRESS_MAP_END
READ8_MEMBER( supracan_state::_6502_soundmem_r )
{
address_space &mem = m_maincpu->space(AS_PROGRAM);
uint8_t data = m_soundram[offset];
switch(offset)
@ -1146,8 +1145,8 @@ READ8_MEMBER( supracan_state::_6502_soundmem_r )
case 0x410: // Sound IRQ enable
data = m_sound_irq_enable_reg;
if(!mem.debugger_access()) verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", 0, "supracan_soundreg_r: IRQ enable: %04x\n", data);
if(!mem.debugger_access())
if(!machine().side_effect_disabled()) verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", 0, "supracan_soundreg_r: IRQ enable: %04x\n", data);
if(!machine().side_effect_disabled())
{
if(m_sound_irq_enable_reg & m_sound_irq_source_reg)
{
@ -1162,17 +1161,17 @@ READ8_MEMBER( supracan_state::_6502_soundmem_r )
case 0x411: // Sound IRQ source
data = m_sound_irq_source_reg;
m_sound_irq_source_reg = 0;
if(!mem.debugger_access()) verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", 3, "supracan_soundreg_r: IRQ source: %04x\n", data);
if(!mem.debugger_access())
if(!machine().side_effect_disabled()) verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", 3, "supracan_soundreg_r: IRQ source: %04x\n", data);
if(!machine().side_effect_disabled())
{
m_soundcpu->set_input_line(0, CLEAR_LINE);
}
break;
case 0x420:
if(!mem.debugger_access()) verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", 3, "supracan_soundreg_r: Sound hardware status? (not yet implemented): %02x\n", 0);
if(!machine().side_effect_disabled()) verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", 3, "supracan_soundreg_r: Sound hardware status? (not yet implemented): %02x\n", 0);
break;
case 0x422:
if(!mem.debugger_access()) verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", 3, "supracan_soundreg_r: Sound hardware data? (not yet implemented): %02x\n", 0);
if(!machine().side_effect_disabled()) verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", 3, "supracan_soundreg_r: Sound hardware data? (not yet implemented): %02x\n", 0);
break;
case 0x404:
case 0x405:
@ -1183,7 +1182,7 @@ READ8_MEMBER( supracan_state::_6502_soundmem_r )
default:
if(offset >= 0x300 && offset < 0x500)
{
if(!mem.debugger_access()) verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", 0, "supracan_soundreg_r: Unknown register %04x\n", offset);
if(!machine().side_effect_disabled()) verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", 0, "supracan_soundreg_r: Unknown register %04x\n", offset);
}
break;
}
@ -1460,13 +1459,12 @@ WRITE16_MEMBER( supracan_state::sound_w )
READ16_MEMBER( supracan_state::video_r )
{
address_space &mem = m_maincpu->space(AS_PROGRAM);
uint16_t data = m_video_regs[offset];
switch(offset)
{
case 0x00/2: // Video IRQ flags
if(!mem.debugger_access())
if(!machine().side_effect_disabled())
{
//verboselog("maincpu", 0, "read video IRQ flags (%04x)\n", data);
m_maincpu->set_input_line(7, CLEAR_LINE);
@ -1478,16 +1476,16 @@ READ16_MEMBER( supracan_state::video_r )
//data = 0;
break;
case 0x100/2:
if(!mem.debugger_access()) verboselog("maincpu", 0, "read tilemap_flags[0] (%04x)\n", data);
if(!machine().side_effect_disabled()) verboselog("maincpu", 0, "read tilemap_flags[0] (%04x)\n", data);
break;
case 0x106/2:
if(!mem.debugger_access()) verboselog("maincpu", 0, "read tilemap_scrolly[0] (%04x)\n", data);
if(!machine().side_effect_disabled()) verboselog("maincpu", 0, "read tilemap_scrolly[0] (%04x)\n", data);
break;
case 0x120/2:
if(!mem.debugger_access()) verboselog("maincpu", 0, "read tilemap_flags[1] (%04x)\n", data);
if(!machine().side_effect_disabled()) verboselog("maincpu", 0, "read tilemap_flags[1] (%04x)\n", data);
break;
default:
if(!mem.debugger_access()) verboselog("maincpu", 0, "video_r: Unknown register: %08x (%04x & %04x)\n", 0xf00000 + (offset << 1), data, mem_mask);
if(!machine().side_effect_disabled()) verboselog("maincpu", 0, "video_r: Unknown register: %08x (%04x & %04x)\n", 0xf00000 + (offset << 1), data, mem_mask);
break;
}

2
src/mame/drivers/symbolics.cpp
View File

@ -90,7 +90,7 @@ public:
READ16_MEMBER(symbolics_state::buserror_r)
{
if(!space.debugger_access())
if(!machine().side_effect_disabled())
{
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);

8
src/mame/drivers/ti99_4p.cpp
View File

@ -455,7 +455,7 @@ READ16_MEMBER( ti99_4p_state::memread )
int addr_off8k = m_addr_buf & 0x1fff;
// If we use the debugger, decode the address now (normally done in setaddress)
if (space.debugger_access())
if (machine().side_effect_disabled())
{
m_addr_buf = offset << 1;
m_decode = decode_address(m_addr_buf);
@ -498,7 +498,7 @@ READ16_MEMBER( ti99_4p_state::memread )
break;
case SGCPU_PEB:
if (space.debugger_access()) return debugger_read(space, offset);
if (machine().side_effect_disabled()) return debugger_read(space, offset);
// The byte from the odd address has already been read into the latch
// Reading the even address now
m_peribox->readz(space, m_addr_buf, &hbyte);
@ -516,7 +516,7 @@ WRITE16_MEMBER( ti99_4p_state::memwrite )
int address = 0;
// If we use the debugger, decode the address now (normally done in setaddress)
if (space.debugger_access())
if (machine().side_effect_disabled())
{
m_addr_buf = offset << 1;
m_decode = decode_address(m_addr_buf);
@ -560,7 +560,7 @@ WRITE16_MEMBER( ti99_4p_state::memwrite )
break;
case SGCPU_PEB:
if (space.debugger_access()) { debugger_write(space, offset, data); return; }
if (machine().side_effect_disabled()) { debugger_write(space, offset, data); return; }
// Writing the even address now (addr)
// The databus multiplexer puts the even value into the latch and outputs the odd value now.

2
src/mame/drivers/tk2000.cpp
View File

@ -170,7 +170,7 @@ uint32_t tk2000_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap
// most softswitches don't care about read vs write, so handle them here
void tk2000_state::do_io(address_space &space, int offset)
{
if(space.debugger_access())
if(machine().side_effect_disabled())
{
return;
}

10
src/mame/drivers/vixen.cpp
View File

@ -79,18 +79,14 @@ void vixen_state::update_interrupt()
READ8_MEMBER( vixen_state::opram_r )
{
if (!space.debugger_access())
if (!machine().side_effect_disabled())
membank("bank3")->set_entry(0); // read videoram
bool const prev_debugger_access(m_program->debugger_access());
m_program->set_debugger_access(space.debugger_access());
uint8_t const data(m_program->read_byte(offset));
m_program->set_debugger_access(prev_debugger_access);
return data;
return m_program->read_byte(offset);
}
READ8_MEMBER( vixen_state::oprom_r )
{
if (!space.debugger_access())
if (!machine().side_effect_disabled())
membank("bank3")->set_entry(1); // read rom
return m_rom[offset];
}

2
src/mame/drivers/vt240.cpp
View File

@ -378,7 +378,7 @@ WRITE8_MEMBER(vt240_state::vom_w)
READ16_MEMBER(vt240_state::vram_r)
{
if(!BIT(m_reg0, 3) || space.debugger_access())
if(!BIT(m_reg0, 3) || machine().side_effect_disabled())
{
offset = ((offset & 0x18000) >> 1) | (offset & 0x3fff);
return m_video_ram[offset & 0x7fff];

4
src/mame/drivers/wicat.cpp
View File

@ -400,7 +400,7 @@ WRITE8_MEMBER( wicat_state::via_b_w )
READ16_MEMBER( wicat_state::invalid_r )
{
if(!space.debugger_access())
if(!machine().side_effect_disabled())
{
m_maincpu->set_buserror_details(0x300000+offset*2-2,0,m_maincpu->get_fc());
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
@ -411,7 +411,7 @@ READ16_MEMBER( wicat_state::invalid_r )
WRITE16_MEMBER( wicat_state::invalid_w )
{
if(!space.debugger_access())
if(!machine().side_effect_disabled())
{
m_maincpu->set_buserror_details(0x300000+offset*2-2,1,m_maincpu->get_fc());
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);

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