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ASC: sync with MESS improvements (no whatsnew)

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This commit is contained in:
R. Belmont 2010-10-17 20:15:40 +00:00
parent 1d4ea432e9
commit 0d8e40acb6
2 changed files with 90 additions and 97 deletions
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131
src/emu/sound/asc.c
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@ -18,8 +18,8 @@
0x807: CLOCK RATE (0 = Mac 22257 Hz, 1 = undefined, 2 = 22050 Hz, 3 = 44100 Hz) 0x807: CLOCK RATE (0 = Mac 22257 Hz, 1 = undefined, 2 = 22050 Hz, 3 = 44100 Hz)
0x80a: PLAY REC A 0x80a: PLAY REC A
0x80f: TEST (bits 6-7 = digital test, bits 4-5 = analog test) 0x80f: TEST (bits 6-7 = digital test, bits 4-5 = analog test)
0x810: WAVETABLE 0 PHASE (big-endian 8.16 fixed-point, only 24 bits valid) 0x810: WAVETABLE 0 PHASE (big-endian 9.15 fixed-point, only 24 bits valid)
0x814: WAVETABLE 0 INCREMENT (big-endian 8.16 fixed-point, only 24 bits valid) 0x814: WAVETABLE 0 INCREMENT (big-endian 9.15 fixed-point, only 24 bits valid)
0x818: WAVETABLE 1 PHASE 0x818: WAVETABLE 1 PHASE
0x81C: WAVETABLE 1 INCREMENT 0x81C: WAVETABLE 1 INCREMENT
0x820: WAVETABLE 2 PHASE 0x820: WAVETABLE 2 PHASE
@ -141,11 +141,10 @@ void asc_device::device_reset()
memset(m_fifo_b, 0, sizeof(m_fifo_b)); memset(m_fifo_b, 0, sizeof(m_fifo_b));
memset(m_phase, 0, sizeof(m_phase)); memset(m_phase, 0, sizeof(m_phase));
memset(m_incr, 0, sizeof(m_incr)); memset(m_incr, 0, sizeof(m_incr));
memset(m_fifo_a_wrhalf, 0, sizeof(m_fifo_a_wrhalf));
memset(m_fifo_b_wrhalf, 0, sizeof(m_fifo_b_wrhalf));
m_fifo_a_rdptr = m_fifo_b_rdptr = 0; m_fifo_a_rdptr = m_fifo_b_rdptr = 0;
m_fifo_a_wrptr = m_fifo_b_wrptr = 0; m_fifo_a_wrptr = m_fifo_b_wrptr = 0;
m_fifo_cap_a = m_fifo_cap_b = 0;
} }
//------------------------------------------------- //-------------------------------------------------
@ -161,7 +160,7 @@ STREAM_UPDATE( asc_device::static_stream_generate )
void asc_device::stream_generate(stream_sample_t **inputs, stream_sample_t **outputs, int samples) void asc_device::stream_generate(stream_sample_t **inputs, stream_sample_t **outputs, int samples)
{ {
stream_sample_t *outL, *outR; stream_sample_t *outL, *outR;
int i, ch, halt = 0; int i, ch;
static UINT32 wtoffs[2] = { 0, 0x200 }; static UINT32 wtoffs[2] = { 0, 0x200 };
outL = outputs[0]; outL = outputs[0];
@ -177,34 +176,46 @@ void asc_device::stream_generate(stream_sample_t **inputs, stream_sample_t **out
break; break;
case 1: // FIFO mode case 1: // FIFO mode
if ((m_fifo_a_rdptr == 0) && (!m_fifo_a_wrhalf[0]))
{
halt = 1;
}
else if ((m_fifo_a_rdptr == 0x200) && (!m_fifo_a_wrhalf[1]))
{
halt = 1;
}
for (i = 0; i < samples; i++) for (i = 0; i < samples; i++)
{ {
INT8 smpll, smplr; INT8 smpll, smplr;
if (m_fifo_a_rdptr < 0x200) smpll = (INT8)m_fifo_a[m_fifo_a_rdptr]^0x80;
smplr = (INT8)m_fifo_b[m_fifo_b_rdptr]^0x80;
// don't advance the sample pointer if there are no more samples
if (m_fifo_cap_a)
{ {
m_fifo_a_wrhalf[0] = 0; m_fifo_a_rdptr++;
m_fifo_b_wrhalf[0] = 0; m_fifo_a_rdptr &= 0x3ff;
} m_fifo_cap_a--;
else
{
m_fifo_a_wrhalf[1] = 0;
m_fifo_b_wrhalf[1] = 0;
} }
smpll = (INT8)m_fifo_a[m_fifo_a_rdptr++]^0x80; if (m_fifo_cap_b)
smplr = (INT8)m_fifo_b[m_fifo_b_rdptr++]^0x80; {
m_fifo_b_rdptr++;
m_fifo_b_rdptr &= 0x3ff;
m_fifo_cap_b--;
}
if ((m_fifo_a_rdptr == 0x200) || (m_fifo_a_rdptr == 0x400)) if ((m_fifo_cap_a) || (m_fifo_cap_b))
{
switch (m_chip_type)
{
case ASC_TYPE_SONORA:
if (m_fifo_cap_a <= 0x200)
{
m_regs[R_FIFOSTAT-0x800] |= 0x4; // fifo less than half full
m_regs[R_FIFOSTAT-0x800] |= 0x8; // just pass the damn test
if (m_irq_cb)
{
m_irq_cb(this, 1);
}
}
break;
default:
if (m_fifo_cap_a <= 0x200)
{ {
m_regs[R_FIFOSTAT-0x800] |= 1; // fifo A half-empty m_regs[R_FIFOSTAT-0x800] |= 1; // fifo A half-empty
if (m_irq_cb) if (m_irq_cb)
@ -213,7 +224,8 @@ void asc_device::stream_generate(stream_sample_t **inputs, stream_sample_t **out
} }
} }
if ((m_fifo_b_rdptr == 0x200) || (m_fifo_b_rdptr == 0x400)) // don't update for non-(E)ASC
if (m_fifo_cap_b <= 0x200)
{ {
m_regs[R_FIFOSTAT-0x800] |= 4; // fifo B half-empty m_regs[R_FIFOSTAT-0x800] |= 4; // fifo B half-empty
if (m_irq_cb) if (m_irq_cb)
@ -221,18 +233,13 @@ void asc_device::stream_generate(stream_sample_t **inputs, stream_sample_t **out
m_irq_cb(this, 1); m_irq_cb(this, 1);
} }
} }
break;
m_fifo_a_rdptr &= 0x3ff; }
m_fifo_b_rdptr &= 0x3ff; }
outL[i] = smpll * 64; outL[i] = smpll * 64;
outR[i] = smplr * 64; outR[i] = smplr * 64;
} }
if (halt)
{
// m_regs[R_MODE-0x800] = 0;
}
break; break;
case 2: // wavetable mode case 2: // wavetable mode
@ -250,11 +257,11 @@ void asc_device::stream_generate(stream_sample_t **inputs, stream_sample_t **out
if (ch < 2) if (ch < 2)
{ {
smpl = (INT8)m_fifo_a[((m_phase[ch]>>16)&0x1ff) + wtoffs[ch&1]]; smpl = (INT8)m_fifo_a[((m_phase[ch]>>15)&0x1ff) + wtoffs[ch&1]];
} }
else else
{ {
smpl = (INT8)m_fifo_b[((m_phase[ch]>>16)&0x1ff) + wtoffs[ch&1]]; smpl = (INT8)m_fifo_b[((m_phase[ch]>>15)&0x1ff) + wtoffs[ch&1]];
} }
smpl ^= 0x80; smpl ^= 0x80;
@ -415,24 +422,12 @@ void asc_device::write(UINT16 offset, UINT8 data)
{ {
if (m_regs[R_MODE-0x800] == 1) if (m_regs[R_MODE-0x800] == 1)
{ {
if (m_fifo_a_wrptr < 0x400)
{
m_fifo_a_wrhalf[0] = 1;
}
else
{
m_fifo_a_wrhalf[1] = 1;
}
m_fifo_a[m_fifo_a_wrptr++] = data; m_fifo_a[m_fifo_a_wrptr++] = data;
m_fifo_cap_a++;
if ((m_fifo_a_wrptr == 0x200) || (m_fifo_a_wrptr == 0x400)) if (m_fifo_cap_a == 0x800)
{ {
m_regs[R_FIFOSTAT-0x800] |= 2; // fifo A half-full m_regs[R_FIFOSTAT-0x800] |= 2; // fifo A full
if (m_irq_cb)
{
m_irq_cb(this, 1);
}
} }
m_fifo_a_wrptr &= 0x3ff; m_fifo_a_wrptr &= 0x3ff;
@ -446,24 +441,12 @@ void asc_device::write(UINT16 offset, UINT8 data)
{ {
if (m_regs[R_MODE-0x800] == 1) if (m_regs[R_MODE-0x800] == 1)
{ {
if (m_fifo_b_wrptr < 0x400)
{
m_fifo_b_wrhalf[0] = 1;
}
else
{
m_fifo_b_wrhalf[1] = 1;
}
m_fifo_b[m_fifo_b_wrptr++] = data; m_fifo_b[m_fifo_b_wrptr++] = data;
m_fifo_cap_b++;
if ((m_fifo_a_wrptr == 0x200) || (m_fifo_a_wrptr == 0x400)) if (m_fifo_cap_b == 0x800)
{ {
m_regs[R_FIFOSTAT-0x800] |= 8; // fifo B half-full m_regs[R_FIFOSTAT-0x800] |= 8; // fifo B full
if (m_irq_cb)
{
m_irq_cb(this, 1);
}
} }
m_fifo_b_wrptr &= 0x3ff; m_fifo_b_wrptr &= 0x3ff;
@ -483,11 +466,21 @@ void asc_device::write(UINT16 offset, UINT8 data)
case R_MODE: case R_MODE:
data &= 3; // only bits 0 and 1 can be written data &= 3; // only bits 0 and 1 can be written
memset(m_fifo_a_wrhalf, 0, sizeof(m_fifo_a_wrhalf)); if (data != m_regs[R_MODE-0x800])
memset(m_fifo_b_wrhalf, 0, sizeof(m_fifo_b_wrhalf)); {
m_fifo_a_rdptr = m_fifo_b_rdptr = 0; m_fifo_a_rdptr = m_fifo_b_rdptr = 0;
m_fifo_a_wrptr = m_fifo_b_wrptr = 0; m_fifo_a_wrptr = m_fifo_b_wrptr = 0;
m_fifo_cap_a = m_fifo_cap_b = 0;
}
break;
case R_FIFOMODE:
if (data & 0x80)
{
m_fifo_a_rdptr = m_fifo_b_rdptr = 0;
m_fifo_a_wrptr = m_fifo_b_wrptr = 0;
m_fifo_cap_a = m_fifo_cap_b = 0;
}
break; break;
case R_WTCONTROL: case R_WTCONTROL:

4
src/emu/sound/asc.h
View File

@ -138,13 +138,13 @@ protected:
UINT8 m_fifo_a[0x400]; UINT8 m_fifo_a[0x400];
UINT8 m_fifo_b[0x400]; UINT8 m_fifo_b[0x400];
UINT8 m_regs[0x100]; UINT8 m_regs[0x800];
UINT32 m_phase[4], m_incr[4]; UINT32 m_phase[4], m_incr[4];
int m_fifo_a_rdptr, m_fifo_b_rdptr; int m_fifo_a_rdptr, m_fifo_b_rdptr;
int m_fifo_a_wrptr, m_fifo_b_wrptr; int m_fifo_a_wrptr, m_fifo_b_wrptr;
int m_fifo_a_wrhalf[2], m_fifo_b_wrhalf[2]; int m_fifo_cap_a, m_fifo_cap_b;
}; };