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https://github.com/holub/mame
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video/pc_vga_sis: placeholder for extended clock modes, reformat sequencer logging, extend QA notes
This commit is contained in:
angelosa
parent
a17ea8387c
commit
0def9d44cc
@ -1,15 +1,16 @@
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// license:BSD-3-Clause
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// copyright-holders: Angelo Salese
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/***************************************************************************
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/**************************************************************************************************
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Winbond W83977TF
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TODO:
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- PoC for a generic (LPC) Super I/O type, to be merged with fdc37c93x;
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- savquest (in pciagp) fails keyboard self test (PC=e140c reads bit 0 high
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from port $64?)
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- savquest (in pciagp) fails keyboard self test
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\- bp e140c,1,{eax&=~1;g} bit 0 stuck high from port $64, "receives" while essentially reading
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status only three times (and port $61 is claimed by PIIX4 for PCI SERR# read only)
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***************************************************************************/
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**************************************************************************************************/
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#include "emu.h"
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#include "machine/w83977tf.h"
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@ -373,7 +374,7 @@ void w83977tf_device::mouse_irq_w(offs_t offset, u8 data)
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u8 w83977tf_device::keybc_status_r(offs_t offset)
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{
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return (m_kbdc->data_r(4) & 0xfb) | 0x10; // bios needs bit 2 to be 0 as powerup and bit 4 to be 1
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return (m_kbdc->data_r(4) & 0xff);
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}
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void w83977tf_device::keybc_command_w(offs_t offset, u8 data)
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@ -544,7 +544,7 @@ void cirrus_gd5428_device::sequencer_map(address_map &map)
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NAME([this] (offs_t offset, u8 data) {
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// TODO: bebox startup enables this
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if((data & 0xf0) != 0)
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popmessage("1MB framebuffer window enabled at %iMB (%02x)",data >> 4,data);
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popmessage("pc_vga_cirrus: 1MB framebuffer window enabled at %iMB (%02x)",data >> 4,data);
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vga.sequencer.data[0x07] = data;
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cirrus_define_video_mode();
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})
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@ -812,7 +812,7 @@ void cirrus_gd5428_device::cirrus_define_video_mode()
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{
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// TODO: needs subclassing, earlier chips don't have all of these modes
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if (BIT(m_hidden_dac_mode, 4))
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popmessage("Cirrus: Unsupported mixed 5-5-5 / 8bpp mode selected");
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popmessage("pc_vga_cirrus: Unsupported mixed 5-5-5 / 8bpp mode selected");
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switch(m_hidden_dac_mode & 0x4f)
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{
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case 0x00:
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@ -827,23 +827,24 @@ void cirrus_gd5428_device::cirrus_define_video_mode()
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case 0x44: // YUV411 8-bit
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case 0x4a: // 16bpp + YUV422 overlay
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case 0x4b: // 16bpp + YUV411 overlay
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popmessage("Cirrus: CL-GD545 YUV mode selected %02x", m_hidden_dac_mode);
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popmessage("pc_vga_cirrus: CL-GD545 YUV mode selected %02x", m_hidden_dac_mode);
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break;
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case 0x45:
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svga.rgb24_en = 1;
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break;
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case 0x46:
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case 0x47:
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popmessage("Cirrus: CL-GD545+ DAC power down selected %02x", m_hidden_dac_mode);
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popmessage("pc_vga_cirrus: CL-GD545+ DAC power down selected %02x", m_hidden_dac_mode);
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break;
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case 0x48:
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popmessage("Cirrus: CL-GD545+ 8-bit grayscale selected");
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popmessage("pc_vga_cirrus: CL-GD545+ 8-bit grayscale selected");
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break;
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case 0x49:
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svga.rgb8_en = 1;
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break;
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default:
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popmessage("Cirrus: reserved mode selected %02x", m_hidden_dac_mode);
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// TODO: 0xff in pciagp (alias for a DAC power down?)
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popmessage("pc_vga_cirrus: reserved mode selected %02x", m_hidden_dac_mode);
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break;
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}
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}
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@ -1118,7 +1119,7 @@ void cirrus_gd5428_device::copy_pixel(uint8_t src, uint8_t dst)
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res = src ^ dst;
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break;
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default:
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popmessage("CL: Unsupported BitBLT ROP mode %02x",m_blt_rop);
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popmessage("pc_vga_cirrus: Unsupported BitBLT ROP mode %02x",m_blt_rop);
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}
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// handle transparency compare
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@ -1146,11 +1147,11 @@ uint8_t cirrus_gd5428_device::vga_latch_write(int offs, uint8_t data)
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break;
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case 4:
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res = vga.gc.latch[offs];
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popmessage("CL: Unimplemented VGA write mode 4 enabled");
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popmessage("pc_vga_cirrus: Unimplemented VGA write mode 4 enabled");
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break;
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case 5:
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res = vga.gc.latch[offs];
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popmessage("CL: Unimplemented VGA write mode 5 enabled");
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popmessage("pc_vga_cirrus: Unimplemented VGA write mode 5 enabled");
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break;
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}
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@ -2,11 +2,23 @@
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// copyright-holders:Angelo Salese
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/**************************************************************************************************
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Implementation of SiS family (S)VGA chipset
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Implementation of SiS family (S)VGA chipset (SiS630)
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VBE 3.0, Multi Buffering & Virtual Scrolling available
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TODO:
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- interlace (cfr. xubuntu 6.10 splash screen on 1024x768x32);
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- backport to earlier variants;
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- Refresh rate for extended modes;
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- interlace;
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- linear addressing;
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- HW cursor;
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- Output scaling, cfr. xubuntu 6.10 splash screen at 1024x768x32;
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- Interrupts;
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- Dual segment;
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- AGP/HostBus/Turbo Queue i/f;
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- 2D/3D pipeline;
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- DDC;
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- Bridge with a secondary TV out (SiS301);
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- Verify matches with other SiS PCI cards, backport;
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**************************************************************************************************/
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@ -17,6 +29,7 @@ TODO:
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#define VERBOSE (LOG_GENERAL)
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//#define LOG_OUTPUT_FUNC osd_printf_info
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#include "logmacro.h"
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// TODO: later variant of 5598
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@ -90,17 +103,19 @@ void sis630_svga_device::crtc_map(address_map &map)
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map(0x26, 0x26).lr8(
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NAME([this] (offs_t offset) { return vga.attribute.index; })
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);
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// TODO: very preliminary, undocumented stuff
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// TODO: very preliminary, this section is undocumented in '630 doc
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map(0x30, 0xff).lrw8(
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NAME([this] (offs_t offset) {
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return vga.crtc.data[offset];
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}),
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NAME([this] (offs_t offset, u8 data) {
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// TODO: if one of these is 0xff then it enables a single port transfer to $b8000
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// Older style MMIO?
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vga.crtc.data[offset] = data;
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})
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);
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// make sure '301 CRT2 is not enabled for now
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// TODO: BeMAME (0.36b5) under BeOS 5.0 detects a secondary monitor by default anyway
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map(0x30, 0x30).lr8(
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NAME([] (offs_t offset) { return 0; })
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);
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@ -123,7 +138,7 @@ void sis630_svga_device::sequencer_map(address_map &map)
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NAME([this] (offs_t offset, u8 data) {
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// TODO: reimplement me thru memory_view or direct handler override
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m_unlock_reg = (data == 0x86);
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LOG("Unlock register write %02x (%s)\n", data, m_unlock_reg ? "unlocked" : "locked");
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//LOG("SR5: Unlock register write %02x (%s)\n", data, m_unlock_reg ? "unlocked" : "locked");
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})
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);
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/*
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@ -142,7 +157,7 @@ void sis630_svga_device::sequencer_map(address_map &map)
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}),
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NAME([this] (offs_t offset, u8 data) {
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m_ramdac_mode = data;
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LOG("RAMDAC mode %02x\n", data);
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LOG("SR06: RAMDAC mode %02x\n", data);
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if (!BIT(data, 1))
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{
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@ -163,17 +178,18 @@ void sis630_svga_device::sequencer_map(address_map &map)
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return m_ext_misc_ctrl_0;
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}),
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NAME([this] (offs_t offset, u8 data) {
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LOG("Extended Misc. Control register 0 SR07 %02x\n", data);
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LOG("SR07: Extended Misc. Control 0 %02x\n", data);
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m_ext_misc_ctrl_0 = data;
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std::tie(svga.rgb24_en, svga.rgb32_en) = flush_true_color_mode();
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})
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);
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//map(0x08, 0x09) CRT threshold
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map(0x0a, 0x0a).lrw8(
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NAME([this] (offs_t offset) {
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return m_ext_vert_overflow;
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}),
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NAME([this] (offs_t offset, u8 data) {
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LOG("Extended vertical Overflow register SR0A %02x\n", data);
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LOG("SR0A: Extended Vertical Overflow %02x\n", data);
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m_ext_vert_overflow = data;
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vga.crtc.vert_retrace_end = (vga.crtc.vert_retrace_end & 0xf) | ((data & 0x20) >> 1);
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vga.crtc.vert_blank_end = (vga.crtc.vert_blank_end & 0x00ff) | ((data & 0x10) << 4);
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@ -192,7 +208,7 @@ void sis630_svga_device::sequencer_map(address_map &map)
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map(0x0b, 0x0b).lw8(
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NAME([this] (offs_t offset, u8 data) {
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//m_dual_seg_mode = bool(BIT(data, 3));
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LOG("Extended horizontal Overflow 1 SR0B %02x\n", data);
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LOG("SR0B: Extended Horizontal Overflow 1 %02x\n", data);
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m_ext_horz_overflow[0] = data;
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vga.crtc.horz_retrace_start = (vga.crtc.horz_retrace_start & 0x00ff) | ((data & 0xc0) << 2);
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@ -205,7 +221,7 @@ void sis630_svga_device::sequencer_map(address_map &map)
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);
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map(0x0c, 0x0c).lw8(
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NAME([this] (offs_t offset, u8 data) {
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LOG("Extended horizontal Overflow 2 SR0C %02x\n", data);
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LOG("SR0C: Extended Horizontal Overflow 2 %02x\n", data);
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m_ext_horz_overflow[1] = data;
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vga.crtc.horz_retrace_end = (vga.crtc.horz_retrace_end & 0x001f) | ((data & 0x04) << 3);
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@ -218,18 +234,21 @@ void sis630_svga_device::sequencer_map(address_map &map)
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return vga.crtc.start_addr_latch >> 16;
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}),
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NAME([this] (offs_t offset, u8 data) {
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LOG("Extended starting address register SR0D %02x\n", data);
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LOG("SR0D: Extended Starting Address %02x\n", data);
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vga.crtc.start_addr_latch &= ~0xff0000;
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vga.crtc.start_addr_latch |= data << 16;
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})
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);
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map(0x0e, 0x0e).lw8(
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NAME([this] (offs_t offset, u8 data) {
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LOG("Extended pitch register SR0E %02x\n", data);
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LOG("SR0E: Extended pitch register %02x\n", data);
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// sis_main.c implicitly sets this with bits 0-3 granularity, assume being right
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vga.crtc.offset = (vga.crtc.offset & 0x00ff) | ((data & 0x0f) << 8);
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})
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);
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//map(0x0f, 0x0f) CRT misc. control
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//map(0x10, 0x10) Display line width register
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//map(0x11, 0x11) DDC register
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map(0x14, 0x14).lrw8(
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NAME([this] (offs_t offset) {
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// sis_main.c calculates VRAM size in two ways:
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@ -242,21 +261,80 @@ void sis630_svga_device::sequencer_map(address_map &map)
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return (m_bus_width) | ((vga.svga_intf.vram_size / (1024 * 1024) - 1) & 0x3f);
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}),
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NAME([this] (offs_t offset, u8 data) {
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LOG("SR14: <unknown> %02x\n", data);
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m_bus_width = data & 0xc0;
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})
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);
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//map(0x1d, 0x1d) Segment Selection Overflow
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map(0x1e, 0x1e).lw8(
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NAME([this] (offs_t offset, u8 data) {
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if (BIT(data, 6))
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popmessage("Warning: enable 2d engine");
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popmessage("pc_vga_sis: enable 2d engine");
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})
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);
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//map(0x1f, 0x1f) Power management
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map(0x20, 0x20).lw8(
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NAME([this] (offs_t offset, u8 data) {
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// GUI address decoder setting
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if (data & 0x81)
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popmessage("Warning: %s %s", BIT(data, 7) ? "PCI address enabled" : "", BIT(data, 0) ? "memory map I/O enable" : "");
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popmessage("pc_vga_sis: SR20 %s %s", BIT(data, 7) ? "PCI address enabled" : "", BIT(data, 0) ? "memory map I/O enable" : "");
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})
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);
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//map(0x21, 0x21) GUI HostBus state machine setting
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//map(0x22, 0x22) GUI HostBus controller timing
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//map(0x23, 0x23) GUI HostBus timer
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//map(0x26, 0x26) Turbo Queue base address
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//map(0x27, 0x27) Turbo Queue control
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map(0x2b, 0x2d).lrw8(
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NAME([this] (offs_t offset) {
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return m_ext_dclk[offset];
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}),
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NAME([this] (offs_t offset, u8 data) {
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LOG("SR%02X: Extended DCLK %02x\n", offset + 0x2b, data);
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m_ext_dclk[offset] = data;
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recompute_params();
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})
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);
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map(0x2e, 0x30).lrw8(
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NAME([this] (offs_t offset) {
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return m_ext_eclk[offset];
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}),
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NAME([this] (offs_t offset, u8 data) {
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LOG("SR%02X: Extended ECLK %02x\n", offset + 0x2e, data);
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m_ext_eclk[offset] = data;
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recompute_params();
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})
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);
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map(0x31, 0x31).lrw8(
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NAME([this] (offs_t offset) {
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return m_ext_clock_gen;
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}),
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NAME([this] (offs_t offset, u8 data) {
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LOG("SR31: Extended clock generator misc. %02x\n", data);
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m_ext_clock_gen = data;
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recompute_params();
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})
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);
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map(0x32, 0x32).lrw8(
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NAME([this] (offs_t offset) {
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return m_ext_clock_source_select;
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}),
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NAME([this] (offs_t offset, u8 data) {
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LOG("SR32: Extended clock source selection %02x\n", data);
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m_ext_clock_source_select = data;
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recompute_params();
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})
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);
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//map(0x34, 0x34) Interrupt status
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//map(0x35, 0x35) Interrupt enable
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//map(0x36, 0x36) Interrupt reset
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//map(0x38, 0x3a) Power on trapping
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//map(0x3c, 0x3c) Synchronous reset
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//map(0x3d, 0x3d) Test enable
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}
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std::tuple<u8, u8> sis630_svga_device::flush_true_color_mode()
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@ -272,8 +350,21 @@ std::tuple<u8, u8> sis630_svga_device::flush_true_color_mode()
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void sis630_svga_device::recompute_params()
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{
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// TODO: ext clock
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recompute_params_clock(1, XTAL(25'174'800).value());
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u8 xtal_select = (vga.miscellaneous_output & 0x0c) >> 2;
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int xtal;
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switch(xtal_select & 3)
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{
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case 0: xtal = XTAL(25'174'800).value(); break;
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case 1: xtal = XTAL(28'636'363).value(); break;
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// TODO: stub, barely enough to make BeOS 5 to set ~60 Hz for 640x480x16
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case 2:
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default:
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xtal = XTAL(25'174'800).value();
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break;
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}
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recompute_params_clock(1, xtal);
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}
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uint16_t sis630_svga_device::offset()
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@ -33,6 +33,10 @@ protected:
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u8 m_ext_vert_overflow = 0;
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u8 m_ext_horz_overflow[2]{};
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u8 m_bus_width = 0;
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u8 m_ext_dclk[3]{};
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u8 m_ext_eclk[3]{};
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u8 m_ext_clock_gen = 0;
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u8 m_ext_clock_source_select = 0;
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bool m_unlock_reg = false;
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std::tuple<u8, u8> flush_true_color_mode();
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