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Removed more cpunum_get_active().

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This commit is contained in:
Aaron Giles 2008-11-26 20:07:20 +00:00
parent c2ca1ef0cb
commit 0df0ba2bc4
15 changed files with 222 additions and 249 deletions
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26
src/emu/cpu/saturn/satops.c
View File

@ -1,7 +1,7 @@
#define IRQ_ADDRESS 0xf #define IRQ_ADDRESS 0xf
#define saturn_assert(x) \ #define saturn_assert(x) \
do { if (!(x)) logerror("SATURN%d assertion failed: %s at %s:%i, pc=%05x\n", cpunum_get_active(), #x, __FILE__, __LINE__, saturn.pc); } while (0) do { if (!(x)) logerror("SATURN '%s' assertion failed: %s at %s:%i, pc=%05x\n", saturn.device->tag, #x, __FILE__, __LINE__, saturn.pc); } while (0)
INLINE int READ_OP(void) INLINE int READ_OP(void)
{ {
@ -186,24 +186,24 @@ INLINE void saturn_push(SaturnAdr adr)
INLINE void saturn_interrupt_on(void) INLINE void saturn_interrupt_on(void)
{ {
LOG(( "SATURN#%d at %05x: INTON\n", cpunum_get_active(), saturn.pc-4 )); LOG(( "SATURN '%s' at %05x: INTON\n", saturn.device->tag, saturn.pc-4 ));
saturn.irq_enable=1; saturn.irq_enable=1;
if (saturn.irq_state) if (saturn.irq_state)
{ {
LOG(( "SATURN#%d set_irq_line(ASSERT)\n", cpunum_get_active())); LOG(( "SATURN '%s' set_irq_line(ASSERT)\n", saturn.device->tag));
saturn.pending_irq=1; saturn.pending_irq=1;
} }
} }
INLINE void saturn_interrupt_off(void) INLINE void saturn_interrupt_off(void)
{ {
LOG(( "SATURN#%d at %05x: INTOFF\n", cpunum_get_active(), saturn.pc-4 )); LOG(( "SATURN '%s' at %05x: INTOFF\n", saturn.device->tag, saturn.pc-4 ));
saturn.irq_enable=0; saturn.irq_enable=0;
} }
INLINE void saturn_reset_interrupt(void) INLINE void saturn_reset_interrupt(void)
{ {
LOG(( "SATURN#%d at %05x: RSI\n", cpunum_get_active(), saturn.pc-5 )); LOG(( "SATURN '%s' at %05x: RSI\n", saturn.device->tag, saturn.pc-5 ));
if (saturn.config&&saturn.config->rsi) saturn.config->rsi(Machine); if (saturn.config&&saturn.config->rsi) saturn.config->rsi(Machine);
} }
@ -236,27 +236,27 @@ INLINE void saturn_shutdown(void)
{ {
saturn.sleeping=1; saturn.sleeping=1;
saturn.irq_enable=1; saturn.irq_enable=1;
LOG(( "SATURN#%d at %05x: SHUTDN\n", cpunum_get_active(), saturn.pc-3 )); LOG(( "SATURN '%s' at %05x: SHUTDN\n", saturn.device->tag, saturn.pc-3 ));
} }
INLINE void saturn_bus_command_b(void) INLINE void saturn_bus_command_b(void)
{ {
logerror( "SATURN#%d at %05x: BUSCB opcode not handled\n", cpunum_get_active(), saturn.pc-4 ); logerror( "SATURN '%s' at %05x: BUSCB opcode not handled\n", saturn.device->tag, saturn.pc-4 );
} }
INLINE void saturn_bus_command_c(void) INLINE void saturn_bus_command_c(void)
{ {
logerror( "SATURN#%d at %05x: BUSCC opcode not handled\n", cpunum_get_active(), saturn.pc-3 ); logerror( "SATURN '%s' at %05x: BUSCC opcode not handled\n", saturn.device->tag, saturn.pc-3 );
} }
INLINE void saturn_bus_command_d(void) INLINE void saturn_bus_command_d(void)
{ {
logerror( "SATURN#%d at %05x: BUSCD opcode not handled\n", cpunum_get_active(), saturn.pc-4 ); logerror( "SATURN '%s' at %05x: BUSCD opcode not handled\n", saturn.device->tag, saturn.pc-4 );
} }
INLINE void saturn_serial_request(void) INLINE void saturn_serial_request(void)
{ {
logerror( "SATURN#%d at %05x: SREQ? opcode not handled\n", cpunum_get_active(), saturn.pc-3 ); logerror( "SATURN '%s' at %05x: SREQ? opcode not handled\n", saturn.device->tag, saturn.pc-3 );
} }
INLINE void saturn_out_c(void) INLINE void saturn_out_c(void)
@ -278,8 +278,8 @@ INLINE void saturn_in(int reg)
int in = 0; int in = 0;
saturn_assert(reg>=0 && reg<9); saturn_assert(reg>=0 && reg<9);
if (!(saturn.pc&1)) if (!(saturn.pc&1))
logerror( "SATURN#%d at %05x: reg=IN opcode at odd addresse\n", logerror( "SATURN '%s' at %05x: reg=IN opcode at odd addresse\n",
cpunum_get_active(), saturn.pc-3 ); saturn.device->tag, saturn.pc-3 );
if (saturn.config&&saturn.config->in) in = saturn.config->in(Machine); if (saturn.config&&saturn.config->in) in = saturn.config->in(Machine);
S64_WRITE_WORD(reg,in); S64_WRITE_WORD(reg,in);
monitor_in = in; monitor_in = in;
@ -463,7 +463,7 @@ INLINE void saturn_return_carry_clear(void)
INLINE void saturn_return_interrupt(void) INLINE void saturn_return_interrupt(void)
{ {
LOG(( "SATURN#%d at %05x: RTI\n", cpunum_get_active(), saturn.pc-2 )); LOG(( "SATURN '%s' at %05x: RTI\n", saturn.device->tag, saturn.pc-2 ));
saturn.in_irq=0; /* set to 1 when an IRQ is taken */ saturn.in_irq=0; /* set to 1 when an IRQ is taken */
saturn.pc=saturn_pop(); saturn.pc=saturn_pop();
// saturn_ICount-=10; // saturn_ICount-=10;

16
src/emu/cpu/saturn/sattable.c
View File

@ -37,26 +37,26 @@ static const int sub_right[]={B,C,A,C, I,I,I,I, A,B,C,D, B,C,A,C};
static void saturn_invalid3( int op1, int op2, int op3 ) static void saturn_invalid3( int op1, int op2, int op3 )
{ {
logerror( "SATURN#%d invalid opcode %x%x%x at %05x\n", logerror( "SATURN '%s' invalid opcode %x%x%x at %05x\n",
cpunum_get_active(), op1, op2, op3, saturn.pc-3 ); saturn.device->tag, op1, op2, op3, saturn.pc-3 );
} }
static void saturn_invalid4( int op1, int op2, int op3, int op4 ) static void saturn_invalid4( int op1, int op2, int op3, int op4 )
{ {
logerror( "SATURN#%d invalid opcode %x%x%x%x at %05x\n", logerror( "SATURN '%s' invalid opcode %x%x%x%x at %05x\n",
cpunum_get_active(), op1, op2, op3, op4, saturn.pc-4 ); saturn.device->tag, op1, op2, op3, op4, saturn.pc-4 );
} }
static void saturn_invalid5( int op1, int op2, int op3, int op4, int op5 ) static void saturn_invalid5( int op1, int op2, int op3, int op4, int op5 )
{ {
logerror( "SATURN#%d invalid opcode %x%x%x%x%x at %05x\n", logerror( "SATURN '%s' invalid opcode %x%x%x%x%x at %05x\n",
cpunum_get_active(), op1, op2, op3, op4, op5, saturn.pc-5 ); saturn.device->tag, op1, op2, op3, op4, op5, saturn.pc-5 );
} }
static void saturn_invalid6( int op1, int op2, int op3, int op4, int op5, int op6 ) static void saturn_invalid6( int op1, int op2, int op3, int op4, int op5, int op6 )
{ {
logerror( "SATURN#%d invalid opcode %x%x%x%x%x%x at %05x\n", logerror( "SATURN '%s' invalid opcode %x%x%x%x%x%x at %05x\n",
cpunum_get_active(), op1, op2, op3, op4, op5, op6, saturn.pc-6 ); saturn.device->tag, op1, op2, op3, op4, op5, op6, saturn.pc-6 );
} }

8
src/emu/cpu/saturn/saturn.c
View File

@ -164,7 +164,7 @@ INLINE void saturn_take_irq(void)
saturn_push(saturn.pc); saturn_push(saturn.pc);
saturn.pc=IRQ_ADDRESS; saturn.pc=IRQ_ADDRESS;
LOG(("Saturn#%d takes IRQ ($%04x)\n", cpunum_get_active(), saturn.pc)); LOG(("Saturn '%s' takes IRQ ($%04x)\n", saturn.device->tag, saturn.pc));
if (saturn.irq_callback) (*saturn.irq_callback)(saturn.device, SATURN_IRQ_LINE); if (saturn.irq_callback) (*saturn.irq_callback)(saturn.device, SATURN_IRQ_LINE);
} }
@ -206,7 +206,7 @@ static void saturn_set_nmi_line(int state)
saturn.nmi_state = state; saturn.nmi_state = state;
if ( state != CLEAR_LINE ) if ( state != CLEAR_LINE )
{ {
LOG(( "SATURN#%d set_nmi_line(ASSERT)\n", cpunum_get_active())); LOG(( "SATURN '%s' set_nmi_line(ASSERT)\n", saturn.device->tag));
saturn.pending_irq = 1; saturn.pending_irq = 1;
} }
} }
@ -217,7 +217,7 @@ static void saturn_set_irq_line(int state)
saturn.irq_state = state; saturn.irq_state = state;
if ( state != CLEAR_LINE && saturn.irq_enable ) if ( state != CLEAR_LINE && saturn.irq_enable )
{ {
LOG(( "SATURN#%d set_irq_line(ASSERT)\n", cpunum_get_active())); LOG(( "SATURN '%s' set_irq_line(ASSERT)\n", saturn.device->tag));
saturn.pending_irq = 1; saturn.pending_irq = 1;
} }
} }
@ -226,7 +226,7 @@ static void saturn_set_wakeup_line(int state)
{ {
if (saturn.sleeping && state==1) if (saturn.sleeping && state==1)
{ {
LOG(( "SATURN#%d set_wakeup_line(ASSERT)\n", cpunum_get_active())); LOG(( "SATURN '%s' set_wakeup_line(ASSERT)\n", saturn.device->tag));
if (saturn.irq_callback) (*saturn.irq_callback)(saturn.device, SATURN_WAKEUP_LINE); if (saturn.irq_callback) (*saturn.irq_callback)(saturn.device, SATURN_WAKEUP_LINE);
saturn.sleeping = 0; saturn.sleeping = 0;
} }

2
src/emu/cpu/sh2/sh2.c
View File

@ -2324,7 +2324,7 @@ static CPU_SET_INFO( sh2 )
case CPUINFO_INT_REGISTER + SH2_R15: sh2->r[15] = info->i; break; case CPUINFO_INT_REGISTER + SH2_R15: sh2->r[15] = info->i; break;
case CPUINFO_INT_REGISTER + SH2_EA: sh2->ea = info->i; break; case CPUINFO_INT_REGISTER + SH2_EA: sh2->ea = info->i; break;
case CPUINFO_INT_SH2_FRT_INPUT: sh2_set_frt_input(cpunum_get_active(), info->i); break; case CPUINFO_INT_SH2_FRT_INPUT: sh2_set_frt_input(device, info->i); break;
/* --- the following bits of info are set as pointers to data or functions --- */ /* --- the following bits of info are set as pointers to data or functions --- */
case CPUINFO_PTR_SH2_FTCSR_READ_CALLBACK: sh2->ftcsr_read_callback = (void (*) (UINT32 ))info->f; break; case CPUINFO_PTR_SH2_FTCSR_READ_CALLBACK: sh2->ftcsr_read_callback = (void (*) (UINT32 ))info->f; break;

28
src/emu/cpu/sh2/sh2comn.c
View File

@ -363,7 +363,7 @@ WRITE32_HANDLER( sh2_internal_w )
{ {
INT32 a = sh2->m[0x41]; INT32 a = sh2->m[0x41];
INT32 b = sh2->m[0x40]; INT32 b = sh2->m[0x40];
LOG(("SH2 #%d div+mod %d/%d\n", cpunum_get_active(), a, b)); LOG(("SH2 '%s' div+mod %d/%d\n", sh2->device->tag, a, b));
if (b) if (b)
{ {
sh2->m[0x45] = a / b; sh2->m[0x45] = a / b;
@ -391,7 +391,7 @@ WRITE32_HANDLER( sh2_internal_w )
{ {
INT64 a = sh2->m[0x45] | ((UINT64)(sh2->m[0x44]) << 32); INT64 a = sh2->m[0x45] | ((UINT64)(sh2->m[0x44]) << 32);
INT64 b = (INT32)sh2->m[0x40]; INT64 b = (INT32)sh2->m[0x40];
LOG(("SH2 #%d div+mod %lld/%lld\n", cpunum_get_active(), a, b)); LOG(("SH2 '%s' div+mod %lld/%lld\n", sh2->device->tag, a, b));
if (b) if (b)
{ {
INT64 q = a / b; INT64 q = a / b;
@ -503,16 +503,16 @@ READ32_HANDLER( sh2_internal_r )
return sh2->m[offset]; return sh2->m[offset];
} }
void sh2_set_frt_input(int cpunum, int state) void sh2_set_frt_input(const device_config *device, int state)
{ {
if(state == PULSE_LINE) if(state == PULSE_LINE)
{ {
sh2_set_frt_input(cpunum, ASSERT_LINE); sh2_set_frt_input(device, ASSERT_LINE);
sh2_set_frt_input(cpunum, CLEAR_LINE); sh2_set_frt_input(device, CLEAR_LINE);
return; return;
} }
cpu_push_context(Machine->cpu[cpunum]); cpu_push_context(device);
if(sh2->frt_input == state) { if(sh2->frt_input == state) {
cpu_pop_context(); cpu_pop_context();
@ -551,11 +551,11 @@ void sh2_set_irq_line(int irqline, int state)
if( state == CLEAR_LINE ) if( state == CLEAR_LINE )
{ {
LOG(("SH-2 #%d cleared nmi\n", cpunum_get_active())); LOG(("SH-2 '%s' cleared nmi\n", sh2->device->tag));
} }
else else
{ {
LOG(("SH-2 #%d assert nmi\n", cpunum_get_active())); LOG(("SH-2 '%s' assert nmi\n", sh2->device->tag));
sh2_exception("Set IRQ line", 16); sh2_exception("Set IRQ line", 16);
@ -572,12 +572,12 @@ void sh2_set_irq_line(int irqline, int state)
if( state == CLEAR_LINE ) if( state == CLEAR_LINE )
{ {
LOG(("SH-2 #%d cleared irq #%d\n", cpunum_get_active(), irqline)); LOG(("SH-2 '%s' cleared irq #%d\n", sh2->device->tag, irqline));
sh2->pending_irq &= ~(1 << irqline); sh2->pending_irq &= ~(1 << irqline);
} }
else else
{ {
LOG(("SH-2 #%d assert irq #%d\n", cpunum_get_active(), irqline)); LOG(("SH-2 '%s' assert irq #%d\n", sh2->device->tag, irqline));
sh2->pending_irq |= 1 << irqline; sh2->pending_irq |= 1 << irqline;
#ifdef USE_SH2DRC #ifdef USE_SH2DRC
sh2->test_irq = 1; sh2->test_irq = 1;
@ -648,27 +648,27 @@ void sh2_exception(const char *message, int irqline)
if (sh2->internal_irq_level == irqline) if (sh2->internal_irq_level == irqline)
{ {
vector = sh2->internal_irq_vector; vector = sh2->internal_irq_vector;
LOG(("SH-2 #%d exception #%d (internal vector: $%x) after [%s]\n", cpunum_get_active(), irqline, vector, message)); LOG(("SH-2 '%s' exception #%d (internal vector: $%x) after [%s]\n", sh2->device->tag, irqline, vector, message));
} }
else else
{ {
if(sh2->m[0x38] & 0x00010000) if(sh2->m[0x38] & 0x00010000)
{ {
vector = sh2->irq_callback(sh2->device, irqline); vector = sh2->irq_callback(sh2->device, irqline);
LOG(("SH-2 #%d exception #%d (external vector: $%x) after [%s]\n", cpunum_get_active(), irqline, vector, message)); LOG(("SH-2 '%s' exception #%d (external vector: $%x) after [%s]\n", sh2->device->tag, irqline, vector, message));
} }
else else
{ {
sh2->irq_callback(sh2->device, irqline); sh2->irq_callback(sh2->device, irqline);
vector = 64 + irqline/2; vector = 64 + irqline/2;
LOG(("SH-2 #%d exception #%d (autovector: $%x) after [%s]\n", cpunum_get_active(), irqline, vector, message)); LOG(("SH-2 '%s' exception #%d (autovector: $%x) after [%s]\n", sh2->device->tag, irqline, vector, message));
} }
} }
} }
else else
{ {
vector = 11; vector = 11;
LOG(("SH-2 #%d nmi exception (autovector: $%x) after [%s]\n", cpunum_get_active(), vector, message)); LOG(("SH-2 '%s' nmi exception (autovector: $%x) after [%s]\n", sh2->device->tag, vector, message));
} }
#ifdef USE_SH2DRC #ifdef USE_SH2DRC

2
src/emu/cpu/sh2/sh2comn.h
View File

@ -177,7 +177,7 @@ TIMER_CALLBACK( sh2_dmac_callback );
void sh2_common_init(int alloc, const device_config *device, int index, int clock, cpu_irq_callback irqcallback); void sh2_common_init(int alloc, const device_config *device, int index, int clock, cpu_irq_callback irqcallback);
void sh2_recalc_irq(void); void sh2_recalc_irq(void);
void sh2_set_irq_line(int irqline, int state); void sh2_set_irq_line(int irqline, int state);
void sh2_set_frt_input(int cpunum, int state); void sh2_set_frt_input(const device_config *device, int state);
void sh2_exception(const char *message, int irqline); void sh2_exception(const char *message, int irqline);
#endif /* __SH2COMN_H__ */ #endif /* __SH2COMN_H__ */

2
src/emu/cpu/sh2/sh2drc.c
View File

@ -3389,7 +3389,7 @@ static CPU_SET_INFO( sh2 )
case CPUINFO_INT_REGISTER + SH2_R15: sh2->r[15] = info->i; break; case CPUINFO_INT_REGISTER + SH2_R15: sh2->r[15] = info->i; break;
case CPUINFO_INT_REGISTER + SH2_EA: sh2->ea = info->i; break; case CPUINFO_INT_REGISTER + SH2_EA: sh2->ea = info->i; break;
case CPUINFO_INT_SH2_FRT_INPUT: sh2_set_frt_input(cpunum_get_active(), info->i); break; case CPUINFO_INT_SH2_FRT_INPUT: sh2_set_frt_input(device, info->i); break;
/* --- the following bits of info are set as pointers to data or functions --- */ /* --- the following bits of info are set as pointers to data or functions --- */
case CPUINFO_PTR_SH2_FTCSR_READ_CALLBACK: sh2->ftcsr_read_callback = (void (*) (UINT32 ))info->f; break; case CPUINFO_PTR_SH2_FTCSR_READ_CALLBACK: sh2->ftcsr_read_callback = (void (*) (UINT32 ))info->f; break;

4
src/emu/cpu/sh4/sh4.c
View File

@ -3609,8 +3609,8 @@ static CPU_SET_INFO( sh4 )
case CPUINFO_STR_REGISTER + SH4_XF15: sh4.xf[15] = info->i; break; case CPUINFO_STR_REGISTER + SH4_XF15: sh4.xf[15] = info->i; break;
#endif #endif
case CPUINFO_INT_SH4_IRLn_INPUT: sh4_set_irln_input(cpunum_get_active(), info->i); break; case CPUINFO_INT_SH4_IRLn_INPUT: sh4_set_irln_input(device, info->i); break;
case CPUINFO_INT_SH4_FRT_INPUT: sh4_set_frt_input(cpunum_get_active(), info->i); break; case CPUINFO_INT_SH4_FRT_INPUT: sh4_set_frt_input(device, info->i); break;
/* --- the following bits of info are set as pointers to data or functions --- */ /* --- the following bits of info are set as pointers to data or functions --- */
case CPUINFO_PTR_SH4_FTCSR_READ_CALLBACK: sh4.ftcsr_read_callback = (void (*) (UINT32 ))info->f; break; case CPUINFO_PTR_SH4_FTCSR_READ_CALLBACK: sh4.ftcsr_read_callback = (void (*) (UINT32 ))info->f; break;

26
src/emu/cpu/sh4/sh4comn.c
View File

@ -173,7 +173,7 @@ void sh4_exception(const char *message, int exception) // handle exception
sh4.m[INTEVT] = 0x1c0; sh4.m[INTEVT] = 0x1c0;
vector = 0x600; vector = 0x600;
sh4.irq_callback(sh4.device, INPUT_LINE_NMI); sh4.irq_callback(sh4.device, INPUT_LINE_NMI);
LOG(("SH-4 #%d nmi exception after [%s]\n", cpunum_get_active(), message)); LOG(("SH-4 '%s' nmi exception after [%s]\n", sh4.device->tag, message));
} else { } else {
// if ((sh4.m[ICR] & 0x4000) && (sh4.nmi_line_state == ASSERT_LINE)) // if ((sh4.m[ICR] & 0x4000) && (sh4.nmi_line_state == ASSERT_LINE))
// return; // return;
@ -187,7 +187,7 @@ void sh4_exception(const char *message, int exception) // handle exception
sh4.irq_callback(sh4.device, SH4_INTC_IRL0-exception+SH4_IRL0); sh4.irq_callback(sh4.device, SH4_INTC_IRL0-exception+SH4_IRL0);
else else
sh4.irq_callback(sh4.device, SH4_IRL3+1); sh4.irq_callback(sh4.device, SH4_IRL3+1);
LOG(("SH-4 #%d interrupt exception #%d after [%s]\n", cpunum_get_active(), exception, message)); LOG(("SH-4 '%s' interrupt exception #%d after [%s]\n", sh4.device->tag, exception, message));
} }
sh4_exception_checkunrequest(exception); sh4_exception_checkunrequest(exception);
@ -965,16 +965,16 @@ READ32_HANDLER( sh4_internal_r )
return sh4.m[offset]; return sh4.m[offset];
} }
void sh4_set_frt_input(int cpunum, int state) void sh4_set_frt_input(const device_config *device, int state)
{ {
if(state == PULSE_LINE) if(state == PULSE_LINE)
{ {
sh4_set_frt_input(cpunum, ASSERT_LINE); sh4_set_frt_input(device, ASSERT_LINE);
sh4_set_frt_input(cpunum, CLEAR_LINE); sh4_set_frt_input(device, CLEAR_LINE);
return; return;
} }
cpu_push_context(Machine->cpu[cpunum]); cpu_push_context(device);
if(sh4.frt_input == state) { if(sh4.frt_input == state) {
cpu_pop_context(); cpu_pop_context();
@ -1005,12 +1005,12 @@ void sh4_set_frt_input(int cpunum, int state)
cpu_pop_context(); cpu_pop_context();
} }
void sh4_set_irln_input(int cpunum, int value) void sh4_set_irln_input(const device_config *device, int value)
{ {
if (sh4.irln == value) if (sh4.irln == value)
return; return;
sh4.irln = value; sh4.irln = value;
cpu_set_input_line(Machine->cpu[cpunum], SH4_IRLn, PULSE_LINE); cpu_set_input_line(device, SH4_IRLn, PULSE_LINE);
} }
void sh4_set_irq_line(int irqline, int state) // set state of external interrupt line void sh4_set_irq_line(int irqline, int state) // set state of external interrupt line
@ -1025,7 +1025,7 @@ int s;
{ {
if ((state == CLEAR_LINE) && (sh4.nmi_line_state == ASSERT_LINE)) // rising if ((state == CLEAR_LINE) && (sh4.nmi_line_state == ASSERT_LINE)) // rising
{ {
LOG(("SH-4 #%d assert nmi\n", cpunum_get_active())); LOG(("SH-4 '%s' assert nmi\n", sh4.device->tag));
sh4_exception_request(SH4_INTC_NMI); sh4_exception_request(SH4_INTC_NMI);
sh4_dmac_nmi(); sh4_dmac_nmi();
} }
@ -1034,7 +1034,7 @@ int s;
{ {
if ((state == ASSERT_LINE) && (sh4.nmi_line_state == CLEAR_LINE)) // falling if ((state == ASSERT_LINE) && (sh4.nmi_line_state == CLEAR_LINE)) // falling
{ {
LOG(("SH-4 #%d assert nmi\n", cpunum_get_active())); LOG(("SH-4 '%s' assert nmi\n", sh4.device->tag));
sh4_exception_request(SH4_INTC_NMI); sh4_exception_request(SH4_INTC_NMI);
sh4_dmac_nmi(); sh4_dmac_nmi();
} }
@ -1057,12 +1057,12 @@ int s;
if( state == CLEAR_LINE ) if( state == CLEAR_LINE )
{ {
LOG(("SH-4 #%d cleared external irq IRL%d\n", cpunum_get_active(), irqline)); LOG(("SH-4 '%s' cleared external irq IRL%d\n", sh4.device->tag, irqline));
sh4_exception_unrequest(SH4_INTC_IRL0+irqline-SH4_IRL0); sh4_exception_unrequest(SH4_INTC_IRL0+irqline-SH4_IRL0);
} }
else else
{ {
LOG(("SH-4 #%d assert external irq IRL%d\n", cpunum_get_active(), irqline)); LOG(("SH-4 '%s' assert external irq IRL%d\n", sh4.device->tag, irqline));
sh4_exception_request(SH4_INTC_IRL0+irqline-SH4_IRL0); sh4_exception_request(SH4_INTC_IRL0+irqline-SH4_IRL0);
} }
} }
@ -1076,7 +1076,7 @@ int s;
sh4_exception_unrequest(SH4_INTC_IRLn0+s); sh4_exception_unrequest(SH4_INTC_IRLn0+s);
if (sh4.irln < 15) if (sh4.irln < 15)
sh4_exception_request(SH4_INTC_IRLn0+sh4.irln); sh4_exception_request(SH4_INTC_IRLn0+sh4.irln);
LOG(("SH-4 #%d IRLn0-IRLn3 level #%d\n", cpunum_get_active(), sh4.irln)); LOG(("SH-4 '%s' IRLn0-IRLn3 level #%d\n", sh4.device->tag, sh4.irln));
} }
} }
if (sh4.test_irq && (!sh4.delay)) if (sh4.test_irq && (!sh4.delay))

4
src/emu/cpu/sh4/sh4comn.h
View File

@ -138,8 +138,8 @@ void sh4_default_exception_priorities(void); // setup default priorities for exc
void sh4_parse_configuration(const struct sh4_config *conf); void sh4_parse_configuration(const struct sh4_config *conf);
void sh4_dma_ddt(struct sh4_ddt_dma *s); void sh4_dma_ddt(struct sh4_ddt_dma *s);
void sh4_set_irq_line(int irqline, int state); // set state of external interrupt line void sh4_set_irq_line(int irqline, int state); // set state of external interrupt line
void sh4_set_frt_input(int cpunum, int state); void sh4_set_frt_input(const device_config *device, int state);
void sh4_set_irln_input(int cpunum, int value); void sh4_set_irln_input(const device_config *device, int value);
#ifdef LSB_FIRST #ifdef LSB_FIRST
void sh4_swap_fp_couples(void); void sh4_swap_fp_couples(void);
#endif #endif

27
src/emu/cpu/spc700/spc700.c
View File

@ -1366,38 +1366,11 @@ void spc700_set_irq_callback(cpu_irq_callback callback)
/* Save the current CPU state to disk */ /* Save the current CPU state to disk */
void spc700_state_save(void *file) void spc700_state_save(void *file)
{ {
#if 0
int cpu = cpunum_get_active();
uint p = GET_REG_P();
state_save_UINT16(file,"spc700",cpu,"PC",&REG_PC,2);
state_save_UINT16(file,"spc700",cpu,"PPC",&REG_PPC,2);
state_save_UINT8(file,"spc700",cpu,"SP",&REG_SP,1);
state_save_UINT8(file,"spc700",cpu,"P",&p,1);
state_save_UINT8(file,"spc700",cpu,"A",&REG_A,1);
state_save_UINT8(file,"spc700",cpu,"X",&REG_X,1);
state_save_UINT8(file,"spc700",cpu,"Y",&REG_Y,1);
state_save_UINT8(file,"spc700",cpu,"IRQ",&LINE_IRQ,1);
state_save_UINT8(file,"spc700",cpu,"NMI",&LINE_NMI,1);
#endif
} }
/* Load a CPU state from disk */ /* Load a CPU state from disk */
void spc700_state_load(void *file) void spc700_state_load(void *file)
{ {
#if 0
int cpu = cpunum_get_active();
uint p;
state_load_UINT16(file,"spc700",cpu,"PC",&REG_PC,2);
state_load_UINT16(file,"spc700",cpu,"PPC",&REG_PPC,2);
state_load_UINT8(file,"spc700",cpu,"SP",&REG_SP,1);
state_load_UINT8(file,"spc700",cpu,"P",&p,1);
state_load_UINT8(file,"spc700",cpu,"A",&REG_A,1);
state_load_UINT8(file,"spc700",cpu,"X",&REG_X,1);
state_load_UINT8(file,"spc700",cpu,"Y",&REG_Y,1);
state_load_UINT8(file,"spc700",cpu,"IRQ",&LINE_IRQ,1);
state_load_UINT8(file,"spc700",cpu,"NMI",&LINE_NMI,1);
SET_REG_P(p);
#endif
} }

16
src/emu/cpu/tms34010/tms34010.c
View File

@ -531,7 +531,7 @@ static void check_interrupt(tms34010_state *tms)
/* check for NMI first */ /* check for NMI first */
if (IOREG(tms, REG_HSTCTLH) & 0x0100) if (IOREG(tms, REG_HSTCTLH) & 0x0100)
{ {
LOG(("TMS34010#%d takes NMI\n", cpunum_get_active())); LOG(("TMS34010 '%s' takes NMI\n", tms->device->tag));
/* ack the NMI */ /* ack the NMI */
IOREG(tms, REG_HSTCTLH) &= ~0x0100; IOREG(tms, REG_HSTCTLH) &= ~0x0100;
@ -558,28 +558,28 @@ static void check_interrupt(tms34010_state *tms)
/* host interrupt */ /* host interrupt */
if (irq & TMS34010_HI) if (irq & TMS34010_HI)
{ {
LOG(("TMS34010#%d takes HI\n", cpunum_get_active())); LOG(("TMS34010 '%s' takes HI\n", tms->device->tag));
vector = 0xfffffec0; vector = 0xfffffec0;
} }
/* display interrupt */ /* display interrupt */
else if (irq & TMS34010_DI) else if (irq & TMS34010_DI)
{ {
LOG(("TMS34010#%d takes DI\n", cpunum_get_active())); LOG(("TMS34010 '%s' takes DI\n", tms->device->tag));
vector = 0xfffffea0; vector = 0xfffffea0;
} }
/* window violation interrupt */ /* window violation interrupt */
else if (irq & TMS34010_WV) else if (irq & TMS34010_WV)
{ {
LOG(("TMS34010#%d takes WV\n", cpunum_get_active())); LOG(("TMS34010 '%s' takes WV\n", tms->device->tag));
vector = 0xfffffe80; vector = 0xfffffe80;
} }
/* external 1 interrupt */ /* external 1 interrupt */
else if (irq & TMS34010_INT1) else if (irq & TMS34010_INT1)
{ {
LOG(("TMS34010#%d takes INT1\n", cpunum_get_active())); LOG(("TMS34010 '%s' takes INT1\n", tms->device->tag));
vector = 0xffffffc0; vector = 0xffffffc0;
irqline = 0; irqline = 0;
} }
@ -587,7 +587,7 @@ static void check_interrupt(tms34010_state *tms)
/* external 2 interrupt */ /* external 2 interrupt */
else if (irq & TMS34010_INT2) else if (irq & TMS34010_INT2)
{ {
LOG(("TMS34010#%d takes INT2\n", cpunum_get_active())); LOG(("TMS34010 '%s' takes INT2\n", tms->device->tag));
vector = 0xffffffa0; vector = 0xffffffa0;
irqline = 1; irqline = 1;
} }
@ -736,7 +736,7 @@ static CPU_SET_CONTEXT( tms34020 )
static void set_irq_line(tms34010_state *tms, int irqline, int linestate) static void set_irq_line(tms34010_state *tms, int irqline, int linestate)
{ {
LOG(("TMS34010#%d set irq line %d state %d\n", cpunum_get_active(), irqline, linestate)); LOG(("TMS34010 '%s' set irq line %d state %d\n", tms->device->tag, irqline, linestate));
/* set the pending interrupt */ /* set the pending interrupt */
switch (irqline) switch (irqline)
@ -771,7 +771,7 @@ static TIMER_CALLBACK( internal_interrupt_callback )
/* call through to the CPU to generate the int */ /* call through to the CPU to generate the int */
IOREG(tms, REG_INTPEND) |= type; IOREG(tms, REG_INTPEND) |= type;
LOG(("TMS34010#%d set internal interrupt $%04x\n", cpunum_get_active(), type)); LOG(("TMS34010 '%s' set internal interrupt $%04x\n", tms->device->tag, type));
/* generate triggers so that spin loops can key off them */ /* generate triggers so that spin loops can key off them */
for (cpunum = 0; cpunum < ARRAY_LENGTH(machine->cpu); cpunum++) for (cpunum = 0; cpunum < ARRAY_LENGTH(machine->cpu); cpunum++)

2
src/emu/cpu/tms7000/tms7000.c
View File

@ -385,7 +385,7 @@ void tms7000_set_irq_line(int irqline, int state)
{ /* check for transition */ { /* check for transition */
tms7000.irq_state[irqline] = state; tms7000.irq_state[irqline] = state;
LOG(("tms7000: (cpu #%d) set_irq_line (INT%d, state %d)\n", cpunum_get_active(), irqline+1, state)); LOG(("tms7000: (cpu '%s') set_irq_line (INT%d, state %d)\n", tms7000.device->tag, irqline+1, state));
if (state == CLEAR_LINE) if (state == CLEAR_LINE)
{ {

12
src/emu/cpu/upd7810/7810ops.c
View File

@ -9,12 +9,12 @@
static void illegal(void) static void illegal(void)
{ {
logerror("uPD7810 #%d: illegal opcode %02x at PC:%04x\n", cpunum_get_active(), OP, PC); logerror("uPD7810 '%s': illegal opcode %02x at PC:%04x\n", upd7810.device->tag, OP, PC);
} }
static void illegal2(void) static void illegal2(void)
{ {
logerror("uPD7810 #%d: illegal opcode %02x %02x at PC:%04x\n", cpunum_get_active(), OP, OP2, PC); logerror("uPD7810 '%s': illegal opcode %02x %02x at PC:%04x\n", upd7810.device->tag, OP, OP2, PC);
} }
/* prefix 48 */ /* prefix 48 */
@ -8648,7 +8648,7 @@ static void SKN_bit(void)
val = RP( UPD7807_PORTT ); val = RP( UPD7807_PORTT );
break; break;
default: default:
logerror("uPD7810 #%d: illegal opcode %02x %02x at PC:%04x\n", cpunum_get_active(), OP, imm, PC); logerror("uPD7810 '%s': illegal opcode %02x %02x at PC:%04x\n", upd7810.device->tag, OP, imm, PC);
val = 0; val = 0;
break; break;
} }
@ -8702,7 +8702,7 @@ static void SETB(void)
// PT is input only // PT is input only
// break; // break;
default: default:
logerror("uPD7810 #%d: illegal opcode %02x %02x at PC:%04x\n", cpunum_get_active(), OP, imm, PC); logerror("uPD7810 '%s': illegal opcode %02x %02x at PC:%04x\n", upd7810.device->tag, OP, imm, PC);
break; break;
} }
} }
@ -8752,7 +8752,7 @@ static void CLR(void)
// PT is input only // PT is input only
// break; // break;
default: default:
logerror("uPD7810 #%d: illegal opcode %02x %02x at PC:%04x\n", cpunum_get_active(), OP, imm, PC); logerror("uPD7810 '%s': illegal opcode %02x %02x at PC:%04x\n", upd7810.device->tag, OP, imm, PC);
break; break;
} }
} }
@ -8801,7 +8801,7 @@ static void SK_bit(void)
val = RP( UPD7807_PORTT ); val = RP( UPD7807_PORTT );
break; break;
default: default:
logerror("uPD7810 #%d: illegal opcode %02x %02x at PC:%04x\n", cpunum_get_active(), OP, imm, PC); logerror("uPD7810 '%s': illegal opcode %02x %02x at PC:%04x\n", upd7810.device->tag, OP, imm, PC);
val = 0; val = 0;
break; break;
} }

296
src/emu/cpu/z180/z180.c
View File

@ -825,68 +825,68 @@ static UINT8 z180_readcontrol(offs_t port)
{ {
case Z180_CNTLA0: case Z180_CNTLA0:
data = IO_CNTLA0 & Z180_CNTLA0_RMASK; data = IO_CNTLA0 & Z180_CNTLA0_RMASK;
LOG(("Z180 #%d CNTLA0 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' CNTLA0 rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_CNTLA1: case Z180_CNTLA1:
data = IO_CNTLA1 & Z180_CNTLA1_RMASK; data = IO_CNTLA1 & Z180_CNTLA1_RMASK;
LOG(("Z180 #%d CNTLA1 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' CNTLA1 rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_CNTLB0: case Z180_CNTLB0:
data = IO_CNTLB0 & Z180_CNTLB0_RMASK; data = IO_CNTLB0 & Z180_CNTLB0_RMASK;
LOG(("Z180 #%d CNTLB0 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' CNTLB0 rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_CNTLB1: case Z180_CNTLB1:
data = IO_CNTLB1 & Z180_CNTLB1_RMASK; data = IO_CNTLB1 & Z180_CNTLB1_RMASK;
LOG(("Z180 #%d CNTLB1 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' CNTLB1 rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_STAT0: case Z180_STAT0:
data = IO_STAT0 & Z180_STAT0_RMASK; data = IO_STAT0 & Z180_STAT0_RMASK;
data |= 0x02; // kludge for 20pacgal data |= 0x02; // kludge for 20pacgal
LOG(("Z180 #%d STAT0 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' STAT0 rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_STAT1: case Z180_STAT1:
data = IO_STAT1 & Z180_STAT1_RMASK; data = IO_STAT1 & Z180_STAT1_RMASK;
LOG(("Z180 #%d STAT1 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' STAT1 rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_TDR0: case Z180_TDR0:
data = IO_TDR0 & Z180_TDR0_RMASK; data = IO_TDR0 & Z180_TDR0_RMASK;
LOG(("Z180 #%d TDR0 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' TDR0 rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_TDR1: case Z180_TDR1:
data = IO_TDR1 & Z180_TDR1_RMASK; data = IO_TDR1 & Z180_TDR1_RMASK;
LOG(("Z180 #%d TDR1 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' TDR1 rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_RDR0: case Z180_RDR0:
data = IO_RDR0 & Z180_RDR0_RMASK; data = IO_RDR0 & Z180_RDR0_RMASK;
LOG(("Z180 #%d RDR0 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' RDR0 rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_RDR1: case Z180_RDR1:
data = IO_RDR1 & Z180_RDR1_RMASK; data = IO_RDR1 & Z180_RDR1_RMASK;
LOG(("Z180 #%d RDR1 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' RDR1 rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_CNTR: case Z180_CNTR:
data = IO_CNTR & Z180_CNTR_RMASK; data = IO_CNTR & Z180_CNTR_RMASK;
LOG(("Z180 #%d CNTR rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' CNTR rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_TRDR: case Z180_TRDR:
data = IO_TRDR & Z180_TRDR_RMASK; data = IO_TRDR & Z180_TRDR_RMASK;
LOG(("Z180 #%d TRDR rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' TRDR rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_TMDR0L: case Z180_TMDR0L:
data = Z180.tmdr_value[0] & Z180_TMDR0L_RMASK; data = Z180.tmdr_value[0] & Z180_TMDR0L_RMASK;
LOG(("Z180 #%d TMDR0L rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' TMDR0L rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
/* if timer is counting, latch the MSB and set the latch flag */ /* if timer is counting, latch the MSB and set the latch flag */
if ((IO_TCR & Z180_TCR_TDE0) == 0) if ((IO_TCR & Z180_TCR_TDE0) == 0)
{ {
@ -926,17 +926,17 @@ data |= 0x02; // kludge for 20pacgal
{ {
Z180.read_tcr_tmdr[0] = 1; Z180.read_tcr_tmdr[0] = 1;
} }
LOG(("Z180 #%d TMDR0H rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' TMDR0H rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_RLDR0L: case Z180_RLDR0L:
data = IO_RLDR0L & Z180_RLDR0L_RMASK; data = IO_RLDR0L & Z180_RLDR0L_RMASK;
LOG(("Z180 #%d RLDR0L rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' RLDR0L rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_RLDR0H: case Z180_RLDR0H:
data = IO_RLDR0H & Z180_RLDR0H_RMASK; data = IO_RLDR0H & Z180_RLDR0H_RMASK;
LOG(("Z180 #%d RLDR0H rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' RLDR0H rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_TCR: case Z180_TCR:
@ -962,27 +962,27 @@ data |= 0x02; // kludge for 20pacgal
Z180.read_tcr_tmdr[1] = 1; Z180.read_tcr_tmdr[1] = 1;
} }
LOG(("Z180 #%d TCR rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' TCR rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_IO11: case Z180_IO11:
data = IO_IO11 & Z180_IO11_RMASK; data = IO_IO11 & Z180_IO11_RMASK;
LOG(("Z180 #%d IO11 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' IO11 rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_ASEXT0: case Z180_ASEXT0:
data = IO_ASEXT0 & Z180_ASEXT0_RMASK; data = IO_ASEXT0 & Z180_ASEXT0_RMASK;
LOG(("Z180 #%d ASEXT0 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' ASEXT0 rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_ASEXT1: case Z180_ASEXT1:
data = IO_ASEXT1 & Z180_ASEXT1_RMASK; data = IO_ASEXT1 & Z180_ASEXT1_RMASK;
LOG(("Z180 #%d ASEXT1 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' ASEXT1 rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_TMDR1L: case Z180_TMDR1L:
data = Z180.tmdr_value[1] & Z180_TMDR1L_RMASK; data = Z180.tmdr_value[1] & Z180_TMDR1L_RMASK;
LOG(("Z180 #%d TMDR1L rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' TMDR1L rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
/* if timer is counting, latch the MSB and set the latch flag */ /* if timer is counting, latch the MSB and set the latch flag */
if ((IO_TCR & Z180_TCR_TDE1) == 0) if ((IO_TCR & Z180_TCR_TDE1) == 0)
{ {
@ -1022,217 +1022,217 @@ data |= 0x02; // kludge for 20pacgal
{ {
Z180.read_tcr_tmdr[1] = 1; Z180.read_tcr_tmdr[1] = 1;
} }
LOG(("Z180 #%d TMDR1H rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' TMDR1H rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_RLDR1L: case Z180_RLDR1L:
data = IO_RLDR1L & Z180_RLDR1L_RMASK; data = IO_RLDR1L & Z180_RLDR1L_RMASK;
LOG(("Z180 #%d RLDR1L rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' RLDR1L rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_RLDR1H: case Z180_RLDR1H:
data = IO_RLDR1H & Z180_RLDR1H_RMASK; data = IO_RLDR1H & Z180_RLDR1H_RMASK;
LOG(("Z180 #%d RLDR1H rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' RLDR1H rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_FRC: case Z180_FRC:
data = IO_FRC & Z180_FRC_RMASK; data = IO_FRC & Z180_FRC_RMASK;
LOG(("Z180 #%d FRC rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' FRC rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_IO19: case Z180_IO19:
data = IO_IO19 & Z180_IO19_RMASK; data = IO_IO19 & Z180_IO19_RMASK;
LOG(("Z180 #%d IO19 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' IO19 rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_ASTC0L: case Z180_ASTC0L:
data = IO_ASTC0L & Z180_ASTC0L_RMASK; data = IO_ASTC0L & Z180_ASTC0L_RMASK;
LOG(("Z180 #%d ASTC0L rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' ASTC0L rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_ASTC0H: case Z180_ASTC0H:
data = IO_ASTC0H & Z180_ASTC0H_RMASK; data = IO_ASTC0H & Z180_ASTC0H_RMASK;
LOG(("Z180 #%d ASTC0H rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' ASTC0H rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_ASTC1L: case Z180_ASTC1L:
data = IO_ASTC1L & Z180_ASTC1L_RMASK; data = IO_ASTC1L & Z180_ASTC1L_RMASK;
LOG(("Z180 #%d ASTC1L rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' ASTC1L rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_ASTC1H: case Z180_ASTC1H:
data = IO_ASTC1H & Z180_ASTC1H_RMASK; data = IO_ASTC1H & Z180_ASTC1H_RMASK;
LOG(("Z180 #%d ASTC1H rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' ASTC1H rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_CMR: case Z180_CMR:
data = IO_CMR & Z180_CMR_RMASK; data = IO_CMR & Z180_CMR_RMASK;
LOG(("Z180 #%d CMR rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' CMR rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_CCR: case Z180_CCR:
data = IO_CCR & Z180_CCR_RMASK; data = IO_CCR & Z180_CCR_RMASK;
LOG(("Z180 #%d CCR rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' CCR rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_SAR0L: case Z180_SAR0L:
data = IO_SAR0L & Z180_SAR0L_RMASK; data = IO_SAR0L & Z180_SAR0L_RMASK;
LOG(("Z180 #%d SAR0L rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' SAR0L rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_SAR0H: case Z180_SAR0H:
data = IO_SAR0H & Z180_SAR0H_RMASK; data = IO_SAR0H & Z180_SAR0H_RMASK;
LOG(("Z180 #%d SAR0H rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' SAR0H rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_SAR0B: case Z180_SAR0B:
data = IO_SAR0B & Z180_SAR0B_RMASK; data = IO_SAR0B & Z180_SAR0B_RMASK;
LOG(("Z180 #%d SAR0B rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' SAR0B rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_DAR0L: case Z180_DAR0L:
data = IO_DAR0L & Z180_DAR0L_RMASK; data = IO_DAR0L & Z180_DAR0L_RMASK;
LOG(("Z180 #%d DAR0L rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' DAR0L rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_DAR0H: case Z180_DAR0H:
data = IO_DAR0H & Z180_DAR0H_RMASK; data = IO_DAR0H & Z180_DAR0H_RMASK;
LOG(("Z180 #%d DAR0H rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' DAR0H rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_DAR0B: case Z180_DAR0B:
data = IO_DAR0B & Z180_DAR0B_RMASK; data = IO_DAR0B & Z180_DAR0B_RMASK;
LOG(("Z180 #%d DAR0B rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' DAR0B rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_BCR0L: case Z180_BCR0L:
data = IO_BCR0L & Z180_BCR0L_RMASK; data = IO_BCR0L & Z180_BCR0L_RMASK;
LOG(("Z180 #%d BCR0L rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' BCR0L rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_BCR0H: case Z180_BCR0H:
data = IO_BCR0H & Z180_BCR0H_RMASK; data = IO_BCR0H & Z180_BCR0H_RMASK;
LOG(("Z180 #%d BCR0H rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' BCR0H rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_MAR1L: case Z180_MAR1L:
data = IO_MAR1L & Z180_MAR1L_RMASK; data = IO_MAR1L & Z180_MAR1L_RMASK;
LOG(("Z180 #%d MAR1L rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' MAR1L rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_MAR1H: case Z180_MAR1H:
data = IO_MAR1H & Z180_MAR1H_RMASK; data = IO_MAR1H & Z180_MAR1H_RMASK;
LOG(("Z180 #%d MAR1H rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' MAR1H rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_MAR1B: case Z180_MAR1B:
data = IO_MAR1B & Z180_MAR1B_RMASK; data = IO_MAR1B & Z180_MAR1B_RMASK;
LOG(("Z180 #%d MAR1B rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' MAR1B rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_IAR1L: case Z180_IAR1L:
data = IO_IAR1L & Z180_IAR1L_RMASK; data = IO_IAR1L & Z180_IAR1L_RMASK;
LOG(("Z180 #%d IAR1L rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' IAR1L rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_IAR1H: case Z180_IAR1H:
data = IO_IAR1H & Z180_IAR1H_RMASK; data = IO_IAR1H & Z180_IAR1H_RMASK;
LOG(("Z180 #%d IAR1H rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' IAR1H rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_IAR1B: case Z180_IAR1B:
data = IO_IAR1B & Z180_IAR1B_RMASK; data = IO_IAR1B & Z180_IAR1B_RMASK;
LOG(("Z180 #%d IAR1B rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' IAR1B rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_BCR1L: case Z180_BCR1L:
data = IO_BCR1L & Z180_BCR1L_RMASK; data = IO_BCR1L & Z180_BCR1L_RMASK;
LOG(("Z180 #%d BCR1L rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' BCR1L rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_BCR1H: case Z180_BCR1H:
data = IO_BCR1H & Z180_BCR1H_RMASK; data = IO_BCR1H & Z180_BCR1H_RMASK;
LOG(("Z180 #%d BCR1H rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' BCR1H rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_DSTAT: case Z180_DSTAT:
data = IO_DSTAT & Z180_DSTAT_RMASK; data = IO_DSTAT & Z180_DSTAT_RMASK;
LOG(("Z180 #%d DSTAT rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' DSTAT rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_DMODE: case Z180_DMODE:
data = IO_DMODE & Z180_DMODE_RMASK; data = IO_DMODE & Z180_DMODE_RMASK;
LOG(("Z180 #%d DMODE rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' DMODE rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_DCNTL: case Z180_DCNTL:
data = IO_DCNTL & Z180_DCNTL_RMASK; data = IO_DCNTL & Z180_DCNTL_RMASK;
LOG(("Z180 #%d DCNTL rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' DCNTL rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_IL: case Z180_IL:
data = IO_IL & Z180_IL_RMASK; data = IO_IL & Z180_IL_RMASK;
LOG(("Z180 #%d IL rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' IL rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_ITC: case Z180_ITC:
data = IO_ITC & Z180_ITC_RMASK; data = IO_ITC & Z180_ITC_RMASK;
LOG(("Z180 #%d ITC rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' ITC rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_IO35: case Z180_IO35:
data = IO_IO35 & Z180_IO35_RMASK; data = IO_IO35 & Z180_IO35_RMASK;
LOG(("Z180 #%d IO35 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' IO35 rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_RCR: case Z180_RCR:
data = IO_RCR & Z180_RCR_RMASK; data = IO_RCR & Z180_RCR_RMASK;
LOG(("Z180 #%d RCR rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' RCR rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_IO37: case Z180_IO37:
data = IO_IO37 & Z180_IO37_RMASK; data = IO_IO37 & Z180_IO37_RMASK;
LOG(("Z180 #%d IO37 rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' IO37 rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_CBR: case Z180_CBR:
data = IO_CBR & Z180_CBR_RMASK; data = IO_CBR & Z180_CBR_RMASK;
LOG(("Z180 #%d CBR rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' CBR rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_BBR: case Z180_BBR:
data = IO_BBR & Z180_BBR_RMASK; data = IO_BBR & Z180_BBR_RMASK;
LOG(("Z180 #%d BBR rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' BBR rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_CBAR: case Z180_CBAR:
data = IO_CBAR & Z180_CBAR_RMASK; data = IO_CBAR & Z180_CBAR_RMASK;
LOG(("Z180 #%d CBAR rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' CBAR rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_IO3B: case Z180_IO3B:
data = IO_IO3B & Z180_IO3B_RMASK; data = IO_IO3B & Z180_IO3B_RMASK;
LOG(("Z180 #%d IO3B rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' IO3B rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_IO3C: case Z180_IO3C:
data = IO_IO3C & Z180_IO3C_RMASK; data = IO_IO3C & Z180_IO3C_RMASK;
LOG(("Z180 #%d IO3C rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' IO3C rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_IO3D: case Z180_IO3D:
data = IO_IO3D & Z180_IO3D_RMASK; data = IO_IO3D & Z180_IO3D_RMASK;
LOG(("Z180 #%d IO3D rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' IO3D rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_OMCR: case Z180_OMCR:
data = IO_OMCR & Z180_OMCR_RMASK; data = IO_OMCR & Z180_OMCR_RMASK;
LOG(("Z180 #%d OMCR rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' OMCR rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
case Z180_IOCR: case Z180_IOCR:
data = IO_IOCR & Z180_IOCR_RMASK; data = IO_IOCR & Z180_IOCR_RMASK;
LOG(("Z180 #%d IOCR rd $%02x ($%02x)\n", cpunum_get_active(), data, Z180.io[port & 0x3f])); LOG(("Z180 '%s' IOCR rd $%02x ($%02x)\n", Z180.device->tag, data, Z180.io[port & 0x3f]));
break; break;
} }
@ -1252,251 +1252,251 @@ static void z180_writecontrol(offs_t port, UINT8 data)
switch (port + Z180_CNTLA0) switch (port + Z180_CNTLA0)
{ {
case Z180_CNTLA0: case Z180_CNTLA0:
LOG(("Z180 #%d CNTLA0 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_CNTLA0_WMASK)); LOG(("Z180 '%s' CNTLA0 wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_CNTLA0_WMASK));
IO_CNTLA0 = (IO_CNTLA0 & ~Z180_CNTLA0_WMASK) | (data & Z180_CNTLA0_WMASK); IO_CNTLA0 = (IO_CNTLA0 & ~Z180_CNTLA0_WMASK) | (data & Z180_CNTLA0_WMASK);
break; break;
case Z180_CNTLA1: case Z180_CNTLA1:
LOG(("Z180 #%d CNTLA1 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_CNTLA1_WMASK)); LOG(("Z180 '%s' CNTLA1 wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_CNTLA1_WMASK));
IO_CNTLA1 = (IO_CNTLA1 & ~Z180_CNTLA1_WMASK) | (data & Z180_CNTLA1_WMASK); IO_CNTLA1 = (IO_CNTLA1 & ~Z180_CNTLA1_WMASK) | (data & Z180_CNTLA1_WMASK);
break; break;
case Z180_CNTLB0: case Z180_CNTLB0:
LOG(("Z180 #%d CNTLB0 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_CNTLB0_WMASK)); LOG(("Z180 '%s' CNTLB0 wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_CNTLB0_WMASK));
IO_CNTLB0 = (IO_CNTLB0 & ~Z180_CNTLB0_WMASK) | (data & Z180_CNTLB0_WMASK); IO_CNTLB0 = (IO_CNTLB0 & ~Z180_CNTLB0_WMASK) | (data & Z180_CNTLB0_WMASK);
break; break;
case Z180_CNTLB1: case Z180_CNTLB1:
LOG(("Z180 #%d CNTLB1 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_CNTLB1_WMASK)); LOG(("Z180 '%s' CNTLB1 wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_CNTLB1_WMASK));
IO_CNTLB1 = (IO_CNTLB1 & ~Z180_CNTLB1_WMASK) | (data & Z180_CNTLB1_WMASK); IO_CNTLB1 = (IO_CNTLB1 & ~Z180_CNTLB1_WMASK) | (data & Z180_CNTLB1_WMASK);
break; break;
case Z180_STAT0: case Z180_STAT0:
LOG(("Z180 #%d STAT0 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_STAT0_WMASK)); LOG(("Z180 '%s' STAT0 wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_STAT0_WMASK));
IO_STAT0 = (IO_STAT0 & ~Z180_STAT0_WMASK) | (data & Z180_STAT0_WMASK); IO_STAT0 = (IO_STAT0 & ~Z180_STAT0_WMASK) | (data & Z180_STAT0_WMASK);
break; break;
case Z180_STAT1: case Z180_STAT1:
LOG(("Z180 #%d STAT1 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_STAT1_WMASK)); LOG(("Z180 '%s' STAT1 wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_STAT1_WMASK));
IO_STAT1 = (IO_STAT1 & ~Z180_STAT1_WMASK) | (data & Z180_STAT1_WMASK); IO_STAT1 = (IO_STAT1 & ~Z180_STAT1_WMASK) | (data & Z180_STAT1_WMASK);
break; break;
case Z180_TDR0: case Z180_TDR0:
LOG(("Z180 #%d TDR0 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_TDR0_WMASK)); LOG(("Z180 '%s' TDR0 wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_TDR0_WMASK));
IO_TDR0 = (IO_TDR0 & ~Z180_TDR0_WMASK) | (data & Z180_TDR0_WMASK); IO_TDR0 = (IO_TDR0 & ~Z180_TDR0_WMASK) | (data & Z180_TDR0_WMASK);
break; break;
case Z180_TDR1: case Z180_TDR1:
LOG(("Z180 #%d TDR1 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_TDR1_WMASK)); LOG(("Z180 '%s' TDR1 wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_TDR1_WMASK));
IO_TDR1 = (IO_TDR1 & ~Z180_TDR1_WMASK) | (data & Z180_TDR1_WMASK); IO_TDR1 = (IO_TDR1 & ~Z180_TDR1_WMASK) | (data & Z180_TDR1_WMASK);
break; break;
case Z180_RDR0: case Z180_RDR0:
LOG(("Z180 #%d RDR0 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_RDR0_WMASK)); LOG(("Z180 '%s' RDR0 wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_RDR0_WMASK));
IO_RDR0 = (IO_RDR0 & ~Z180_RDR0_WMASK) | (data & Z180_RDR0_WMASK); IO_RDR0 = (IO_RDR0 & ~Z180_RDR0_WMASK) | (data & Z180_RDR0_WMASK);
break; break;
case Z180_RDR1: case Z180_RDR1:
LOG(("Z180 #%d RDR1 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_RDR1_WMASK)); LOG(("Z180 '%s' RDR1 wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_RDR1_WMASK));
IO_RDR1 = (IO_RDR1 & ~Z180_RDR1_WMASK) | (data & Z180_RDR1_WMASK); IO_RDR1 = (IO_RDR1 & ~Z180_RDR1_WMASK) | (data & Z180_RDR1_WMASK);
break; break;
case Z180_CNTR: case Z180_CNTR:
LOG(("Z180 #%d CNTR wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_CNTR_WMASK)); LOG(("Z180 '%s' CNTR wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_CNTR_WMASK));
IO_CNTR = (IO_CNTR & ~Z180_CNTR_WMASK) | (data & Z180_CNTR_WMASK); IO_CNTR = (IO_CNTR & ~Z180_CNTR_WMASK) | (data & Z180_CNTR_WMASK);
break; break;
case Z180_TRDR: case Z180_TRDR:
LOG(("Z180 #%d TRDR wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_TRDR_WMASK)); LOG(("Z180 '%s' TRDR wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_TRDR_WMASK));
IO_TRDR = (IO_TRDR & ~Z180_TRDR_WMASK) | (data & Z180_TRDR_WMASK); IO_TRDR = (IO_TRDR & ~Z180_TRDR_WMASK) | (data & Z180_TRDR_WMASK);
break; break;
case Z180_TMDR0L: case Z180_TMDR0L:
LOG(("Z180 #%d TMDR0L wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_TMDR0L_WMASK)); LOG(("Z180 '%s' TMDR0L wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_TMDR0L_WMASK));
IO_TMDR0L = data & Z180_TMDR0L_WMASK; IO_TMDR0L = data & Z180_TMDR0L_WMASK;
Z180.tmdr_value[0] = (Z180.tmdr_value[0] & 0xff00) | IO_TMDR0L; Z180.tmdr_value[0] = (Z180.tmdr_value[0] & 0xff00) | IO_TMDR0L;
break; break;
case Z180_TMDR0H: case Z180_TMDR0H:
LOG(("Z180 #%d TMDR0H wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_TMDR0H_WMASK)); LOG(("Z180 '%s' TMDR0H wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_TMDR0H_WMASK));
IO_TMDR0H = data & Z180_TMDR0H_WMASK; IO_TMDR0H = data & Z180_TMDR0H_WMASK;
Z180.tmdr_value[0] = (Z180.tmdr_value[0] & 0x00ff) | (IO_TMDR0H << 8); Z180.tmdr_value[0] = (Z180.tmdr_value[0] & 0x00ff) | (IO_TMDR0H << 8);
break; break;
case Z180_RLDR0L: case Z180_RLDR0L:
LOG(("Z180 #%d RLDR0L wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_RLDR0L_WMASK)); LOG(("Z180 '%s' RLDR0L wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_RLDR0L_WMASK));
IO_RLDR0L = (IO_RLDR0L & ~Z180_RLDR0L_WMASK) | (data & Z180_RLDR0L_WMASK); IO_RLDR0L = (IO_RLDR0L & ~Z180_RLDR0L_WMASK) | (data & Z180_RLDR0L_WMASK);
break; break;
case Z180_RLDR0H: case Z180_RLDR0H:
LOG(("Z180 #%d RLDR0H wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_RLDR0H_WMASK)); LOG(("Z180 '%s' RLDR0H wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_RLDR0H_WMASK));
IO_RLDR0H = (IO_RLDR0H & ~Z180_RLDR0H_WMASK) | (data & Z180_RLDR0H_WMASK); IO_RLDR0H = (IO_RLDR0H & ~Z180_RLDR0H_WMASK) | (data & Z180_RLDR0H_WMASK);
break; break;
case Z180_TCR: case Z180_TCR:
LOG(("Z180 #%d TCR wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_TCR_WMASK)); LOG(("Z180 '%s' TCR wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_TCR_WMASK));
IO_TCR = (IO_TCR & ~Z180_TCR_WMASK) | (data & Z180_TCR_WMASK); IO_TCR = (IO_TCR & ~Z180_TCR_WMASK) | (data & Z180_TCR_WMASK);
break; break;
case Z180_IO11: case Z180_IO11:
LOG(("Z180 #%d IO11 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_IO11_WMASK)); LOG(("Z180 '%s' IO11 wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_IO11_WMASK));
IO_IO11 = (IO_IO11 & ~Z180_IO11_WMASK) | (data & Z180_IO11_WMASK); IO_IO11 = (IO_IO11 & ~Z180_IO11_WMASK) | (data & Z180_IO11_WMASK);
break; break;
case Z180_ASEXT0: case Z180_ASEXT0:
LOG(("Z180 #%d ASEXT0 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_ASEXT0_WMASK)); LOG(("Z180 '%s' ASEXT0 wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_ASEXT0_WMASK));
IO_ASEXT0 = (IO_ASEXT0 & ~Z180_ASEXT0_WMASK) | (data & Z180_ASEXT0_WMASK); IO_ASEXT0 = (IO_ASEXT0 & ~Z180_ASEXT0_WMASK) | (data & Z180_ASEXT0_WMASK);
break; break;
case Z180_ASEXT1: case Z180_ASEXT1:
LOG(("Z180 #%d ASEXT1 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_ASEXT1_WMASK)); LOG(("Z180 '%s' ASEXT1 wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_ASEXT1_WMASK));
IO_ASEXT1 = (IO_ASEXT1 & ~Z180_ASEXT1_WMASK) | (data & Z180_ASEXT1_WMASK); IO_ASEXT1 = (IO_ASEXT1 & ~Z180_ASEXT1_WMASK) | (data & Z180_ASEXT1_WMASK);
break; break;
case Z180_TMDR1L: case Z180_TMDR1L:
LOG(("Z180 #%d TMDR1L wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_TMDR1L_WMASK)); LOG(("Z180 '%s' TMDR1L wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_TMDR1L_WMASK));
IO_TMDR1L = data & Z180_TMDR1L_WMASK; IO_TMDR1L = data & Z180_TMDR1L_WMASK;
Z180.tmdr_value[1] = (Z180.tmdr_value[1] & 0xff00) | IO_TMDR1L; Z180.tmdr_value[1] = (Z180.tmdr_value[1] & 0xff00) | IO_TMDR1L;
break; break;
case Z180_TMDR1H: case Z180_TMDR1H:
LOG(("Z180 #%d TMDR1H wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_TMDR1H_WMASK)); LOG(("Z180 '%s' TMDR1H wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_TMDR1H_WMASK));
IO_TMDR1H = data & Z180_TMDR1H_WMASK; IO_TMDR1H = data & Z180_TMDR1H_WMASK;
Z180.tmdr_value[1] = (Z180.tmdr_value[1] & 0x00ff) | IO_TMDR1H; Z180.tmdr_value[1] = (Z180.tmdr_value[1] & 0x00ff) | IO_TMDR1H;
break; break;
case Z180_RLDR1L: case Z180_RLDR1L:
LOG(("Z180 #%d RLDR1L wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_RLDR1L_WMASK)); LOG(("Z180 '%s' RLDR1L wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_RLDR1L_WMASK));
IO_RLDR1L = (IO_RLDR1L & ~Z180_RLDR1L_WMASK) | (data & Z180_RLDR1L_WMASK); IO_RLDR1L = (IO_RLDR1L & ~Z180_RLDR1L_WMASK) | (data & Z180_RLDR1L_WMASK);
break; break;
case Z180_RLDR1H: case Z180_RLDR1H:
LOG(("Z180 #%d RLDR1H wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_RLDR1H_WMASK)); LOG(("Z180 '%s' RLDR1H wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_RLDR1H_WMASK));
IO_RLDR1H = (IO_RLDR1H & ~Z180_RLDR1H_WMASK) | (data & Z180_RLDR1H_WMASK); IO_RLDR1H = (IO_RLDR1H & ~Z180_RLDR1H_WMASK) | (data & Z180_RLDR1H_WMASK);
break; break;
case Z180_FRC: case Z180_FRC:
LOG(("Z180 #%d FRC wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_FRC_WMASK)); LOG(("Z180 '%s' FRC wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_FRC_WMASK));
IO_FRC = (IO_FRC & ~Z180_FRC_WMASK) | (data & Z180_FRC_WMASK); IO_FRC = (IO_FRC & ~Z180_FRC_WMASK) | (data & Z180_FRC_WMASK);
break; break;
case Z180_IO19: case Z180_IO19:
LOG(("Z180 #%d IO19 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_IO19_WMASK)); LOG(("Z180 '%s' IO19 wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_IO19_WMASK));
IO_IO19 = (IO_IO19 & ~Z180_IO19_WMASK) | (data & Z180_IO19_WMASK); IO_IO19 = (IO_IO19 & ~Z180_IO19_WMASK) | (data & Z180_IO19_WMASK);
break; break;
case Z180_ASTC0L: case Z180_ASTC0L:
LOG(("Z180 #%d ASTC0L wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_ASTC0L_WMASK)); LOG(("Z180 '%s' ASTC0L wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_ASTC0L_WMASK));
IO_ASTC0L = (IO_ASTC0L & ~Z180_ASTC0L_WMASK) | (data & Z180_ASTC0L_WMASK); IO_ASTC0L = (IO_ASTC0L & ~Z180_ASTC0L_WMASK) | (data & Z180_ASTC0L_WMASK);
break; break;
case Z180_ASTC0H: case Z180_ASTC0H:
LOG(("Z180 #%d ASTC0H wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_ASTC0H_WMASK)); LOG(("Z180 '%s' ASTC0H wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_ASTC0H_WMASK));
IO_ASTC0H = (IO_ASTC0H & ~Z180_ASTC0H_WMASK) | (data & Z180_ASTC0H_WMASK); IO_ASTC0H = (IO_ASTC0H & ~Z180_ASTC0H_WMASK) | (data & Z180_ASTC0H_WMASK);
break; break;
case Z180_ASTC1L: case Z180_ASTC1L:
LOG(("Z180 #%d ASTC1L wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_ASTC1L_WMASK)); LOG(("Z180 '%s' ASTC1L wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_ASTC1L_WMASK));
IO_ASTC1L = (IO_ASTC1L & ~Z180_ASTC1L_WMASK) | (data & Z180_ASTC1L_WMASK); IO_ASTC1L = (IO_ASTC1L & ~Z180_ASTC1L_WMASK) | (data & Z180_ASTC1L_WMASK);
break; break;
case Z180_ASTC1H: case Z180_ASTC1H:
LOG(("Z180 #%d ASTC1H wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_ASTC1H_WMASK)); LOG(("Z180 '%s' ASTC1H wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_ASTC1H_WMASK));
IO_ASTC1H = (IO_ASTC1H & ~Z180_ASTC1H_WMASK) | (data & Z180_ASTC1H_WMASK); IO_ASTC1H = (IO_ASTC1H & ~Z180_ASTC1H_WMASK) | (data & Z180_ASTC1H_WMASK);
break; break;
case Z180_CMR: case Z180_CMR:
LOG(("Z180 #%d CMR wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_CMR_WMASK)); LOG(("Z180 '%s' CMR wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_CMR_WMASK));
IO_CMR = (IO_CMR & ~Z180_CMR_WMASK) | (data & Z180_CMR_WMASK); IO_CMR = (IO_CMR & ~Z180_CMR_WMASK) | (data & Z180_CMR_WMASK);
break; break;
case Z180_CCR: case Z180_CCR:
LOG(("Z180 #%d CCR wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_CCR_WMASK)); LOG(("Z180 '%s' CCR wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_CCR_WMASK));
IO_CCR = (IO_CCR & ~Z180_CCR_WMASK) | (data & Z180_CCR_WMASK); IO_CCR = (IO_CCR & ~Z180_CCR_WMASK) | (data & Z180_CCR_WMASK);
break; break;
case Z180_SAR0L: case Z180_SAR0L:
LOG(("Z180 #%d SAR0L wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_SAR0L_WMASK)); LOG(("Z180 '%s' SAR0L wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_SAR0L_WMASK));
IO_SAR0L = (IO_SAR0L & ~Z180_SAR0L_WMASK) | (data & Z180_SAR0L_WMASK); IO_SAR0L = (IO_SAR0L & ~Z180_SAR0L_WMASK) | (data & Z180_SAR0L_WMASK);
break; break;
case Z180_SAR0H: case Z180_SAR0H:
LOG(("Z180 #%d SAR0H wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_SAR0H_WMASK)); LOG(("Z180 '%s' SAR0H wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_SAR0H_WMASK));
IO_SAR0H = (IO_SAR0H & ~Z180_SAR0H_WMASK) | (data & Z180_SAR0H_WMASK); IO_SAR0H = (IO_SAR0H & ~Z180_SAR0H_WMASK) | (data & Z180_SAR0H_WMASK);
break; break;
case Z180_SAR0B: case Z180_SAR0B:
LOG(("Z180 #%d SAR0B wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_SAR0B_WMASK)); LOG(("Z180 '%s' SAR0B wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_SAR0B_WMASK));
IO_SAR0B = (IO_SAR0B & ~Z180_SAR0B_WMASK) | (data & Z180_SAR0B_WMASK); IO_SAR0B = (IO_SAR0B & ~Z180_SAR0B_WMASK) | (data & Z180_SAR0B_WMASK);
break; break;
case Z180_DAR0L: case Z180_DAR0L:
LOG(("Z180 #%d DAR0L wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_DAR0L_WMASK)); LOG(("Z180 '%s' DAR0L wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_DAR0L_WMASK));
IO_DAR0L = (IO_DAR0L & ~Z180_DAR0L_WMASK) | (data & Z180_DAR0L_WMASK); IO_DAR0L = (IO_DAR0L & ~Z180_DAR0L_WMASK) | (data & Z180_DAR0L_WMASK);
break; break;
case Z180_DAR0H: case Z180_DAR0H:
LOG(("Z180 #%d DAR0H wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_DAR0H_WMASK)); LOG(("Z180 '%s' DAR0H wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_DAR0H_WMASK));
IO_DAR0H = (IO_DAR0H & ~Z180_DAR0H_WMASK) | (data & Z180_DAR0H_WMASK); IO_DAR0H = (IO_DAR0H & ~Z180_DAR0H_WMASK) | (data & Z180_DAR0H_WMASK);
break; break;
case Z180_DAR0B: case Z180_DAR0B:
LOG(("Z180 #%d DAR0B wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_DAR0B_WMASK)); LOG(("Z180 '%s' DAR0B wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_DAR0B_WMASK));
IO_DAR0B = (IO_DAR0B & ~Z180_DAR0B_WMASK) | (data & Z180_DAR0B_WMASK); IO_DAR0B = (IO_DAR0B & ~Z180_DAR0B_WMASK) | (data & Z180_DAR0B_WMASK);
break; break;
case Z180_BCR0L: case Z180_BCR0L:
LOG(("Z180 #%d BCR0L wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_BCR0L_WMASK)); LOG(("Z180 '%s' BCR0L wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_BCR0L_WMASK));
IO_BCR0L = (IO_BCR0L & ~Z180_BCR0L_WMASK) | (data & Z180_BCR0L_WMASK); IO_BCR0L = (IO_BCR0L & ~Z180_BCR0L_WMASK) | (data & Z180_BCR0L_WMASK);
break; break;
case Z180_BCR0H: case Z180_BCR0H:
LOG(("Z180 #%d BCR0H wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_BCR0H_WMASK)); LOG(("Z180 '%s' BCR0H wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_BCR0H_WMASK));
IO_BCR0H = (IO_BCR0H & ~Z180_BCR0H_WMASK) | (data & Z180_BCR0H_WMASK); IO_BCR0H = (IO_BCR0H & ~Z180_BCR0H_WMASK) | (data & Z180_BCR0H_WMASK);
break; break;
case Z180_MAR1L: case Z180_MAR1L:
LOG(("Z180 #%d MAR1L wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_MAR1L_WMASK)); LOG(("Z180 '%s' MAR1L wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_MAR1L_WMASK));
IO_MAR1L = (IO_MAR1L & ~Z180_MAR1L_WMASK) | (data & Z180_MAR1L_WMASK); IO_MAR1L = (IO_MAR1L & ~Z180_MAR1L_WMASK) | (data & Z180_MAR1L_WMASK);
break; break;
case Z180_MAR1H: case Z180_MAR1H:
LOG(("Z180 #%d MAR1H wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_MAR1H_WMASK)); LOG(("Z180 '%s' MAR1H wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_MAR1H_WMASK));
IO_MAR1H = (IO_MAR1H & ~Z180_MAR1H_WMASK) | (data & Z180_MAR1H_WMASK); IO_MAR1H = (IO_MAR1H & ~Z180_MAR1H_WMASK) | (data & Z180_MAR1H_WMASK);
break; break;
case Z180_MAR1B: case Z180_MAR1B:
LOG(("Z180 #%d MAR1B wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_MAR1B_WMASK)); LOG(("Z180 '%s' MAR1B wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_MAR1B_WMASK));
IO_MAR1B = (IO_MAR1B & ~Z180_MAR1B_WMASK) | (data & Z180_MAR1B_WMASK); IO_MAR1B = (IO_MAR1B & ~Z180_MAR1B_WMASK) | (data & Z180_MAR1B_WMASK);
break; break;
case Z180_IAR1L: case Z180_IAR1L:
LOG(("Z180 #%d IAR1L wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_IAR1L_WMASK)); LOG(("Z180 '%s' IAR1L wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_IAR1L_WMASK));
IO_IAR1L = (IO_IAR1L & ~Z180_IAR1L_WMASK) | (data & Z180_IAR1L_WMASK); IO_IAR1L = (IO_IAR1L & ~Z180_IAR1L_WMASK) | (data & Z180_IAR1L_WMASK);
break; break;
case Z180_IAR1H: case Z180_IAR1H:
LOG(("Z180 #%d IAR1H wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_IAR1H_WMASK)); LOG(("Z180 '%s' IAR1H wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_IAR1H_WMASK));
IO_IAR1H = (IO_IAR1H & ~Z180_IAR1H_WMASK) | (data & Z180_IAR1H_WMASK); IO_IAR1H = (IO_IAR1H & ~Z180_IAR1H_WMASK) | (data & Z180_IAR1H_WMASK);
break; break;
case Z180_IAR1B: case Z180_IAR1B:
LOG(("Z180 #%d IAR1B wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_IAR1B_WMASK)); LOG(("Z180 '%s' IAR1B wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_IAR1B_WMASK));
IO_IAR1B = (IO_IAR1B & ~Z180_IAR1B_WMASK) | (data & Z180_IAR1B_WMASK); IO_IAR1B = (IO_IAR1B & ~Z180_IAR1B_WMASK) | (data & Z180_IAR1B_WMASK);
break; break;
case Z180_BCR1L: case Z180_BCR1L:
LOG(("Z180 #%d BCR1L wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_BCR1L_WMASK)); LOG(("Z180 '%s' BCR1L wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_BCR1L_WMASK));
IO_BCR1L = (IO_BCR1L & ~Z180_BCR1L_WMASK) | (data & Z180_BCR1L_WMASK); IO_BCR1L = (IO_BCR1L & ~Z180_BCR1L_WMASK) | (data & Z180_BCR1L_WMASK);
break; break;
case Z180_BCR1H: case Z180_BCR1H:
LOG(("Z180 #%d BCR1H wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_BCR1H_WMASK)); LOG(("Z180 '%s' BCR1H wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_BCR1H_WMASK));
IO_BCR1H = (IO_BCR1H & ~Z180_BCR1H_WMASK) | (data & Z180_BCR1H_WMASK); IO_BCR1H = (IO_BCR1H & ~Z180_BCR1H_WMASK) | (data & Z180_BCR1H_WMASK);
break; break;
case Z180_DSTAT: case Z180_DSTAT:
LOG(("Z180 #%d DSTAT wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_DSTAT_WMASK)); LOG(("Z180 '%s' DSTAT wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_DSTAT_WMASK));
IO_DSTAT = (IO_DSTAT & ~Z180_DSTAT_WMASK) | (data & Z180_DSTAT_WMASK); IO_DSTAT = (IO_DSTAT & ~Z180_DSTAT_WMASK) | (data & Z180_DSTAT_WMASK);
if ((data & (Z180_DSTAT_DE1 | Z180_DSTAT_DWE1)) == Z180_DSTAT_DE1) if ((data & (Z180_DSTAT_DE1 | Z180_DSTAT_DWE1)) == Z180_DSTAT_DE1)
IO_DSTAT |= Z180_DSTAT_DME; /* DMA enable */ IO_DSTAT |= Z180_DSTAT_DME; /* DMA enable */
@ -1505,80 +1505,80 @@ static void z180_writecontrol(offs_t port, UINT8 data)
break; break;
case Z180_DMODE: case Z180_DMODE:
LOG(("Z180 #%d DMODE wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_DMODE_WMASK)); LOG(("Z180 '%s' DMODE wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_DMODE_WMASK));
IO_DMODE = (IO_DMODE & ~Z180_DMODE_WMASK) | (data & Z180_DMODE_WMASK); IO_DMODE = (IO_DMODE & ~Z180_DMODE_WMASK) | (data & Z180_DMODE_WMASK);
break; break;
case Z180_DCNTL: case Z180_DCNTL:
LOG(("Z180 #%d DCNTL wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_DCNTL_WMASK)); LOG(("Z180 '%s' DCNTL wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_DCNTL_WMASK));
IO_DCNTL = (IO_DCNTL & ~Z180_DCNTL_WMASK) | (data & Z180_DCNTL_WMASK); IO_DCNTL = (IO_DCNTL & ~Z180_DCNTL_WMASK) | (data & Z180_DCNTL_WMASK);
break; break;
case Z180_IL: case Z180_IL:
LOG(("Z180 #%d IL wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_IL_WMASK)); LOG(("Z180 '%s' IL wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_IL_WMASK));
IO_IL = (IO_IL & ~Z180_IL_WMASK) | (data & Z180_IL_WMASK); IO_IL = (IO_IL & ~Z180_IL_WMASK) | (data & Z180_IL_WMASK);
break; break;
case Z180_ITC: case Z180_ITC:
LOG(("Z180 #%d ITC wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_ITC_WMASK)); LOG(("Z180 '%s' ITC wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_ITC_WMASK));
IO_ITC = (IO_ITC & ~Z180_ITC_WMASK) | (data & Z180_ITC_WMASK); IO_ITC = (IO_ITC & ~Z180_ITC_WMASK) | (data & Z180_ITC_WMASK);
break; break;
case Z180_IO35: case Z180_IO35:
LOG(("Z180 #%d IO35 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_IO35_WMASK)); LOG(("Z180 '%s' IO35 wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_IO35_WMASK));
IO_IO35 = (IO_IO35 & ~Z180_IO35_WMASK) | (data & Z180_IO35_WMASK); IO_IO35 = (IO_IO35 & ~Z180_IO35_WMASK) | (data & Z180_IO35_WMASK);
break; break;
case Z180_RCR: case Z180_RCR:
LOG(("Z180 #%d RCR wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_RCR_WMASK)); LOG(("Z180 '%s' RCR wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_RCR_WMASK));
IO_RCR = (IO_RCR & ~Z180_RCR_WMASK) | (data & Z180_RCR_WMASK); IO_RCR = (IO_RCR & ~Z180_RCR_WMASK) | (data & Z180_RCR_WMASK);
break; break;
case Z180_IO37: case Z180_IO37:
LOG(("Z180 #%d IO37 wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_IO37_WMASK)); LOG(("Z180 '%s' IO37 wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_IO37_WMASK));
IO_IO37 = (IO_IO37 & ~Z180_IO37_WMASK) | (data & Z180_IO37_WMASK); IO_IO37 = (IO_IO37 & ~Z180_IO37_WMASK) | (data & Z180_IO37_WMASK);
break; break;
case Z180_CBR: case Z180_CBR:
LOG(("Z180 #%d CBR wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_CBR_WMASK)); LOG(("Z180 '%s' CBR wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_CBR_WMASK));
IO_CBR = (IO_CBR & ~Z180_CBR_WMASK) | (data & Z180_CBR_WMASK); IO_CBR = (IO_CBR & ~Z180_CBR_WMASK) | (data & Z180_CBR_WMASK);
z180_mmu(); z180_mmu();
break; break;
case Z180_BBR: case Z180_BBR:
LOG(("Z180 #%d BBR wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_BBR_WMASK)); LOG(("Z180 '%s' BBR wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_BBR_WMASK));
IO_BBR = (IO_BBR & ~Z180_BBR_WMASK) | (data & Z180_BBR_WMASK); IO_BBR = (IO_BBR & ~Z180_BBR_WMASK) | (data & Z180_BBR_WMASK);
z180_mmu(); z180_mmu();
break; break;
case Z180_CBAR: case Z180_CBAR:
LOG(("Z180 #%d CBAR wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_CBAR_WMASK)); LOG(("Z180 '%s' CBAR wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_CBAR_WMASK));
IO_CBAR = (IO_CBAR & ~Z180_CBAR_WMASK) | (data & Z180_CBAR_WMASK); IO_CBAR = (IO_CBAR & ~Z180_CBAR_WMASK) | (data & Z180_CBAR_WMASK);
z180_mmu(); z180_mmu();
break; break;
case Z180_IO3B: case Z180_IO3B:
LOG(("Z180 #%d IO3B wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_IO3B_WMASK)); LOG(("Z180 '%s' IO3B wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_IO3B_WMASK));
IO_IO3B = (IO_IO3B & ~Z180_IO3B_WMASK) | (data & Z180_IO3B_WMASK); IO_IO3B = (IO_IO3B & ~Z180_IO3B_WMASK) | (data & Z180_IO3B_WMASK);
break; break;
case Z180_IO3C: case Z180_IO3C:
LOG(("Z180 #%d IO3C wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_IO3C_WMASK)); LOG(("Z180 '%s' IO3C wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_IO3C_WMASK));
IO_IO3C = (IO_IO3C & ~Z180_IO3C_WMASK) | (data & Z180_IO3C_WMASK); IO_IO3C = (IO_IO3C & ~Z180_IO3C_WMASK) | (data & Z180_IO3C_WMASK);
break; break;
case Z180_IO3D: case Z180_IO3D:
LOG(("Z180 #%d IO3D wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_IO3D_WMASK)); LOG(("Z180 '%s' IO3D wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_IO3D_WMASK));
IO_IO3D = (IO_IO3D & ~Z180_IO3D_WMASK) | (data & Z180_IO3D_WMASK); IO_IO3D = (IO_IO3D & ~Z180_IO3D_WMASK) | (data & Z180_IO3D_WMASK);
break; break;
case Z180_OMCR: case Z180_OMCR:
LOG(("Z180 #%d OMCR wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_OMCR_WMASK)); LOG(("Z180 '%s' OMCR wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_OMCR_WMASK));
IO_OMCR = (IO_OMCR & ~Z180_OMCR_WMASK) | (data & Z180_OMCR_WMASK); IO_OMCR = (IO_OMCR & ~Z180_OMCR_WMASK) | (data & Z180_OMCR_WMASK);
break; break;
case Z180_IOCR: case Z180_IOCR:
LOG(("Z180 #%d IOCR wr $%02x ($%02x)\n", cpunum_get_active(), data, data & Z180_IOCR_WMASK)); LOG(("Z180 '%s' IOCR wr $%02x ($%02x)\n", Z180.device->tag, data, data & Z180_IOCR_WMASK));
IO_IOCR = (IO_IOCR & ~Z180_IOCR_WMASK) | (data & Z180_IOCR_WMASK); IO_IOCR = (IO_IOCR & ~Z180_IOCR_WMASK) | (data & Z180_IOCR_WMASK);
break; break;
} }
@ -1781,120 +1781,120 @@ static void z180_write_iolines(UINT32 data)
/* I/O asynchronous clock 0 (active high) or DREQ0 (mux) */ /* I/O asynchronous clock 0 (active high) or DREQ0 (mux) */
if (changes & Z180_CKA0) if (changes & Z180_CKA0)
{ {
LOG(("Z180 #%d CKA0 %d\n", cpunum_get_active(), data & Z180_CKA0 ? 1 : 0)); LOG(("Z180 '%s' CKA0 %d\n", Z180.device->tag, data & Z180_CKA0 ? 1 : 0));
Z180.iol = (Z180.iol & ~Z180_CKA0) | (data & Z180_CKA0); Z180.iol = (Z180.iol & ~Z180_CKA0) | (data & Z180_CKA0);
} }
/* I/O asynchronous clock 1 (active high) or TEND1 (mux) */ /* I/O asynchronous clock 1 (active high) or TEND1 (mux) */
if (changes & Z180_CKA1) if (changes & Z180_CKA1)
{ {
LOG(("Z180 #%d CKA1 %d\n", cpunum_get_active(), data & Z180_CKA1 ? 1 : 0)); LOG(("Z180 '%s' CKA1 %d\n", Z180.device->tag, data & Z180_CKA1 ? 1 : 0));
Z180.iol = (Z180.iol & ~Z180_CKA1) | (data & Z180_CKA1); Z180.iol = (Z180.iol & ~Z180_CKA1) | (data & Z180_CKA1);
} }
/* I/O serial clock (active high) */ /* I/O serial clock (active high) */
if (changes & Z180_CKS) if (changes & Z180_CKS)
{ {
LOG(("Z180 #%d CKS %d\n", cpunum_get_active(), data & Z180_CKS ? 1 : 0)); LOG(("Z180 '%s' CKS %d\n", Z180.device->tag, data & Z180_CKS ? 1 : 0));
Z180.iol = (Z180.iol & ~Z180_CKS) | (data & Z180_CKS); Z180.iol = (Z180.iol & ~Z180_CKS) | (data & Z180_CKS);
} }
/* I clear to send 0 (active low) */ /* I clear to send 0 (active low) */
if (changes & Z180_CTS0) if (changes & Z180_CTS0)
{ {
LOG(("Z180 #%d CTS0 %d\n", cpunum_get_active(), data & Z180_CTS0 ? 1 : 0)); LOG(("Z180 '%s' CTS0 %d\n", Z180.device->tag, data & Z180_CTS0 ? 1 : 0));
Z180.iol = (Z180.iol & ~Z180_CTS0) | (data & Z180_CTS0); Z180.iol = (Z180.iol & ~Z180_CTS0) | (data & Z180_CTS0);
} }
/* I clear to send 1 (active low) or RXS (mux) */ /* I clear to send 1 (active low) or RXS (mux) */
if (changes & Z180_CTS1) if (changes & Z180_CTS1)
{ {
LOG(("Z180 #%d CTS1 %d\n", cpunum_get_active(), data & Z180_CTS1 ? 1 : 0)); LOG(("Z180 '%s' CTS1 %d\n", Z180.device->tag, data & Z180_CTS1 ? 1 : 0));
Z180.iol = (Z180.iol & ~Z180_CTS1) | (data & Z180_CTS1); Z180.iol = (Z180.iol & ~Z180_CTS1) | (data & Z180_CTS1);
} }
/* I data carrier detect (active low) */ /* I data carrier detect (active low) */
if (changes & Z180_DCD0) if (changes & Z180_DCD0)
{ {
LOG(("Z180 #%d DCD0 %d\n", cpunum_get_active(), data & Z180_DCD0 ? 1 : 0)); LOG(("Z180 '%s' DCD0 %d\n", Z180.device->tag, data & Z180_DCD0 ? 1 : 0));
Z180.iol = (Z180.iol & ~Z180_DCD0) | (data & Z180_DCD0); Z180.iol = (Z180.iol & ~Z180_DCD0) | (data & Z180_DCD0);
} }
/* I data request DMA ch 0 (active low) or CKA0 (mux) */ /* I data request DMA ch 0 (active low) or CKA0 (mux) */
if (changes & Z180_DREQ0) if (changes & Z180_DREQ0)
{ {
LOG(("Z180 #%d DREQ0 %d\n", cpunum_get_active(), data & Z180_DREQ0 ? 1 : 0)); LOG(("Z180 '%s' DREQ0 %d\n", Z180.device->tag, data & Z180_DREQ0 ? 1 : 0));
Z180.iol = (Z180.iol & ~Z180_DREQ0) | (data & Z180_DREQ0); Z180.iol = (Z180.iol & ~Z180_DREQ0) | (data & Z180_DREQ0);
} }
/* I data request DMA ch 1 (active low) */ /* I data request DMA ch 1 (active low) */
if (changes & Z180_DREQ1) if (changes & Z180_DREQ1)
{ {
LOG(("Z180 #%d DREQ1 %d\n", cpunum_get_active(), data & Z180_DREQ1 ? 1 : 0)); LOG(("Z180 '%s' DREQ1 %d\n", Z180.device->tag, data & Z180_DREQ1 ? 1 : 0));
Z180.iol = (Z180.iol & ~Z180_DREQ1) | (data & Z180_DREQ1); Z180.iol = (Z180.iol & ~Z180_DREQ1) | (data & Z180_DREQ1);
} }
/* I asynchronous receive data 0 (active high) */ /* I asynchronous receive data 0 (active high) */
if (changes & Z180_RXA0) if (changes & Z180_RXA0)
{ {
LOG(("Z180 #%d RXA0 %d\n", cpunum_get_active(), data & Z180_RXA0 ? 1 : 0)); LOG(("Z180 '%s' RXA0 %d\n", Z180.device->tag, data & Z180_RXA0 ? 1 : 0));
Z180.iol = (Z180.iol & ~Z180_RXA0) | (data & Z180_RXA0); Z180.iol = (Z180.iol & ~Z180_RXA0) | (data & Z180_RXA0);
} }
/* I asynchronous receive data 1 (active high) */ /* I asynchronous receive data 1 (active high) */
if (changes & Z180_RXA1) if (changes & Z180_RXA1)
{ {
LOG(("Z180 #%d RXA1 %d\n", cpunum_get_active(), data & Z180_RXA1 ? 1 : 0)); LOG(("Z180 '%s' RXA1 %d\n", Z180.device->tag, data & Z180_RXA1 ? 1 : 0));
Z180.iol = (Z180.iol & ~Z180_RXA1) | (data & Z180_RXA1); Z180.iol = (Z180.iol & ~Z180_RXA1) | (data & Z180_RXA1);
} }
/* I clocked serial receive data (active high) or CTS1 (mux) */ /* I clocked serial receive data (active high) or CTS1 (mux) */
if (changes & Z180_RXS) if (changes & Z180_RXS)
{ {
LOG(("Z180 #%d RXS %d\n", cpunum_get_active(), data & Z180_RXS ? 1 : 0)); LOG(("Z180 '%s' RXS %d\n", Z180.device->tag, data & Z180_RXS ? 1 : 0));
Z180.iol = (Z180.iol & ~Z180_RXS) | (data & Z180_RXS); Z180.iol = (Z180.iol & ~Z180_RXS) | (data & Z180_RXS);
} }
/* O request to send (active low) */ /* O request to send (active low) */
if (changes & Z180_RTS0) if (changes & Z180_RTS0)
{ {
LOG(("Z180 #%d RTS0 won't change output\n", cpunum_get_active())); LOG(("Z180 '%s' RTS0 won't change output\n", Z180.device->tag));
} }
/* O transfer end 0 (active low) or CKA1 (mux) */ /* O transfer end 0 (active low) or CKA1 (mux) */
if (changes & Z180_TEND0) if (changes & Z180_TEND0)
{ {
LOG(("Z180 #%d TEND0 won't change output\n", cpunum_get_active())); LOG(("Z180 '%s' TEND0 won't change output\n", Z180.device->tag));
} }
/* O transfer end 1 (active low) */ /* O transfer end 1 (active low) */
if (changes & Z180_TEND1) if (changes & Z180_TEND1)
{ {
LOG(("Z180 #%d TEND1 won't change output\n", cpunum_get_active())); LOG(("Z180 '%s' TEND1 won't change output\n", Z180.device->tag));
} }
/* O transfer out (PRT channel, active low) or A18 (mux) */ /* O transfer out (PRT channel, active low) or A18 (mux) */
if (changes & Z180_A18_TOUT) if (changes & Z180_A18_TOUT)
{ {
LOG(("Z180 #%d TOUT won't change output\n", cpunum_get_active())); LOG(("Z180 '%s' TOUT won't change output\n", Z180.device->tag));
} }
/* O asynchronous transmit data 0 (active high) */ /* O asynchronous transmit data 0 (active high) */
if (changes & Z180_TXA0) if (changes & Z180_TXA0)
{ {
LOG(("Z180 #%d TXA0 won't change output\n", cpunum_get_active())); LOG(("Z180 '%s' TXA0 won't change output\n", Z180.device->tag));
} }
/* O asynchronous transmit data 1 (active high) */ /* O asynchronous transmit data 1 (active high) */
if (changes & Z180_TXA1) if (changes & Z180_TXA1)
{ {
LOG(("Z180 #%d TXA1 won't change output\n", cpunum_get_active())); LOG(("Z180 '%s' TXA1 won't change output\n", Z180.device->tag));
} }
/* O clocked serial transmit data (active high) */ /* O clocked serial transmit data (active high) */
if (changes & Z180_TXS) if (changes & Z180_TXS)
{ {
LOG(("Z180 #%d TXS won't change output\n", cpunum_get_active())); LOG(("Z180 '%s' TXS won't change output\n", Z180.device->tag));
} }
} }
@ -2200,7 +2200,7 @@ static CPU_EXECUTE( z180 )
/* to just check here */ /* to just check here */
if (Z180.nmi_pending) if (Z180.nmi_pending)
{ {
LOG(("Z180 #%d take NMI\n", cpunum_get_active())); LOG(("Z180 '%s' take NMI\n", Z180.device->tag));
_PPC = -1; /* there isn't a valid previous program counter */ _PPC = -1; /* there isn't a valid previous program counter */
LEAVE_HALT; /* Check if processor was halted */ LEAVE_HALT; /* Check if processor was halted */
@ -2337,7 +2337,7 @@ static void set_irq_line(int irqline, int state)
} }
else else
{ {
LOG(("Z180 #%d set_irq_line %d = %d\n",cpunum_get_active() , irqline,state)); LOG(("Z180 '%s' set_irq_line %d = %d\n",Z180.device->tag , irqline,state));
/* update the IRQ state */ /* update the IRQ state */
Z180.irq_state[irqline] = state; Z180.irq_state[irqline] = state;