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https://github.com/holub/mame
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decstation.cpp: added more devices, now runs enough to give an interactive PROM monitor. [R. Belmont]
This commit is contained in:
arbee
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16336848af
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0e210f4347
@ -6,6 +6,10 @@
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WANTED: all boot ROM dumps except 5000/133, all TURBOchannel card ROM dumps
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NOTE: after all the spew of failing tests (it really wants a VT102 terminal),
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press 'q' at the MORE prompt and wait a few seconds for the PROM monitor to appear.
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Type 'ls' for a list of commands (this is a very UNIX-flavored PROM monitor).
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Machine types:
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DECstation 3100 (PMAX/KN01):
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16.67 MHz R2000 with FPU and MMU
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@ -55,6 +59,13 @@
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#include "emu.h"
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#include "cpu/mips/r3000.h"
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#include "machine/decioga.h"
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#include "machine/mc146818.h"
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#include "machine/z80scc.h"
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#include "machine/ncr5390.h"
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#include "machine/nscsi_bus.h"
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#include "machine/nscsi_cd.h"
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#include "machine/nscsi_hd.h"
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#include "bus/rs232/rs232.h"
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class decstation_state : public driver_device
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{
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@ -62,19 +73,35 @@ public:
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decstation_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag) ,
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m_maincpu(*this, "maincpu"),
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m_ioga(*this, "ioga")
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m_ioga(*this, "ioga"),
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m_rtc(*this, "rtc"),
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m_scc0(*this, "scc0"),
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m_scc1(*this, "scc1"),
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m_asc(*this, "scsibus:7:asc")
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{ }
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void kn02da(machine_config &config);
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void init_decstation();
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protected:
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DECLARE_READ_LINE_MEMBER(brcond0_r) { return ASSERT_LINE; }
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DECLARE_READ32_MEMBER(cfb_r);
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DECLARE_WRITE32_MEMBER(cfb_w);
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void ncr5394(device_t *device);
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private:
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virtual void machine_start() override;
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virtual void machine_reset() override;
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virtual void video_start() override;
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required_device<cpu_device> m_maincpu;
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required_device<dec_ioga_device> m_ioga;
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required_device<mc146818_device> m_rtc;
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required_device<z80scc_device> m_scc0, m_scc1;
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required_device<ncr53c94_device> m_asc;
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void decstation_map(address_map &map);
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};
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@ -82,8 +109,59 @@ private:
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VIDEO HARDWARE
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***************************************************************************/
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void decstation_state::video_start()
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READ32_MEMBER(decstation_state::cfb_r)
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{
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static const char fwver[8] = "V5.3a ";
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static const char fwvendor[8] = "DEC ";
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static const char fwmodule[8] = "PMAG-BA";
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static const char fwtype[8] = "TCF0 ";
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static const char fwinfo[8] = "CX - D8";
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uint32_t addr = offset << 2;
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logerror("cfb_r: reading at %x\n", addr);
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// attempt to fake the ROM ID bytes of a PMAG-BA
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// color framebuffer card. doesn't work for unknown reasons.
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if ((addr >= 0x3c0400) && (addr < 0x3c0420))
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{
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return fwver[(addr>>2)&0x7];
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}
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if ((addr >= 0x3c0420) && (addr < 0x3c0440))
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{
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return fwvendor[(addr>>2)&0x7];
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}
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if ((addr >= 0x3c0440) && (addr < 0x3c0460))
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{
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return fwmodule[(addr>>2)&0x7];
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}
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if ((addr >= 0x3c0460) && (addr < 0x3c0480))
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{
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return fwtype[(addr>>2)&0x7];
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}
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if ((addr >= 0x3c0480) && (addr < 0x3c04a0))
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{
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return fwinfo[(addr>>2)&0x7];
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}
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switch (addr)
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{
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case 0x3c03e0: return 1; // ROM width
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case 0x3c03e4: return 4; // ROM stride
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case 0x3c03e8: return 1; // ROM size in 8 KiB units
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case 0x3c03ec: return 1; // card address space in 4 MiB units
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case 0x3c03f0: return 0x55555555; // TURBOchannel ID bytes
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case 0x3c03f4: return 0x00000000;
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case 0x3c03f8: return 0xaaaaaaaa;
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case 0x3c03fc: return 0xffffffff;
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case 0x3c0470: return 0; // does card support parity?
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}
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return 0xffffffff;
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}
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WRITE32_MEMBER(decstation_state::cfb_w)
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{
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logerror("cfb: %08x (mask %08x) @ %x\n", data, mem_mask, offset);
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}
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/***************************************************************************
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@ -105,7 +183,18 @@ void decstation_state::machine_reset()
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void decstation_state::decstation_map(address_map &map)
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{
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map(0x00000000, 0x07ffffff).ram(); // full 128 MB
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map(0x1c000000, 0x1dffffff).m(m_ioga, FUNC(dec_ioga_device::map));
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map(0x10000000, 0x103cffff).rw(FUNC(decstation_state::cfb_r), FUNC(decstation_state::cfb_w));
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map(0x1c000000, 0x1c07ffff).m(m_ioga, FUNC(dec_ioga_device::map));
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map(0x1c100000, 0x1c100003).rw(m_scc0, FUNC(z80scc_device::ca_r), FUNC(z80scc_device::ca_w)).umask32(0x0000ff00);
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map(0x1c100004, 0x1c100007).rw(m_scc0, FUNC(z80scc_device::da_r), FUNC(z80scc_device::da_w)).umask32(0x0000ff00);
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map(0x1c100008, 0x1c10000b).rw(m_scc0, FUNC(z80scc_device::cb_r), FUNC(z80scc_device::cb_w)).umask32(0x0000ff00);
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map(0x1c10000c, 0x1c10000f).rw(m_scc0, FUNC(z80scc_device::db_r), FUNC(z80scc_device::db_w)).umask32(0x0000ff00);
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map(0x1c180000, 0x1c180003).rw(m_scc1, FUNC(z80scc_device::ca_r), FUNC(z80scc_device::ca_w)).umask32(0x0000ff00);
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map(0x1c180004, 0x1c180007).rw(m_scc1, FUNC(z80scc_device::da_r), FUNC(z80scc_device::da_w)).umask32(0x0000ff00);
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map(0x1c180008, 0x1c18000b).rw(m_scc1, FUNC(z80scc_device::cb_r), FUNC(z80scc_device::cb_w)).umask32(0x0000ff00);
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map(0x1c18000c, 0x1c18000f).rw(m_scc1, FUNC(z80scc_device::db_r), FUNC(z80scc_device::db_w)).umask32(0x0000ff00);
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map(0x1c200000, 0x1c2000ff).rw(m_rtc, FUNC(mc146818_device::read_direct), FUNC(mc146818_device::write_direct)).umask32(0x000000ff);
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map(0x1c300000, 0x1c30003f).m(m_asc, FUNC(ncr53c94_device::map)).umask32(0x000000ff);
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map(0x1fc00000, 0x1fc3ffff).rom().region("user1", 0);
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}
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@ -113,12 +202,60 @@ void decstation_state::decstation_map(address_map &map)
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MACHINE DRIVERS
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***************************************************************************/
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void decstation_state::ncr5394(device_t *device)
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{
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devcb_base *devcb;
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(void)devcb;
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MCFG_DEVICE_CLOCK(10000000)
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}
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static void dec_scsi_devices(device_slot_interface &device)
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{
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device.option_add("cdrom", NSCSI_CDROM);
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device.option_add("harddisk", NSCSI_HARDDISK);
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device.option_add_internal("asc", NCR53C94);
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}
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MACHINE_CONFIG_START(decstation_state::kn02da)
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MCFG_DEVICE_ADD( "maincpu", R3041, 33000000 ) // FIXME: Should be R2000
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MCFG_DEVICE_ADD( "maincpu", R3041, 33000000 ) // FIXME: Should be R3000A
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MCFG_R3000_ENDIANNESS(ENDIANNESS_LITTLE)
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MCFG_R3000_BRCOND0_INPUT(READLINE(*this, decstation_state, brcond0_r))
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MCFG_DEVICE_PROGRAM_MAP( decstation_map )
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MCFG_DEVICE_ADD("ioga", DECSTATION_IOGA, XTAL(12'500'000))
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MCFG_DEVICE_ADD("rtc", MC146818, XTAL(32'768))
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MCFG_MC146818_IRQ_HANDLER(WRITELINE("ioga", dec_ioga_device, rtc_irq_w))
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MCFG_MC146818_BINARY(true)
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MCFG_DEVICE_ADD("scc0", SCC85C30, XTAL(14'745'600)/2)
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//MCFG_Z80SCC_OUT_INT_CB(WRITELINE("ioga", dec_ioga_device, scc0_irq_w))
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MCFG_DEVICE_ADD("scc1", SCC85C30, XTAL(14'745'600)/2)
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//MCFG_Z80SCC_OUT_INT_CB(WRITELINE("ioga", dec_ioga_device, scc1_irq_w))
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MCFG_Z80SCC_OUT_TXDA_CB(WRITELINE("rs232a", rs232_port_device, write_txd))
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MCFG_Z80SCC_OUT_TXDB_CB(WRITELINE("rs232b", rs232_port_device, write_txd))
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MCFG_DEVICE_ADD("rs232a", RS232_PORT, default_rs232_devices, "terminal")
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MCFG_RS232_RXD_HANDLER(WRITELINE("scc1", z80scc_device, rxa_w))
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MCFG_RS232_DCD_HANDLER(WRITELINE("scc1", z80scc_device, dcda_w))
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MCFG_RS232_CTS_HANDLER(WRITELINE("scc1", z80scc_device, ctsa_w))
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MCFG_DEVICE_ADD("rs232b", RS232_PORT, default_rs232_devices, nullptr)
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MCFG_RS232_RXD_HANDLER(WRITELINE("scc1", z80scc_device, rxb_w))
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MCFG_RS232_DCD_HANDLER(WRITELINE("scc1", z80scc_device, dcdb_w))
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MCFG_RS232_CTS_HANDLER(WRITELINE("scc1", z80scc_device, ctsb_w))
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MCFG_NSCSI_BUS_ADD("scsibus")
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MCFG_NSCSI_ADD("scsibus:0", dec_scsi_devices, "harddisk", false)
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MCFG_NSCSI_ADD("scsibus:1", dec_scsi_devices, "cdrom", false)
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MCFG_NSCSI_ADD("scsibus:2", dec_scsi_devices, nullptr, false)
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MCFG_NSCSI_ADD("scsibus:3", dec_scsi_devices, nullptr, false)
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MCFG_NSCSI_ADD("scsibus:4", dec_scsi_devices, nullptr, false)
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MCFG_NSCSI_ADD("scsibus:5", dec_scsi_devices, nullptr, false)
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MCFG_NSCSI_ADD("scsibus:6", dec_scsi_devices, nullptr, false)
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MCFG_NSCSI_ADD("scsibus:7", dec_scsi_devices, "asc", true)
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MCFG_SLOT_OPTION_MACHINE_CONFIG("asc", [this] (device_t *device) { ncr5394(device); })
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MACHINE_CONFIG_END
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static INPUT_PORTS_START( decstation )
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@ -3,8 +3,8 @@
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/******************************************************************************
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*
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* MIPS DECstation I/O Gate Array emulation
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*
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*
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* This IC contains some address decoding, an interrupt controller, and
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* a multi-channel DMA engine.
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*/
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#include "decioga.h"
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@ -13,7 +13,9 @@ DEFINE_DEVICE_TYPE(DECSTATION_IOGA, dec_ioga_device, "decioga", "DECstation I/O
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void dec_ioga_device::map(address_map &map)
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{
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map(0x040100, 0x040103).rw(FUNC(dec_ioga_device::csr_r), FUNC(dec_ioga_device::csr_w));
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map(0x040100, 0x040103).rw(FUNC(dec_ioga_device::csr_r), FUNC(dec_ioga_device::csr_w));
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map(0x040110, 0x040113).rw(FUNC(dec_ioga_device::intr_r), FUNC(dec_ioga_device::intr_w));
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map(0x040120, 0x040123).rw(FUNC(dec_ioga_device::imsk_r), FUNC(dec_ioga_device::imsk_w));
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}
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dec_ioga_device::dec_ioga_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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@ -24,10 +26,13 @@ dec_ioga_device::dec_ioga_device(const machine_config &mconfig, const char *tag,
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void dec_ioga_device::device_start()
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{
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save_item(NAME(m_csr));
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save_item(NAME(m_intr));
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save_item(NAME(m_imsk));
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}
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void dec_ioga_device::device_reset()
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{
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m_csr = m_intr = m_imsk = 0;
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}
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READ32_MEMBER(dec_ioga_device::csr_r)
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@ -46,4 +51,35 @@ WRITE32_MEMBER(dec_ioga_device::csr_w)
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}
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printf("]\n");
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#endif
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}
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READ32_MEMBER(dec_ioga_device::intr_r)
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{
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uint32_t rv = m_intr;
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m_intr &= ~0x20; // 5000/133 boot ROM tests that reading clears this bit
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//printf("m_intr = %08x\n", m_intr);
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return rv;
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}
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WRITE32_MEMBER(dec_ioga_device::intr_w)
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{
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m_intr &= ~data; // clear bits on write
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}
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READ32_MEMBER(dec_ioga_device::imsk_r)
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{
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return m_imsk;
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}
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WRITE32_MEMBER(dec_ioga_device::imsk_w)
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{
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COMBINE_DATA(&m_imsk);
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}
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WRITE_LINE_MEMBER(dec_ioga_device::rtc_irq_w)
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{
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if (state == ASSERT_LINE)
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{
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m_intr |= 0x20; // tested by 5000/133 boot ROM circa BFC027C8
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}
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}
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@ -26,15 +26,21 @@ public:
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void map(address_map &map);
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// irq inputs
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DECLARE_WRITE_LINE_MEMBER(rtc_irq_w);
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protected:
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virtual void device_start() override;
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virtual void device_reset() override;
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DECLARE_READ32_MEMBER(csr_r);
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DECLARE_WRITE32_MEMBER(csr_w);
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DECLARE_READ32_MEMBER(intr_r);
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DECLARE_WRITE32_MEMBER(intr_w);
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DECLARE_READ32_MEMBER(imsk_r);
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DECLARE_WRITE32_MEMBER(imsk_w);
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private:
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uint32_t m_csr;
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uint32_t m_csr, m_intr, m_imsk;
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};
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DECLARE_DEVICE_TYPE(DECSTATION_IOGA, dec_ioga_device)
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