mirror of
https://github.com/holub/mame
synced 2025-07-06 18:39:28 +03:00
Cleanups and version bump.
This commit is contained in:
Aaron Giles
parent
5248234004
commit
0e672ba6eb
@ -670,7 +670,7 @@ void ADDRESS_MAP_NAME(_name)(address_map &map, const device_config &devconfig) \
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#define AM_RAM_READ(_read) AM_READ(_read) AM_WRITEONLY
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#define AM_RAM_WRITE(_write) AM_READONLY AM_WRITE(_write)
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#define AM_RAM_DEVREAD(_tag, _read) AM_DEVREAD(_tag, _read) AM_WRITEONLY
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#define AM_RAM_DEVWRITE(_tag, _write) AM_READONLY AM_DEVWRITE(_tag, _write)
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#define AM_RAM_DEVWRITE(_tag, _write) AM_READONLY AM_DEVWRITE(_tag, _write)
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#define AM_BASE_SIZE_MEMBER(_struct, _base, _size) AM_BASE_MEMBER(_struct, _base) AM_SIZE_MEMBER(_struct, _size)
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#define AM_BASE_SIZE_GENERIC(_member) AM_BASE_GENERIC(_member) AM_SIZE_GENERIC(_member)
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@ -1,8 +1,8 @@
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/***************************************************************************
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dsp56dsm.c
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Disassembler for the portable Motorola/Freescale dsp56k emulator.
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Written by Andrew Gardner
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dsp56dsm.c
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Disassembler for the portable Motorola/Freescale dsp56k emulator.
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Written by Andrew Gardner
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***************************************************************************/
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@ -505,8 +505,8 @@ CPU_GET_INFO( dsp56k )
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case CPUINFO_INT_CLOCK_DIVIDER: info->i = 2; break;
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case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break;
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case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break;
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case CPUINFO_INT_MIN_CYCLES: info->i = 1; // ? break;
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case CPUINFO_INT_MAX_CYCLES: info->i = 8; // ? break;
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case CPUINFO_INT_MIN_CYCLES: info->i = 1; // ? break;
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case CPUINFO_INT_MAX_CYCLES: info->i = 8; // ? break;
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case DEVINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 16; break;
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case DEVINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 16; break;
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@ -112,8 +112,8 @@ Instruction* Instruction::decodeInstruction(const Opcode* opc,
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/* No Parallel Data Move : 0100 1010 .... .... : A-131 */
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/* Register to Register Data Move : 0100 IIII .... .... : A-133 */
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/* Address Register Update : 0011 0zRR .... .... : A-135 */
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/* X Memory Data Move : 1mRR HHHW .... .... : A-137 */
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/* X Memory Data Move : 0101 HHHW .... .... : A-137 */
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/* X Memory Data Move : 1mRR HHHW .... .... : A-137 */
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/* X Memory Data Move : 0101 HHHW .... .... : A-137 */
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/* Quote: (32 General parallel move instructions) */
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/****************************************************************/
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else if (((w0 & 0xff00) == 0x4a00) ||
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@ -926,7 +926,7 @@ public:
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bool decode(const UINT16 word0, const UINT16 word1)
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{
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/* Note: This is a JJJF limited in the docs, but other opcodes sneak
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in before cmp, so the same decode function can be used. */
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in before cmp, so the same decode function can be used. */
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decode_JJJF_table(BITSn(word0,0x07), BITSn(word0,0x08),
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m_source, m_destination);
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return true;
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@ -951,7 +951,7 @@ public:
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bool decode(const UINT16 word0, const UINT16 word1)
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{
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/* Note: This is a JJJF limited in the docs, but other opcodes sneak
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in before cmp, so the same decode function can be used. */
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in before cmp, so the same decode function can be used. */
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decode_JJJF_table(BITSn(word0,0x07), BITSn(word0,0x08),
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m_source, m_destination);
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return true;
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@ -2677,7 +2677,7 @@ public:
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bool decode(const UINT16 word0, const UINT16 word1)
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{
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/* There are inconsistencies with the S1 & S2 operand ordering in the docs,
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but since it's a multiply it doesn't matter */
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but since it's a multiply it doesn't matter */
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decode_QQQF_table(BITSn(word0,0x07), BITSn(word0,0x08),
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m_source, m_source2, m_destination);
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@ -2773,7 +2773,7 @@ public:
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bool decode(const UINT16 word0, const UINT16 word1)
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{
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/* There are inconsistencies with the S1 & S2 operand ordering in the docs,
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but since it's a multiply it doesn't matter */
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but since it's a multiply it doesn't matter */
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decode_QQQF_table(BITSn(word0,0x07), BITSn(word0,0x08),
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m_source, m_source2, m_destination);
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@ -211,7 +211,7 @@ public:
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// Don't return a failure, just let everything fall through (nop).
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//if (m_source == "?" && m_destination == "?")
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// return false;
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// return false;
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return true;
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}
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@ -382,8 +382,8 @@ static CPU_SET_INFO( hcd62121 )
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case CPUINFO_INT_REGISTER + HCD62121_IP: cpustate->ip = info->i; break;
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case CPUINFO_INT_REGISTER + HCD62121_SP: cpustate->sp = info->i; break;
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// case CPUINFO_INT_REGISTER + HCD62121_R00: break;
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// case CPUINFO_INT_REGISTER + HCD62121_R02: break;
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// case CPUINFO_INT_REGISTER + HCD62121_R00: break;
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// case CPUINFO_INT_REGISTER + HCD62121_R02: break;
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}
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}
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@ -432,7 +432,7 @@ CPU_GET_INFO( hcd62121 )
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case CPUINFO_INT_REGISTER + HCD62121_SS: info->i = cpustate->sseg; break;
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case CPUINFO_INT_REGISTER + HCD62121_DSIZE: info->i = cpustate->dsize; break;
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case CPUINFO_INT_REGISTER + HCD62121_R00: info->i = ( cpustate->reg[0x00] << 24 ) | ( cpustate->reg[0x01] << 16 ) | ( cpustate->reg[0x02] << 8 ) | cpustate->reg[0x03]; break;
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// case CPUINFO_INT_REGISTER + HCD62121_R02: info->i = cpustate->; break;
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// case CPUINFO_INT_REGISTER + HCD62121_R02: info->i = cpustate->; break;
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/* --- the following bits of info are returned as pointers to data or functions --- */
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case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(hcd62121); break;
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@ -503,7 +503,7 @@ static CPU_EXECUTE( m6809 ) /* NS 970908 */
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m68_state->ireg = ROP(PCD);
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PC++;
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(*m6809_main[m68_state->ireg])(m68_state);
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(*m6809_main[m68_state->ireg])(m68_state);
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m68_state->icount -= cycles1[m68_state->ireg];
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} while( m68_state->icount > 0 );
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@ -14,9 +14,9 @@
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#define OpRead32(s, a) ((s)->direct->read_decrypted_dword(a))
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#else
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#define OpRead8(s, a) ((s)->direct->read_decrypted_byte((a) ^ (s)->fetch_xor))
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#define OpRead16(s, a) (((s)->direct->read_decrypted_byte(((a)+0) ^ (s)->fetch_xor) << 0) | \
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#define OpRead16(s, a) (((s)->direct->read_decrypted_byte(((a)+0) ^ (s)->fetch_xor) << 0) | \
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((s)->direct->read_decrypted_byte(((a)+1) ^ (s)->fetch_xor) << 8))
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#define OpRead32(s, a) (((s)->direct->read_decrypted_byte(((a)+0) ^ (s)->fetch_xor) << 0) | \
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#define OpRead32(s, a) (((s)->direct->read_decrypted_byte(((a)+0) ^ (s)->fetch_xor) << 0) | \
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((s)->direct->read_decrypted_byte(((a)+1) ^ (s)->fetch_xor) << 8) | \
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((s)->direct->read_decrypted_byte(((a)+2) ^ (s)->fetch_xor) << 16) | \
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((s)->direct->read_decrypted_byte(((a)+3) ^ (s)->fetch_xor) << 24))
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@ -37,68 +37,68 @@
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****************************************************************************
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There are many implementations of delegate-like functionality for
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C++ code, but none of them is a perfect drop-in fit for use in MAME.
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In order to be useful in MAME, we need the following properties:
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There are many implementations of delegate-like functionality for
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C++ code, but none of them is a perfect drop-in fit for use in MAME.
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In order to be useful in MAME, we need the following properties:
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* No significant overhead; we want to use these for memory
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accessors, and memory accessor overhead is already the dominant
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performance aspect for most drivers.
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* No significant overhead; we want to use these for memory
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accessors, and memory accessor overhead is already the dominant
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performance aspect for most drivers.
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* Existing static functions need to be bound with an additional
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pointer parameter as the first argument. All existing
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implementations that allow static function binding assume the
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same signature as the member functions.
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* Existing static functions need to be bound with an additional
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pointer parameter as the first argument. All existing
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implementations that allow static function binding assume the
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same signature as the member functions.
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* We must be able to bind the function separately from the
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object. This is to allow configurations to bind functions
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before the objects are created.
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* We must be able to bind the function separately from the
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object. This is to allow configurations to bind functions
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before the objects are created.
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Thus, the implementations below are based on existing works but are
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really a new implementation that is specific to MAME.
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Thus, the implementations below are based on existing works but are
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really a new implementation that is specific to MAME.
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--------------------------------------------------------------------
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--------------------------------------------------------------------
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The "compatible" version of delegates is based on an implementation
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from Sergey Ryazanov, found here:
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The "compatible" version of delegates is based on an implementation
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from Sergey Ryazanov, found here:
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http://www.codeproject.com/KB/cpp/ImpossiblyFastCppDelegate.aspx
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http://www.codeproject.com/KB/cpp/ImpossiblyFastCppDelegate.aspx
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These delegates essentially generate a templated static stub function
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for each target function. The static function takes the first
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parameter, uses it as the object pointer, and calls through the
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member function. For static functions, the stub is compatible with
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the signature of a static function, so we just set the stub directly.
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These delegates essentially generate a templated static stub function
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for each target function. The static function takes the first
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parameter, uses it as the object pointer, and calls through the
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member function. For static functions, the stub is compatible with
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the signature of a static function, so we just set the stub directly.
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Pros:
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* should work with any modern compiler
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* static bindings are just as fast as direct calls
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Pros:
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* should work with any modern compiler
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* static bindings are just as fast as direct calls
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Cons:
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* lots of little stub functions generated
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* double-hops on member function calls means more overhead
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* calling through stub functions repackages parameters
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Cons:
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* lots of little stub functions generated
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* double-hops on member function calls means more overhead
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* calling through stub functions repackages parameters
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--------------------------------------------------------------------
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--------------------------------------------------------------------
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The "internal" version of delegates makes use of the internal
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structure of member function pointers in order to convert them at
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binding time into simple static function pointers. This only works
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on platforms where object->func(p1, p2) is equivalent in calling
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convention to func(object, p1, p2).
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The "internal" version of delegates makes use of the internal
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structure of member function pointers in order to convert them at
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binding time into simple static function pointers. This only works
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on platforms where object->func(p1, p2) is equivalent in calling
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convention to func(object, p1, p2).
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Most of the information on how this works comes from Don Clugston
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in this article:
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Most of the information on how this works comes from Don Clugston
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in this article:
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http://www.codeproject.com/KB/cpp/FastDelegate.aspx
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http://www.codeproject.com/KB/cpp/FastDelegate.aspx
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Pros:
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* as fast as a standard function call in static and member cases
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* no stub functions or double-hops needed
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Pros:
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* as fast as a standard function call in static and member cases
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* no stub functions or double-hops needed
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Cons:
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* requires internal knowledge of the member function pointer
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* only works for GCC (for now; MSVC info is also readily available)
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Cons:
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* requires internal knowledge of the member function pointer
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* only works for GCC (for now; MSVC info is also readily available)
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***************************************************************************/
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@ -125,8 +125,8 @@
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// nicer macros to hide the template gobblety-gook and to pass the names
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#define create_member_name(_class, _member, _name) _create_member<_class, &_class::_member>(_name)
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#define create_member(_class, _member) _create_member<_class, &_class::_member>(#_class "::" #_member)
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#define create_static(_class, _func) _crate_static<_class, &_func>(#_func)
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#define create_member(_class, _member) _create_member<_class, &_class::_member>(#_class "::" #_member)
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#define create_static(_class, _func) _crate_static<_class, &_func>(#_func)
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@ -190,7 +190,7 @@ public:
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const char *name() const { return m_name; }
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protected:
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deferred_cast_func m_caster; // pointer to helper function that does the cast
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deferred_cast_func m_caster; // pointer to helper function that does the cast
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const char * m_name; // name string
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};
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@ -680,7 +680,7 @@ struct delegate_gcc_mfp_internal
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union // first item can be one of two things:
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{
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delegate_generic_function funcptr; // if even, it's a pointer to the function
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FPTR vtable_index; // if odd, it's the byte offset into the vtable
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FPTR vtable_index; // if odd, it's the byte offset into the vtable
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} u;
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int this_delta; // delta to apply to the 'this' pointer
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};
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@ -507,7 +507,7 @@ TIMER_CALLBACK( mos6526_device::clock_tod_callback )
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/*-------------------------------------------------
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cnt_w
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cnt_w
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-------------------------------------------------*/
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void mos6526_device::cnt_w(UINT8 state)
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@ -172,7 +172,7 @@ int ttl74123_device::timer_running()
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/*-------------------------------------------------
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TIMER_CALLBACK( output_callback )
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TIMER_CALLBACK( output_callback )
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-------------------------------------------------*/
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TIMER_CALLBACK( ttl74123_device::output_callback )
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@ -176,7 +176,7 @@ void ttl7474_device::device_reset()
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void ttl7474_device::update()
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{
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if (!m_preset && m_clear) /* line 1 in truth table */
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if (!m_preset && m_clear) /* line 1 in truth table */
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{
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m_output = 1;
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m_output_comp = 0;
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@ -191,7 +191,7 @@ void ttl7474_device::update()
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m_output = 1;
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m_output_comp = 1;
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}
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else if (!m_last_clock && m_clk) /* line 4 in truth table */
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else if (!m_last_clock && m_clk) /* line 4 in truth table */
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{
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m_output = m_d;
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m_output_comp = !m_d;
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@ -139,7 +139,7 @@ private:
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/* inputs */
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UINT8 m_clear; /* pin 1/13 */
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UINT8 m_preset; /* pin 4/10 */
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UINT8 m_clk; /* pin 3/11 */
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UINT8 m_clk; /* pin 3/11 */
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UINT8 m_d; /* pin 2/12 */
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/* outputs */
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@ -284,7 +284,7 @@ void i8237_device::i8237_timerproc()
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/* Check if a new DMA request has been received. */
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/* Bit 6 of the command register determines whether the DREQ signals are active
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high or active low. */
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high or active low. */
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UINT16 pending_request = ( ( m_command & 0x40 ) ? ~m_drq : m_drq ) & ~m_mask;
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if ( pending_request & 0x0f )
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@ -133,7 +133,7 @@ void eeprom_device_config::static_set_default_data(device_config *device, const
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{
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eeprom_device_config *eeprom = downcast<eeprom_device_config *>(device);
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if (eeprom->m_data_bits != 8) mame_printf_warning("16-bit EEPROM set with 8-bit data\n");
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// assert(eeprom->m_data_bits == 8);
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// assert(eeprom->m_data_bits == 8);
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eeprom->m_default_data = data;
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eeprom->m_default_data_size = size;
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}
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@ -142,7 +142,7 @@ void eeprom_device_config::static_set_default_data(device_config *device, const
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{
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eeprom_device_config *eeprom = downcast<eeprom_device_config *>(device);
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if (eeprom->m_data_bits != 16) mame_printf_warning("8-bit EEPROM set with 16-bit data\n");
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// assert(eeprom->m_data_bits == 16);
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// assert(eeprom->m_data_bits == 16);
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eeprom->m_default_data = reinterpret_cast<const UINT8 *>(data);
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eeprom->m_default_data_size = size;
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}
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@ -1,22 +1,22 @@
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/**********************************************************************
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Fairchild F3853 SRAM interface with integrated interrupt
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controller and timer (SMI)
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Fairchild F3853 SRAM interface with integrated interrupt
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controller and timer (SMI)
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This chip is a timer shift register, basically the same as in the
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F3851.
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This chip is a timer shift register, basically the same as in the
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F3851.
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Based on a datasheet obtained from www.freetradezone.com
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Based on a datasheet obtained from www.freetradezone.com
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The SMI does not have DC0 and DC1, only DC0; as a result, it does
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not respond to the main CPU's DC0/DC1 swap instruction. This may
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lead to two devices responding to the same DC0 address and
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attempting to place their bytes on the data bus simultaneously!
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The SMI does not have DC0 and DC1, only DC0; as a result, it does
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not respond to the main CPU's DC0/DC1 swap instruction. This may
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lead to two devices responding to the same DC0 address and
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attempting to place their bytes on the data bus simultaneously!
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8-bit shift register:
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Feedback in0 = !((out3 ^ out4) ^ (out5 ^ out7))
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Interrupts are at 0xfe
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0xff stops the register (0xfe is never reached)
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8-bit shift register:
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Feedback in0 = !((out3 ^ out4) ^ (out5 ^ out7))
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Interrupts are at 0xfe
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0xff stops the register (0xfe is never reached)
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**********************************************************************/
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@ -1,10 +1,10 @@
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/**********************************************************************
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Fairchild F3853 SRAM interface with integrated interrupt
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controller and timer
|
||||
Fairchild F3853 SRAM interface with integrated interrupt
|
||||
controller and timer
|
||||
|
||||
This chip is a timer shift register, basically the same as in the
|
||||
F3851.
|
||||
This chip is a timer shift register, basically the same as in the
|
||||
F3851.
|
||||
|
||||
**********************************************************************/
|
||||
|
||||
|
||||
@ -3,10 +3,10 @@
|
||||
timekpr.h
|
||||
|
||||
Various ST Microelectronics timekeeper SRAM implementations:
|
||||
- M48T02
|
||||
- M48T35
|
||||
- M48T58
|
||||
- MK48T08
|
||||
- M48T02
|
||||
- M48T35
|
||||
- M48T58
|
||||
- MK48T08
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
|
||||
@ -3,10 +3,10 @@
|
||||
timekpr.h
|
||||
|
||||
Various ST Microelectronics timekeeper SRAM implementations:
|
||||
- M48T02
|
||||
- M48T35
|
||||
- M48T58
|
||||
- MK48T08
|
||||
- M48T02
|
||||
- M48T35
|
||||
- M48T58
|
||||
- MK48T08
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
|
||||
@ -5,11 +5,11 @@
|
||||
Copyright (c) 2008, The MESS Team.
|
||||
Visit http://mamedev.org for licensing and usage restrictions.
|
||||
|
||||
The z80dart/z80sio itself is based on an older intel serial chip, the i8274 MPSC
|
||||
(see http://doc.chipfind.ru/pdf/intel/8274.pdf), which also has almost identical
|
||||
behavior, except lacks the interrupt daisy chaining and has its own interrupt/dma
|
||||
scheme which uses write register 2 on channel A, that register which is unused on
|
||||
the z80dart and z80sio.
|
||||
The z80dart/z80sio itself is based on an older intel serial chip, the i8274 MPSC
|
||||
(see http://doc.chipfind.ru/pdf/intel/8274.pdf), which also has almost identical
|
||||
behavior, except lacks the interrupt daisy chaining and has its own interrupt/dma
|
||||
scheme which uses write register 2 on channel A, that register which is unused on
|
||||
the z80dart and z80sio.
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
@ -21,8 +21,8 @@
|
||||
- wr0 reset tx interrupt pending
|
||||
- wait/ready
|
||||
- 1.5 stop bits
|
||||
- synchronous mode (Z80-SIO/1,2)
|
||||
- SDLC mode (Z80-SIO/1,2)
|
||||
- synchronous mode (Z80-SIO/1,2)
|
||||
- SDLC mode (Z80-SIO/1,2)
|
||||
|
||||
*/
|
||||
|
||||
|
||||
@ -3289,7 +3289,7 @@ void address_table::populate_range_mirrored(offs_t bytestart, offs_t byteend, of
|
||||
|
||||
//-------------------------------------------------
|
||||
// depopulate_unused - scan the table and
|
||||
// eliminate entries that are no longer used
|
||||
// eliminate entries that are no longer used
|
||||
//-------------------------------------------------
|
||||
|
||||
void address_table::depopulate_unused()
|
||||
|
||||
@ -281,8 +281,8 @@ private:
|
||||
offs_t m_bytestart; // minimum valid byte address
|
||||
offs_t m_byteend; // maximum valid byte address
|
||||
UINT8 m_entry; // live entry
|
||||
simple_list<direct_range> m_rangelist[256]; // list of ranges for each entry
|
||||
simple_list<direct_range> m_freerangelist; // list of recycled range entries
|
||||
simple_list<direct_range> m_rangelist[256]; // list of ranges for each entry
|
||||
simple_list<direct_range> m_freerangelist; // list of recycled range entries
|
||||
direct_update_delegate m_directupdate; // fast direct-access update callback
|
||||
};
|
||||
|
||||
@ -551,7 +551,7 @@ protected:
|
||||
|
||||
|
||||
// space read/write handler function macros
|
||||
#define READ8_MEMBER(name) UINT8 name(ATTR_UNUSED address_space &space, ATTR_UNUSED offs_t offset, ATTR_UNUSED UINT8 mem_mask)
|
||||
#define READ8_MEMBER(name) UINT8 name(ATTR_UNUSED address_space &space, ATTR_UNUSED offs_t offset, ATTR_UNUSED UINT8 mem_mask)
|
||||
#define WRITE8_MEMBER(name) void name(ATTR_UNUSED address_space &space, ATTR_UNUSED offs_t offset, ATTR_UNUSED UINT8 data, ATTR_UNUSED UINT8 mem_mask)
|
||||
#define READ16_MEMBER(name) UINT16 name(ATTR_UNUSED address_space &space, ATTR_UNUSED offs_t offset, ATTR_UNUSED UINT16 mem_mask)
|
||||
#define WRITE16_MEMBER(name) void name(ATTR_UNUSED address_space &space, ATTR_UNUSED offs_t offset, ATTR_UNUSED UINT16 data, ATTR_UNUSED UINT16 mem_mask)
|
||||
@ -560,7 +560,7 @@ protected:
|
||||
#define READ64_MEMBER(name) UINT64 name(ATTR_UNUSED address_space &space, ATTR_UNUSED offs_t offset, ATTR_UNUSED UINT64 mem_mask)
|
||||
#define WRITE64_MEMBER(name) void name(ATTR_UNUSED address_space &space, ATTR_UNUSED offs_t offset, ATTR_UNUSED UINT64 data, ATTR_UNUSED UINT64 mem_mask)
|
||||
|
||||
#define DECLARE_READ8_MEMBER(name) UINT8 name(ATTR_UNUSED address_space &space, ATTR_UNUSED offs_t offset, ATTR_UNUSED UINT8 mem_mask = 0xff)
|
||||
#define DECLARE_READ8_MEMBER(name) UINT8 name(ATTR_UNUSED address_space &space, ATTR_UNUSED offs_t offset, ATTR_UNUSED UINT8 mem_mask = 0xff)
|
||||
#define DECLARE_WRITE8_MEMBER(name) void name(ATTR_UNUSED address_space &space, ATTR_UNUSED offs_t offset, ATTR_UNUSED UINT8 data, ATTR_UNUSED UINT8 mem_mask = 0xff)
|
||||
#define DECLARE_READ16_MEMBER(name) UINT16 name(ATTR_UNUSED address_space &space, ATTR_UNUSED offs_t offset, ATTR_UNUSED UINT16 mem_mask = 0xffff)
|
||||
#define DECLARE_WRITE16_MEMBER(name) void name(ATTR_UNUSED address_space &space, ATTR_UNUSED offs_t offset, ATTR_UNUSED UINT16 data, ATTR_UNUSED UINT16 mem_mask = 0xffff)
|
||||
|
||||
@ -37,14 +37,14 @@
|
||||
|
||||
****************************************************************************
|
||||
|
||||
Profiling is scope-based. To start profiling, put a profiler_scope
|
||||
object on the stack. To end profiling, just end the scope:
|
||||
Profiling is scope-based. To start profiling, put a profiler_scope
|
||||
object on the stack. To end profiling, just end the scope:
|
||||
|
||||
{
|
||||
profiler_scope scope(PROFILER_VIDEO);
|
||||
{
|
||||
profiler_scope scope(PROFILER_VIDEO);
|
||||
|
||||
your_work_here();
|
||||
}
|
||||
your_work_here();
|
||||
}
|
||||
|
||||
the profiler handles a FILO list so calls may be nested.
|
||||
|
||||
|
||||
@ -37,14 +37,14 @@
|
||||
|
||||
****************************************************************************
|
||||
|
||||
Profiling is scope-based. To start profiling, put a profiler_scope
|
||||
object on the stack. To end profiling, just end the scope:
|
||||
Profiling is scope-based. To start profiling, put a profiler_scope
|
||||
object on the stack. To end profiling, just end the scope:
|
||||
|
||||
{
|
||||
profiler_scope scope(PROFILER_VIDEO);
|
||||
{
|
||||
profiler_scope scope(PROFILER_VIDEO);
|
||||
|
||||
your_work_here();
|
||||
}
|
||||
your_work_here();
|
||||
}
|
||||
|
||||
the profiler handles a FILO list so calls may be nested.
|
||||
|
||||
|
||||
@ -26,7 +26,7 @@ General notes:
|
||||
the microcontroller is able to write to anywhere within main memory.
|
||||
|
||||
Gold Medalist (bootleg) has a 68705 in place of the Alpha controller.
|
||||
(Kyros bootleg also? we have decapped MCU dumps of different types for it)
|
||||
(Kyros bootleg also? we have decapped MCU dumps of different types for it)
|
||||
|
||||
V boards have more memory and double the amount of colours as II boards.
|
||||
|
||||
@ -3230,11 +3230,11 @@ static DRIVER_INIT( sbasebal )
|
||||
UINT16 *rom = (UINT16 *)memory_region(machine, "maincpu");
|
||||
|
||||
/* Patch protection check, it does a divide by zero because the MCU is trying to
|
||||
calculate the ball speed when a strike is scored, notice that current emulation
|
||||
just returns 49 mi/h every time that this event happens.
|
||||
68k reads at [0x4023e], then subtracts this value with [0x41838], presumably it's raw speed minus angle.
|
||||
main CPU then writes the result to RAM location [0x41866], probably just to signal the result to the MCU.
|
||||
*/
|
||||
calculate the ball speed when a strike is scored, notice that current emulation
|
||||
just returns 49 mi/h every time that this event happens.
|
||||
68k reads at [0x4023e], then subtracts this value with [0x41838], presumably it's raw speed minus angle.
|
||||
main CPU then writes the result to RAM location [0x41866], probably just to signal the result to the MCU.
|
||||
*/
|
||||
rom[0xb672/2] = 0x4e71;
|
||||
|
||||
/* And patch the ROM checksums */
|
||||
|
||||
@ -54,10 +54,10 @@
|
||||
Now using mc146818 rtc driver instead of rtc_get_reg.
|
||||
|
||||
19/8/10 - Roberto Fresca.
|
||||
Added 3 Bags Full - 5VXFC790 (Victorian).
|
||||
Set is now parent. Replaced the bad dumped GFX from NZ set with the new ones,
|
||||
since they match 4 of 6 bitplanes. The PROM at U71 is also marked for Fantasy Fortune,
|
||||
so maybe is the correct one for this game.
|
||||
Added 3 Bags Full - 5VXFC790 (Victorian).
|
||||
Set is now parent. Replaced the bad dumped GFX from NZ set with the new ones,
|
||||
since they match 4 of 6 bitplanes. The PROM at U71 is also marked for Fantasy Fortune,
|
||||
so maybe is the correct one for this game.
|
||||
|
||||
The mc146818 driver is buggy - reported problem to Firewave and issues will be addressed.
|
||||
In this driver, the wrong day of the month is shown, wrong hours are shown.
|
||||
|
||||
@ -1,59 +1,59 @@
|
||||
/*
|
||||
|
||||
Aristocrat MK5 / MKV hardware
|
||||
possibly 'Acorn Archimedes on a chip' hardware
|
||||
Aristocrat MK5 / MKV hardware
|
||||
possibly 'Acorn Archimedes on a chip' hardware
|
||||
|
||||
Note: ARM250 mapping is not identical to plain AA
|
||||
Note: ARM250 mapping is not identical to plain AA
|
||||
|
||||
BIOS ROMs are actually nowhere to be found on a regular MK5 system. They can be used to change the system configurations on a PCB board
|
||||
by swapping them with the game ROMs u7/u11 locations.
|
||||
BIOS ROMs are actually nowhere to be found on a regular MK5 system. They can be used to change the system configurations on a PCB board
|
||||
by swapping them with the game ROMs u7/u11 locations.
|
||||
|
||||
TODO (MK-5 specific):
|
||||
- Fix remaining errors
|
||||
- If all tests passes, this msg is printed on the keyboard serial port:
|
||||
"System Startup Code Entered \n Gos_create could not allocate stack for the new process \n Unrecoverable error occured. System will now restart"
|
||||
Apparently it looks like some sort of protection device ...
|
||||
TODO (MK-5 specific):
|
||||
- Fix remaining errors
|
||||
- If all tests passes, this msg is printed on the keyboard serial port:
|
||||
"System Startup Code Entered \n Gos_create could not allocate stack for the new process \n Unrecoverable error occured. System will now restart"
|
||||
Apparently it looks like some sort of protection device ...
|
||||
|
||||
code DASMing of POST (adonis):
|
||||
- bp 0x3400224:
|
||||
checks work RAM [0x87000], if bit 0 active high then all tests are skipped (presumably for debugging), otherwise check stuff;
|
||||
- bp 0x3400230: EPROM checksum branch test
|
||||
- bp 0x3400258: DRAM Check branch test
|
||||
- bp 0x3400280: CPU Check branch test
|
||||
bp 0x340027c: checks IRQ status A and FIQ status bit 7 (force IRQ flag)
|
||||
- R0 == 0: CPU Check OK
|
||||
- R0 == 1: IRQ status A force IRQ flag check failed
|
||||
- R0 == 2: FIQ status force IRQ flag check failed
|
||||
- R0 == 3: Internal Latch check 0x3250050 == 0xf5
|
||||
- bp 0x34002a8: SRAM Check branch test (I2C)
|
||||
- basically writes to the I2C clock/data then read-backs it
|
||||
- bp 0x34002d0: 2KHz Timer branch test
|
||||
bp 0x34002cc: it does various test with GO command reads (that are undefined on plain AA) and
|
||||
IRQA status bit 0, that's "printer busy" on original AA but here it have a completely
|
||||
different meaning.
|
||||
- bp 0x34002f8: DRAM emulator branch tests
|
||||
bp 0x34002f4:
|
||||
- R0 == 0 "DRAM emulator found"
|
||||
- R0 == 1 "DRAM emulator found"
|
||||
- R0 == 3 "DRAM emulator not found - Error"
|
||||
- R0 == 4 "DRAM emulator found instead of DRAM - Error"
|
||||
- R0 == x "Undefined error in DRAM emulator area"
|
||||
It r/w RAM location 0 and it expects to NOT read-back value written.
|
||||
code DASMing of POST (adonis):
|
||||
- bp 0x3400224:
|
||||
checks work RAM [0x87000], if bit 0 active high then all tests are skipped (presumably for debugging), otherwise check stuff;
|
||||
- bp 0x3400230: EPROM checksum branch test
|
||||
- bp 0x3400258: DRAM Check branch test
|
||||
- bp 0x3400280: CPU Check branch test
|
||||
bp 0x340027c: checks IRQ status A and FIQ status bit 7 (force IRQ flag)
|
||||
- R0 == 0: CPU Check OK
|
||||
- R0 == 1: IRQ status A force IRQ flag check failed
|
||||
- R0 == 2: FIQ status force IRQ flag check failed
|
||||
- R0 == 3: Internal Latch check 0x3250050 == 0xf5
|
||||
- bp 0x34002a8: SRAM Check branch test (I2C)
|
||||
- basically writes to the I2C clock/data then read-backs it
|
||||
- bp 0x34002d0: 2KHz Timer branch test
|
||||
bp 0x34002cc: it does various test with GO command reads (that are undefined on plain AA) and
|
||||
IRQA status bit 0, that's "printer busy" on original AA but here it have a completely
|
||||
different meaning.
|
||||
- bp 0x34002f8: DRAM emulator branch tests
|
||||
bp 0x34002f4:
|
||||
- R0 == 0 "DRAM emulator found"
|
||||
- R0 == 1 "DRAM emulator found"
|
||||
- R0 == 3 "DRAM emulator not found - Error"
|
||||
- R0 == 4 "DRAM emulator found instead of DRAM - Error"
|
||||
- R0 == x "Undefined error in DRAM emulator area"
|
||||
It r/w RAM location 0 and it expects to NOT read-back value written.
|
||||
|
||||
goldprmd: checks if a "keyboard IRQ" fires (IRQ status B bit 6), it seems a serial port with data on it,
|
||||
returns an External Video Crystal Error (bp 3400278)
|
||||
goldprmd: checks if a "keyboard IRQ" fires (IRQ status B bit 6), it seems a serial port with data on it,
|
||||
returns an External Video Crystal Error (bp 3400278)
|
||||
|
||||
dmdtouch:
|
||||
bp 3400640: checks 2MByte DRAM
|
||||
- writes from 0x1000 to 0x100000, with 0x400 bytes index increment and 0xfb data increment
|
||||
- writes from 0x100000 to 0x200000, with 0x400 bytes index increment and 0xfb data increment
|
||||
- bp 3400720 checks if the aforementioned checks are ok (currently fails at the very first work RAM check at 0x1000, it returns the
|
||||
value that actually should be at 0x141000)
|
||||
bp 340064c: if R0 == 0 2MB DRAM is ok, otherwise there's an error
|
||||
dmdtouch:
|
||||
bp 3400640: checks 2MByte DRAM
|
||||
- writes from 0x1000 to 0x100000, with 0x400 bytes index increment and 0xfb data increment
|
||||
- writes from 0x100000 to 0x200000, with 0x400 bytes index increment and 0xfb data increment
|
||||
- bp 3400720 checks if the aforementioned checks are ok (currently fails at the very first work RAM check at 0x1000, it returns the
|
||||
value that actually should be at 0x141000)
|
||||
bp 340064c: if R0 == 0 2MB DRAM is ok, otherwise there's an error
|
||||
|
||||
set chip (BIOS):
|
||||
same as goldprmd (serial + ext video crystal check)
|
||||
bp 3400110: External Video Crystal test
|
||||
set chip (BIOS):
|
||||
same as goldprmd (serial + ext video crystal check)
|
||||
bp 3400110: External Video Crystal test
|
||||
|
||||
*/
|
||||
|
||||
@ -131,7 +131,7 @@ static ADDRESS_MAP_START( aristmk5_map, ADDRESS_SPACE_PROGRAM, 32 )
|
||||
/* MK-5 overrides */
|
||||
AM_RANGE(0x03010420, 0x03010423) AM_RAM_WRITE(mk5_i2c_w)
|
||||
AM_RANGE(0x03010810, 0x03010813) AM_READNOP //MK-5 specific, watchdog
|
||||
// System Startup Code Enabled protection appears to be located at 0x3010400 - 0x30104ff
|
||||
// System Startup Code Enabled protection appears to be located at 0x3010400 - 0x30104ff
|
||||
AM_RANGE(0x03220000, 0x03220003) AM_READWRITE(mk5_econet_r,mk5_econet_w)
|
||||
AM_RANGE(0x03250048, 0x0325004b) AM_WRITE(mk5_ext_latch_w)
|
||||
AM_RANGE(0x03250050, 0x03250053) AM_READ(mk5_unk_r)
|
||||
@ -150,7 +150,7 @@ static INPUT_PORTS_START( aristmk5 )
|
||||
PORT_CONFNAME( 0x03, 0x00, "System Mode" )
|
||||
PORT_CONFSETTING( 0x00, "Set Chip v4.04 Mode" )
|
||||
PORT_CONFSETTING( 0x01, "Set Chip v4.4 Mode" )
|
||||
// Clear Chip (missing?)
|
||||
// Clear Chip (missing?)
|
||||
PORT_CONFSETTING( 0x03, "Game Mode" )
|
||||
INPUT_PORTS_END
|
||||
|
||||
|
||||
@ -450,8 +450,8 @@
|
||||
- Promoted comg080 (Arcade Black Jack) to working state.
|
||||
|
||||
- Added support for system 906III:
|
||||
- Accurate memory map, CRTC, and PIAs mapped.
|
||||
- Preliminary PIAs support (no multiplexion yet).
|
||||
- Accurate memory map, CRTC, and PIAs mapped.
|
||||
- Preliminary PIAs support (no multiplexion yet).
|
||||
- Added proper machine driver, with correct R65C02 CPU.
|
||||
- Documented the hardware specs.
|
||||
- Added Game 51.08 (CEI Video Poker, Jacks or Better),
|
||||
@ -460,7 +460,7 @@
|
||||
- Mapped the AY8912.
|
||||
- Added AY8912 proper interfase. Tied SW2 to AY8912 port.
|
||||
- PIA0, portA is polled constantly. Tied some debug handlers
|
||||
to understand how the input system works.
|
||||
to understand how the input system works.
|
||||
- Added notes about the PIAs R/W.
|
||||
|
||||
|
||||
@ -3973,9 +3973,9 @@ static DRIVER_INIT( comg080 )
|
||||
}
|
||||
|
||||
/* Injecting missing Start and NMI vectors...
|
||||
Start = $2042; NMI = $26f8;
|
||||
Also a fake vector at $3ff8-$3ff9. The code checks these values to continue.
|
||||
*/
|
||||
Start = $2042; NMI = $26f8;
|
||||
Also a fake vector at $3ff8-$3ff9. The code checks these values to continue.
|
||||
*/
|
||||
UINT8 *PRGROM = memory_region( machine, "maincpu" );
|
||||
|
||||
PRGROM[0x3ff8] = 0x8e; /* checked by code */
|
||||
|
||||
@ -42,18 +42,18 @@ Thanks to Alex, Mr Mudkips, and Philip Burke for this info.
|
||||
#include "debug/debugcmd.h"
|
||||
|
||||
/* jamtable instructions for Chihiro
|
||||
St. Instr. Comment
|
||||
0x01 POKEPCI PCICONF[OP2] := OP1
|
||||
0x02 OUTB PORT[OP2] := OP1
|
||||
0x03 POKE MEM[OP2] := OP1
|
||||
0x04 BNE IF ACC <> OP2 THEN PC := PC + OP1
|
||||
0x05 PEEKPCI ACC := PCICONF[OP2]
|
||||
0x06 AND/OR ACC := (ACC & OP2) | OP1
|
||||
0x07 BRA PC := PC + OP1
|
||||
0x08 INB ACC := PORT[OP2]
|
||||
0x09 PEEK ACC := MEM[OP2]
|
||||
0xE1 (prefix) execute the instruction code in OP2 with OP2 := OP1, OP1 := ACC
|
||||
0xEE END
|
||||
St. Instr. Comment
|
||||
0x01 POKEPCI PCICONF[OP2] := OP1
|
||||
0x02 OUTB PORT[OP2] := OP1
|
||||
0x03 POKE MEM[OP2] := OP1
|
||||
0x04 BNE IF ACC <> OP2 THEN PC := PC + OP1
|
||||
0x05 PEEKPCI ACC := PCICONF[OP2]
|
||||
0x06 AND/OR ACC := (ACC & OP2) | OP1
|
||||
0x07 BRA PC := PC + OP1
|
||||
0x08 INB ACC := PORT[OP2]
|
||||
0x09 PEEK ACC := MEM[OP2]
|
||||
0xE1 (prefix) execute the instruction code in OP2 with OP2 := OP1, OP1 := ACC
|
||||
0xEE END
|
||||
*/
|
||||
|
||||
/* jamtable disassembler */
|
||||
|
||||
@ -4403,7 +4403,7 @@ ROM_START( ffightu )
|
||||
ROM_LOAD16_BYTE( "ff_36.11f", 0x00000, 0x20000, CRC(f9a5ce83) SHA1(0756ae576a1f6d5b8b22f8630dca40ef38567ea6) ) // in "30" socket
|
||||
ROM_LOAD16_BYTE( "ff_42.11h", 0x00001, 0x20000, CRC(65f11215) SHA1(5045a467f3e228c02b4a355b52f58263ffa90113) ) // in "35" socket
|
||||
ROM_LOAD16_BYTE( "ff_37.12f", 0x40000, 0x20000, CRC(e1033784) SHA1(38f44434c8befd623953ae23d6e5ff4e201d6627) ) // in "31" socket
|
||||
ROM_LOAD16_BYTE( "ff_43.12h", 0x40001, 0x20000, CRC(4ca65947) SHA1(74ffe00df96273770a24d9a46f13e53ea8812670) ) // in "36" socket /* seen the same pcb with FFU_43.12H */
|
||||
ROM_LOAD16_BYTE( "ff_43.12h", 0x40001, 0x20000, CRC(4ca65947) SHA1(74ffe00df96273770a24d9a46f13e53ea8812670) ) // in "36" socket /* seen the same pcb with FFU_43.12H */
|
||||
ROM_LOAD16_WORD_SWAP( "ff-32m.8h", 0x80000, 0x80000, CRC(c747696e) SHA1(d3362dadded31ccb7eaf71ef282d698d18edd722) )
|
||||
|
||||
ROM_REGION( 0x200000, "gfx", 0 )
|
||||
@ -4483,7 +4483,7 @@ ROM_START( ffightub )
|
||||
ROMX_LOAD( "ff-3m.5a", 0x000006, 0x80000, CRC(52291cd2) SHA1(df5f3d3aa96a7a33ff22f2a31382942c4c4f1111) , ROM_GROUPWORD | ROM_SKIP(6) )
|
||||
|
||||
ROM_REGION( 0x18000, "audiocpu", 0 ) /* 64k for the audio CPU (+banks) */
|
||||
ROM_LOAD( "ff_23.12b", 0x00000, 0x08000, CRC(b8367eb5) SHA1(ec3db29fdd6200e9a8f4f8073a7e34aef731354f) ) // == ff_09.12b /* label is FF_23, pcb verified */
|
||||
ROM_LOAD( "ff_23.12b", 0x00000, 0x08000, CRC(b8367eb5) SHA1(ec3db29fdd6200e9a8f4f8073a7e34aef731354f) ) // == ff_09.12b /* label is FF_23, pcb verified */
|
||||
ROM_CONTINUE( 0x10000, 0x08000 )
|
||||
|
||||
ROM_REGION( 0x40000, "oki", 0 ) /* Samples */
|
||||
@ -9965,7 +9965,7 @@ GAME( 1992, sf2yyc, sf2ce, cps1_12MHz, sf2hack, sf2hack, ROT0, "bo
|
||||
GAME( 1992, sf2koryu, sf2ce, cps1_12MHz, sf2hack, sf2hack, ROT0, "bootleg", "Street Fighter II': Champion Edition (Xiang Long, Chinese bootleg)", GAME_SUPPORTS_SAVE ) // 811102 !!! - based on World version
|
||||
GAME( 1992, sf2mdt, sf2ce, sf2mdt, sf2hack, sf2mdt, ROT0, "bootleg", "Street Fighter II': Magic Delta Turbo (bootleg)", GAME_NOT_WORKING | GAME_NO_SOUND | GAME_SUPPORTS_SAVE ) // 920313 - based on (heavily modified) World version
|
||||
GAME( 1992, cworld2j, 0, cps1_12MHz, cworld2j, cps1, ROT0, "Capcom", "Adventure Quiz Capcom World 2 (Japan 920611)", GAME_SUPPORTS_SAVE )
|
||||
GAME( 1992, varth, 0, cps1_12MHz, varth, cps1, ROT270, "Capcom", "Varth: Operation Thunderstorm (World 920714)", GAME_SUPPORTS_SAVE ) // "ETC" // 12MHz verified
|
||||
GAME( 1992, varth, 0, cps1_12MHz, varth, cps1, ROT270, "Capcom", "Varth: Operation Thunderstorm (World 920714)", GAME_SUPPORTS_SAVE ) // "ETC" // 12MHz verified
|
||||
GAME( 1992, varthr1, varth, cps1_12MHz, varth, cps1, ROT270, "Capcom", "Varth: Operation Thunderstorm (World 920612)", GAME_SUPPORTS_SAVE ) // "ETC"
|
||||
GAME( 1992, varthu, varth, cps1_12MHz, varth, cps1, ROT270, "Capcom, distributed by Romstar", "Varth: Operation Thunderstorm (USA 920612)", GAME_SUPPORTS_SAVE )
|
||||
GAME( 1992, varthj, varth, cps1_12MHz, varth, cps1, ROT270, "Capcom", "Varth: Operation Thunderstorm (Japan 920714)", GAME_SUPPORTS_SAVE )
|
||||
|
||||
@ -266,8 +266,8 @@ static INPUT_PORTS_START( bestri )
|
||||
PORT_DIPNAME( 0x00c0, 0x00c0, "Girls" ) PORT_DIPLOCATION("SW1:7,8") /* stored at 0x3a6faa.w */
|
||||
PORT_DIPSETTING( 0x00c0, DEF_STR( No ) )
|
||||
PORT_DIPSETTING( 0x0080, DEF_STR( Yes ) )
|
||||
// PORT_DIPSETTING( 0x0040, DEF_STR( No ) )
|
||||
// PORT_DIPSETTING( 0x0000, DEF_STR( No ) )
|
||||
// PORT_DIPSETTING( 0x0040, DEF_STR( No ) )
|
||||
// PORT_DIPSETTING( 0x0000, DEF_STR( No ) )
|
||||
PORT_DIPNAME( 0x0700, 0x0700, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW2:1,2,3") /* stored at 0x3a6fa6.w but not read back ? */
|
||||
PORT_DIPSETTING( 0x0700, "0" )
|
||||
PORT_DIPSETTING( 0x0300, "1" )
|
||||
|
||||
@ -297,15 +297,15 @@ Donkey Kong Junior Notes
|
||||
------------------------------------------------
|
||||
|
||||
|
||||
D2K Jumpman returns Notes
|
||||
=========================
|
||||
D2K Jumpman returns Notes
|
||||
=========================
|
||||
|
||||
This is a DKong/Hack combo using a Braze Technologies High Score Save pcb.
|
||||
This pcb will be placed in the cpu socket and the Z80 together with an
|
||||
additional 64K rom, a 74LS245, an eeprom and a pal/gal. It looks like the
|
||||
"encryption" was a conincidence resulting from an easy pcb layout.
|
||||
The pal is also used to switch A15 on and off. This is done in locations
|
||||
6800 and E800.
|
||||
This is a DKong/Hack combo using a Braze Technologies High Score Save pcb.
|
||||
This pcb will be placed in the cpu socket and the Z80 together with an
|
||||
additional 64K rom, a 74LS245, an eeprom and a pal/gal. It looks like the
|
||||
"encryption" was a conincidence resulting from an easy pcb layout.
|
||||
The pal is also used to switch A15 on and off. This is done in locations
|
||||
6800 and E800.
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
|
||||
@ -359,7 +359,7 @@ static READ8_HANDLER( dip_switch_r )
|
||||
{
|
||||
case 0x01:
|
||||
/* For the DIP switches to be read, protection_data must be
|
||||
0xff on reset. The AY8910 reset ensures this. */
|
||||
0xff on reset. The AY8910 reset ensures this. */
|
||||
if (state->protection_data != 0xff)
|
||||
ret = state->protection_data ^ 0x88;
|
||||
else
|
||||
|
||||
@ -1,22 +1,22 @@
|
||||
/*******************************************************************************************
|
||||
|
||||
Erotictac/Tactic (c) 1990 Sisteme
|
||||
Poizone (c) 1991 Eterna
|
||||
Erotictac/Tactic (c) 1990 Sisteme
|
||||
Poizone (c) 1991 Eterna
|
||||
|
||||
Actually an Acorn Archimedes-based Arcade system
|
||||
Actually an Acorn Archimedes-based Arcade system
|
||||
|
||||
original driver by Tomasz Slanina, Steve Ellenoff, Nicola Salmoria
|
||||
rewrite to use AA functions by R.Belmont & Angelo Salese
|
||||
special thanks to Tom Walker (author of the Acorn Archimedes Arculator emulator)
|
||||
original driver by Tomasz Slanina, Steve Ellenoff, Nicola Salmoria
|
||||
rewrite to use AA functions by R.Belmont & Angelo Salese
|
||||
special thanks to Tom Walker (author of the Acorn Archimedes Arculator emulator)
|
||||
|
||||
TODO (specific issues only):
|
||||
- Sound is currently ugly in both games, recognizable but still nowhere near perfection
|
||||
- ertictac: 'music' dip-sw makes the game to just hang, BGM doesn't play either for
|
||||
whatever reason (should be triggered as soon as it executes the POST)
|
||||
- poizone: ARM core bugs causes it to crash at some point.
|
||||
- Does this Arcade conversion have I2C device? It seems unused afaik.
|
||||
- Need PCB for identify the exact model of AA, available RAM, what kind of i/o "podule"
|
||||
it has etc.
|
||||
TODO (specific issues only):
|
||||
- Sound is currently ugly in both games, recognizable but still nowhere near perfection
|
||||
- ertictac: 'music' dip-sw makes the game to just hang, BGM doesn't play either for
|
||||
whatever reason (should be triggered as soon as it executes the POST)
|
||||
- poizone: ARM core bugs causes it to crash at some point.
|
||||
- Does this Arcade conversion have I2C device? It seems unused afaik.
|
||||
- Need PCB for identify the exact model of AA, available RAM, what kind of i/o "podule"
|
||||
it has etc.
|
||||
|
||||
*******************************************************************************************/
|
||||
#include "emu.h"
|
||||
|
||||
@ -4783,13 +4783,13 @@ ROM_START( starseek )
|
||||
ROM_REGION( 0x50, "picreturn", ROMREGION_ERASE)
|
||||
|
||||
/*
|
||||
Note:
|
||||
There was no sticker or silk screen markings on this PIC.
|
||||
I have used the product number as a label instead.
|
||||
Note:
|
||||
There was no sticker or silk screen markings on this PIC.
|
||||
I have used the product number as a label instead.
|
||||
|
||||
PIC16C621A-20 (317-0005-JPN)
|
||||
Sticker: 253-5509-0005J
|
||||
*/
|
||||
PIC16C621A-20 (317-0005-JPN)
|
||||
Sticker: 253-5509-0005J
|
||||
*/
|
||||
ROM_REGION( 0x4000, "pic", ROMREGION_ERASEFF)
|
||||
ROM_LOAD("317-0005-jpn.pic", 0x00, 0x4000, CRC(19f8d4d0) SHA1(d256f26f757d7019cab7950d81992902cdb65e07) )
|
||||
ROM_END
|
||||
|
||||
@ -5502,8 +5502,8 @@ ROM_END
|
||||
|
||||
ROM_START( mslug4 ) /* Original Version - Encrypted GFX */ /* MVS VERSION */
|
||||
/* There also exist carts where p1 label is pg1; the PG1 revision has a Japanese cart label, SN 02Jxxxxx
|
||||
The P1 revision has a US/EUR cart label, SN 02Txxxxx ; Rom data on both is identical.
|
||||
These carts were manufactured by Mega Enterprise, not SNK. */
|
||||
The P1 revision has a US/EUR cart label, SN 02Txxxxx ; Rom data on both is identical.
|
||||
These carts were manufactured by Mega Enterprise, not SNK. */
|
||||
ROM_REGION( 0x500000, "maincpu", 0 )
|
||||
ROM_LOAD16_WORD_SWAP( "263-p1.bin", 0x000000, 0x100000, CRC(27e4def3) SHA1(a08785e8145981bb6b5332a3b2df7eb321253cca) )
|
||||
ROM_LOAD16_WORD_SWAP( "263-p2.bin", 0x100000, 0x400000, CRC(fdb7aed8) SHA1(dbeaec38f44e58ffedba99e70fa1439c2bf0dfa3) )
|
||||
|
||||
@ -6,11 +6,11 @@
|
||||
Skeleton by R. Belmont
|
||||
|
||||
H/W is a white-box PC consisting of:
|
||||
Pentium II 450 CPU
|
||||
DFI P2XBL motherboard (i440BX chipset)
|
||||
128 MB RAM
|
||||
Guillemot Maxi Gamer 3D2 Voodoo II
|
||||
Sound Blaster AWE64
|
||||
Pentium II 450 CPU
|
||||
DFI P2XBL motherboard (i440BX chipset)
|
||||
128 MB RAM
|
||||
Guillemot Maxi Gamer 3D2 Voodoo II
|
||||
Sound Blaster AWE64
|
||||
|
||||
Protected by a HASP brand parallel port dongle.
|
||||
I/O board has a PIC17C43 which is not readable.
|
||||
|
||||
@ -300,7 +300,7 @@ static ADDRESS_MAP_START( yieartf_map, ADDRESS_SPACE_PROGRAM, 8 )
|
||||
AM_RANGE(0x1085, 0x1085) AM_MIRROR(0x0078) AM_WRITENOP /* CN3.2 */
|
||||
AM_RANGE(0x1086, 0x1086) AM_MIRROR(0x0078) AM_WRITENOP /* CN3.4 */
|
||||
AM_RANGE(0x1087, 0x1087) AM_MIRROR(0x0078) AM_WRITE(interrupt_enable_w) /* INT */
|
||||
// AM_RANGE(0x1100, 0x1100) AM_MIRROR(0x007f) AM_WRITE(soundlatch_w) /* 32 */
|
||||
// AM_RANGE(0x1100, 0x1100) AM_MIRROR(0x007f) AM_WRITE(soundlatch_w) /* 32 */
|
||||
AM_RANGE(0x1200, 0x1200) AM_MIRROR(0x007f) AM_READ_PORT("DSW2")
|
||||
AM_RANGE(0x1280, 0x1280) AM_MIRROR(0x007c) AM_READ_PORT("SYSTEM")
|
||||
AM_RANGE(0x1281, 0x1281) AM_MIRROR(0x007c) AM_READ_PORT("IN0")
|
||||
@ -1050,8 +1050,8 @@ static MACHINE_DRIVER_START( yieartf )
|
||||
MDRV_CPU_VBLANK_INT("screen", irq0_line_hold)
|
||||
|
||||
// z80 isn't used
|
||||
// MDRV_CPU_ADD("audiocpu", Z80, SOUND_CLOCK/4)
|
||||
// MDRV_CPU_PROGRAM_MAP(sound_map)
|
||||
// MDRV_CPU_ADD("audiocpu", Z80, SOUND_CLOCK/4)
|
||||
// MDRV_CPU_PROGRAM_MAP(sound_map)
|
||||
|
||||
MDRV_MACHINE_START(trackfld)
|
||||
MDRV_MACHINE_RESET(trackfld)
|
||||
|
||||
@ -71,9 +71,9 @@ extern UINT8 vidc_interlace;
|
||||
#define CONTROL 0x00/4
|
||||
#define KART 0x04/4 // Keyboard Asynchronous Receiver Transmitter
|
||||
|
||||
#define IRQ_STATUS_A 0x10/4
|
||||
#define IRQ_STATUS_A 0x10/4
|
||||
#define IRQ_REQUEST_A 0x14/4
|
||||
#define IRQ_MASK_A 0x18/4
|
||||
#define IRQ_MASK_A 0x18/4
|
||||
#define IRQ_STATUS_B 0x20/4
|
||||
#define IRQ_REQUEST_B 0x24/4
|
||||
#define IRQ_MASK_B 0x28/4
|
||||
|
||||
@ -267,7 +267,7 @@ READ32_HANDLER(archimedes_memc_logical_r)
|
||||
page = (offset<<2) / page_sizes[memc_pagesize];
|
||||
poffs = (offset<<2) % page_sizes[memc_pagesize];
|
||||
|
||||
// printf("Reading offset %x (addr %x): page %x (size %d %d) offset %x ==> %x %x\n", offset, offset<<2, page, memc_pagesize, page_sizes[memc_pagesize], poffs, memc_pages[page], memc_pages[page]*page_sizes[memc_pagesize]);
|
||||
// printf("Reading offset %x (addr %x): page %x (size %d %d) offset %x ==> %x %x\n", offset, offset<<2, page, memc_pagesize, page_sizes[memc_pagesize], poffs, memc_pages[page], memc_pages[page]*page_sizes[memc_pagesize]);
|
||||
|
||||
if (memc_pages[page] != -1)
|
||||
{
|
||||
@ -339,8 +339,8 @@ DIRECT_UPDATE_HANDLER( a310_setopbase )
|
||||
|
||||
void archimedes_driver_init(running_machine *machine)
|
||||
{
|
||||
// address_space *space = machine->device<arm_device>("maincpu")->space(AS_PROGRAM);
|
||||
// space->set_direct_update_handler(direct_update_delegate_create_static(a310_setopbase, *machine));
|
||||
// address_space *space = machine->device<arm_device>("maincpu")->space(AS_PROGRAM);
|
||||
// space->set_direct_update_handler(direct_update_delegate_create_static(a310_setopbase, *machine));
|
||||
}
|
||||
|
||||
static const char *const ioc_regnames[] =
|
||||
@ -711,15 +711,15 @@ static void vidc_dynamic_res_change(running_machine *machine)
|
||||
{
|
||||
/* sanity checks - first pass */
|
||||
/*
|
||||
total cycles + border end
|
||||
*/
|
||||
total cycles + border end
|
||||
*/
|
||||
if(vidc_regs[VIDC_HCR] && vidc_regs[VIDC_HBER] &&
|
||||
vidc_regs[VIDC_VCR] && vidc_regs[VIDC_VBER])
|
||||
{
|
||||
/* sanity checks - second pass */
|
||||
/*
|
||||
total cycles >= border end >= border start
|
||||
*/
|
||||
total cycles >= border end >= border start
|
||||
*/
|
||||
if((vidc_regs[VIDC_HCR] >= vidc_regs[VIDC_HBER]) &&
|
||||
(vidc_regs[VIDC_HBER] >= vidc_regs[VIDC_HBSR]) &&
|
||||
(vidc_regs[VIDC_VCR] >= vidc_regs[VIDC_VBER]) &&
|
||||
@ -810,30 +810,30 @@ WRITE32_HANDLER(archimedes_vidc_w)
|
||||
{
|
||||
vidc_stereo_reg[(reg >> 2) & 7] = val & 0x07;
|
||||
|
||||
// popmessage("%02x %02x %02x %02x %02x %02x %02x %02x",vidc_stereo_reg[0],vidc_stereo_reg[1],vidc_stereo_reg[2],vidc_stereo_reg[3]
|
||||
// ,vidc_stereo_reg[4],vidc_stereo_reg[5],vidc_stereo_reg[6],vidc_stereo_reg[7]);
|
||||
// popmessage("%02x %02x %02x %02x %02x %02x %02x %02x",vidc_stereo_reg[0],vidc_stereo_reg[1],vidc_stereo_reg[2],vidc_stereo_reg[3]
|
||||
// ,vidc_stereo_reg[4],vidc_stereo_reg[5],vidc_stereo_reg[6],vidc_stereo_reg[7]);
|
||||
}
|
||||
else if (reg >= 0x80 && reg <= 0xbc)
|
||||
{
|
||||
switch(reg)
|
||||
{
|
||||
case VIDC_HCR: vidc_regs[VIDC_HCR] = ((val >> 14)<<1)+1; break;
|
||||
// case VIDC_HSWR: vidc_regs[VIDC_HSWR] = (val >> 14)+1; break;
|
||||
case VIDC_HBSR: vidc_regs[VIDC_HBSR] = ((val >> 14)<<1)+1; break;
|
||||
case VIDC_HCR: vidc_regs[VIDC_HCR] = ((val >> 14)<<1)+1; break;
|
||||
// case VIDC_HSWR: vidc_regs[VIDC_HSWR] = (val >> 14)+1; break;
|
||||
case VIDC_HBSR: vidc_regs[VIDC_HBSR] = ((val >> 14)<<1)+1; break;
|
||||
case VIDC_HDSR: vidc_regs[VIDC_HDSR] = (val >> 14); break;
|
||||
case VIDC_HDER: vidc_regs[VIDC_HDER] = (val >> 14); break;
|
||||
case VIDC_HBER: vidc_regs[VIDC_HBER] = ((val >> 14)<<1)+1; break;
|
||||
// #define VIDC_HCSR 0x98
|
||||
// #define VIDC_HIR 0x9c
|
||||
case VIDC_HBER: vidc_regs[VIDC_HBER] = ((val >> 14)<<1)+1; break;
|
||||
// #define VIDC_HCSR 0x98
|
||||
// #define VIDC_HIR 0x9c
|
||||
|
||||
case VIDC_VCR: vidc_regs[VIDC_VCR] = ((val >> 14)<<1)+1; break;
|
||||
// #define VIDC_VSWR 0xa4
|
||||
case VIDC_VBSR: vidc_regs[VIDC_VBSR] = (val >> 14)+1; break;
|
||||
// #define VIDC_VSWR 0xa4
|
||||
case VIDC_VBSR: vidc_regs[VIDC_VBSR] = (val >> 14)+1; break;
|
||||
case VIDC_VDSR: vidc_regs[VIDC_VDSR] = (val >> 14)+1; break;
|
||||
case VIDC_VDER: vidc_regs[VIDC_VDER] = (val >> 14)+1; break;
|
||||
case VIDC_VBER: vidc_regs[VIDC_VBER] = (val >> 14)+1; break;
|
||||
// #define VIDC_VCSR 0xb8
|
||||
// #define VIDC_VCER 0xbc
|
||||
// #define VIDC_VCSR 0xb8
|
||||
// #define VIDC_VCER 0xbc
|
||||
}
|
||||
|
||||
|
||||
@ -1000,7 +1000,7 @@ WRITE32_HANDLER(archimedes_memc_page_w)
|
||||
break;
|
||||
}
|
||||
|
||||
// log >>= (12 + memc_pagesize);
|
||||
// log >>= (12 + memc_pagesize);
|
||||
|
||||
// always make sure ROM mode is disconnected when this occurs
|
||||
memc_latchrom = 0;
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/***************************************************************************
|
||||
|
||||
Acorn Archimedes VIDC (VIDeo Controller) emulation
|
||||
Acorn Archimedes VIDC (VIDeo Controller) emulation
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
|
||||
@ -76,7 +76,7 @@ static const pen_t default_colortable[] =
|
||||
typedef struct _ppu2c0x_state ppu2c0x_state;
|
||||
struct _ppu2c0x_state
|
||||
{
|
||||
address_space *space; /* memory space */
|
||||
address_space *space; /* memory space */
|
||||
bitmap_t *bitmap; /* target bitmap */
|
||||
UINT8 *spriteram; /* sprite ram */
|
||||
pen_t *colortable; /* color table modified at run time */
|
||||
|
||||
@ -99,7 +99,7 @@ VIDEO_START( toaplan2 )
|
||||
|
||||
if (state->vdp1 != NULL)
|
||||
{
|
||||
state->secondary_render_bitmap = auto_bitmap_alloc(machine, width, height, BITMAP_FORMAT_INDEXED16);
|
||||
state->secondary_render_bitmap = auto_bitmap_alloc(machine, width, height, BITMAP_FORMAT_INDEXED16);
|
||||
state->vdp1->custom_priority_bitmap = state->custom_priority_bitmap;
|
||||
state->vdp1->displog = &state->displog;
|
||||
}
|
||||
@ -345,7 +345,7 @@ VIDEO_UPDATE( toaplan2_dual )
|
||||
{
|
||||
gp9001_log_vram(state->vdp0, screen->machine);
|
||||
|
||||
// bitmap_fill(bitmap,cliprect,0);
|
||||
// bitmap_fill(bitmap,cliprect,0);
|
||||
bitmap_fill(state->custom_priority_bitmap, cliprect, 0);
|
||||
state->vdp0->gp9001_render_vdp(screen->machine, bitmap, cliprect);
|
||||
}
|
||||
@ -360,8 +360,8 @@ VIDEO_UPDATE( toaplan2_mixed )
|
||||
{
|
||||
toaplan2_state *state = screen->machine->driver_data<toaplan2_state>();
|
||||
|
||||
// bitmap_fill(bitmap,cliprect,0);
|
||||
// bitmap_fill(gp9001_custom_priority_bitmap, cliprect, 0);
|
||||
// bitmap_fill(bitmap,cliprect,0);
|
||||
// bitmap_fill(gp9001_custom_priority_bitmap, cliprect, 0);
|
||||
|
||||
if (state->vdp0)
|
||||
{
|
||||
|
||||
@ -225,7 +225,7 @@ static void draw_sprites( running_machine *machine, bitmap_t *bitmap, const rect
|
||||
//
|
||||
//if (offs < 0x26)
|
||||
//{
|
||||
// sy++; /* fix title screen & garbage at the bottom of the screen */
|
||||
// sy++; /* fix title screen & garbage at the bottom of the screen */
|
||||
//}
|
||||
|
||||
|
||||
|
||||
@ -10,4 +10,4 @@
|
||||
***************************************************************************/
|
||||
|
||||
extern const char build_version[];
|
||||
const char build_version[] = "0.139u1 ("__DATE__")";
|
||||
const char build_version[] = "0.139u2 ("__DATE__")";
|
||||
|
||||
Loading…
Reference in New Issue
Block a user