Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-06-10 06:47:18 +03:00
Code Issues Actions Packages Projects Releases Wiki Activity

(MESS) improvements to mbee256. Thanks to RedSkullDC for dumping the bankswitching prom, and ubee512-author for advice.

Browse Source
This commit is contained in:
Robbbert 2015-02-04 19:20:14 +11:00
parent aa0ffdc153
commit 0f602ba86a
3 changed files with 232 additions and 236 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

140
src/mess/drivers/mbee.c
View File

@ -22,11 +22,13 @@
The unemulated Matilda is a IBM XT clone fitted with a NEC V40, and has the The unemulated Matilda is a IBM XT clone fitted with a NEC V40, and has the
ability to emulate the 256TC as mentioned above. ability to emulate the 256TC as mentioned above.
Floppy Disk types (as used by ubee512) Floppy formats:
- ss80 - single sided 80 track - All disks are the standard CPCEMU 'dsk' format.
- ds40 - double-sided 40 track - 400KB - Types are 9cm 80 track, and 13cm 40 track (single or double sided)
- ds80, ds82, ds84 - double sided 80 track - 800KB - 13cm has been specified as QD to prevent a nasty crash if an 80-track disk was mounted
- dsk - various - 211KB, 421KB, 841KB - The tracks/sector layout is the same regardless of size
- Although certain models came with particular drives as standard, users could add
the other size if they wished. We support both sizes on any model.
Microbee Standard / Plus memory map Microbee Standard / Plus memory map
@ -82,18 +84,24 @@
- Fix Paste (it loses most of the characters) - Fix Paste (it loses most of the characters)
- RTC for 256TC works, but it is supposed to be an option on other - all except 256tc: RTC is optional, but it is being totally ignored.
models. It is being completely ignored.
- Most early models have a clock in Telcom, and in the menu. It doesn't - Most early models have a clock in Telcom, and in the menu. It doesn't
work. work.
- The Monitor program on 256TC crashes the system. This appears - various fdc issues:
to be a MAME core bug involving the z80pio. - only some ds40 disks can be used. All 80-track disks fail.
- some disks show no or partial directory listing.
- some disks cause MESS to freeze.
- ENMF pin missing from wd_fdc.
- incorrect timing for track register causes 256tc failure to boot a disk.
- 56k model takes about 2 minutes to boot a disk if loaded via command line.
- The 256TC corrupts itself when a floppy disk is detected. - 256tc: At the menu, if F2 pressed to activate the Monitor, the emulated machine
crashes due to a bug in z80pio emulation.
- Disk system doesn't work because of fdc problems. - 256tc: Keyboard ROM U60 needs to be dumped.
- 128k: PROM PAL needs to be dumped, so that the bankswitching can be fixed.
- Teleterm: keyboard is problematic, and cursor doesn't show. - Teleterm: keyboard is problematic, and cursor doesn't show.
@ -113,24 +121,10 @@
in the emulator for some years. Conversion to the new modern in the emulator for some years. Conversion to the new modern
implementation (2013-07-05) has not resolved the issue. implementation (2013-07-05) has not resolved the issue.
There are 3 types of microbee disks available in the wild.
- CPCEMU-format "dsk" disks, which has an already-working
format "dsk_dsk".
- ubee512-format disks, such as "ds80,ds82,ds84,ss80", etc.
These are described in "mbee_dsk", but it's not known if it
works as yet.
- There a "img" format for the 128k boot disk. The internal
layout is not known and no work has been done.
****************************************************************************/ ****************************************************************************/
#include "includes/mbee.h" #include "includes/mbee.h"
#include "formats/mbee_dsk.h"
#include "formats/mbee_cas.h" #include "formats/mbee_cas.h"
@ -219,6 +213,25 @@ static ADDRESS_MAP_START(mbee128_mem, AS_PROGRAM, 8, mbee_state)
AM_RANGE(0xf800, 0xffff) AM_RAMBANK("bankfh") AM_RANGE(0xf800, 0xffff) AM_RAMBANK("bankfh")
ADDRESS_MAP_END ADDRESS_MAP_END
static ADDRESS_MAP_START(mbee256_mem, AS_PROGRAM, 8, mbee_state)
AM_RANGE(0x0000, 0x0fff) AM_READ_BANK("bankr0") AM_WRITE_BANK("bankw0")
AM_RANGE(0x1000, 0x1fff) AM_READ_BANK("bankr1") AM_WRITE_BANK("bankw1")
AM_RANGE(0x2000, 0x2fff) AM_READ_BANK("bankr2") AM_WRITE_BANK("bankw2")
AM_RANGE(0x3000, 0x3fff) AM_READ_BANK("bankr3") AM_WRITE_BANK("bankw3")
AM_RANGE(0x4000, 0x4fff) AM_READ_BANK("bankr4") AM_WRITE_BANK("bankw4")
AM_RANGE(0x5000, 0x5fff) AM_READ_BANK("bankr5") AM_WRITE_BANK("bankw5")
AM_RANGE(0x6000, 0x6fff) AM_READ_BANK("bankr6") AM_WRITE_BANK("bankw6")
AM_RANGE(0x7000, 0x7fff) AM_READ_BANK("bankr7") AM_WRITE_BANK("bankw7")
AM_RANGE(0x8000, 0x8fff) AM_READ_BANK("bankr8") AM_WRITE_BANK("bankw8")
AM_RANGE(0x9000, 0x9fff) AM_READ_BANK("bankr9") AM_WRITE_BANK("bankw9")
AM_RANGE(0xa000, 0xafff) AM_READ_BANK("bankr10") AM_WRITE_BANK("bankw10")
AM_RANGE(0xb000, 0xbfff) AM_READ_BANK("bankr11") AM_WRITE_BANK("bankw11")
AM_RANGE(0xc000, 0xcfff) AM_READ_BANK("bankr12") AM_WRITE_BANK("bankw12")
AM_RANGE(0xd000, 0xdfff) AM_READ_BANK("bankr13") AM_WRITE_BANK("bankw13")
AM_RANGE(0xe000, 0xefff) AM_READ_BANK("bankr14") AM_WRITE_BANK("bankw14")
AM_RANGE(0xf000, 0xffff) AM_READ_BANK("bankr15") AM_WRITE_BANK("bankw15")
ADDRESS_MAP_END
static ADDRESS_MAP_START(mbeett_mem, AS_PROGRAM, 8, mbee_state) static ADDRESS_MAP_START(mbeett_mem, AS_PROGRAM, 8, mbee_state)
AM_RANGE(0x0000, 0x0fff) AM_RAMBANK("boot") AM_RANGE(0x0000, 0x0fff) AM_RAMBANK("boot")
AM_RANGE(0x1000, 0x7fff) AM_RAM AM_RANGE(0x1000, 0x7fff) AM_RAM
@ -614,49 +627,12 @@ GFXDECODE_END
static GFXDECODE_START( mbeeppc ) static GFXDECODE_START( mbeeppc )
GFXDECODE_ENTRY( "gfx", 0x0000, mbee_charlayout, 0, 8 ) GFXDECODE_ENTRY( "gfx", 0x0000, mbee_charlayout, 0, 8 )
GFXDECODE_END GFXDECODE_END
#if 0
static LEGACY_FLOPPY_OPTIONS_START(mbee)
LEGACY_FLOPPY_OPTION(ss80, "ss80", "SS80 disk image", basicdsk_identify_default, basicdsk_construct_default, NULL,
HEADS([1])
TRACKS([80])
SECTORS([10])
SECTOR_LENGTH([512])
FIRST_SECTOR_ID([1]))
LEGACY_FLOPPY_OPTION(ds40, "ds40", "DS40 disk image", basicdsk_identify_default, basicdsk_construct_default, NULL,
HEADS([2])
TRACKS([40])
SECTORS([10])
SECTOR_LENGTH([512])
FIRST_SECTOR_ID([1]))
LEGACY_FLOPPY_OPTION(ds80, "ds80", "DS80 disk image", basicdsk_identify_default, basicdsk_construct_default, NULL,
HEADS([2])
TRACKS([80])
SECTORS([10])
SECTOR_LENGTH([512])
FIRST_SECTOR_ID([21]))
LEGACY_FLOPPY_OPTION(ds84, "ds82,ds84", "DS84 disk image", basicdsk_identify_default, basicdsk_construct_default, NULL,
HEADS([2])
TRACKS([80])
SECTORS([10])
SECTOR_LENGTH([512])
FIRST_SECTOR_ID([1]))
LEGACY_FLOPPY_OPTIONS_END
static const floppy_interface mbee_floppy_interface =
{
FLOPPY_STANDARD_5_25_DSHD,
LEGACY_FLOPPY_OPTIONS_NAME(mbee),
NULL
};
#endif
FLOPPY_FORMATS_MEMBER( mbee_state::floppy_formats )
FLOPPY_MBEE_FORMAT
FLOPPY_FORMATS_END
static SLOT_INTERFACE_START( mbee_floppies ) static SLOT_INTERFACE_START( mbee_floppies )
SLOT_INTERFACE( "35dd", FLOPPY_35_DD ) SLOT_INTERFACE( "drive3a", FLOPPY_35_DD )
SLOT_INTERFACE( "525dd", FLOPPY_525_QD ) SLOT_INTERFACE( "drive3b", FLOPPY_35_DD )
SLOT_INTERFACE( "drive5a", FLOPPY_525_QD )
SLOT_INTERFACE( "drive5b", FLOPPY_525_QD )
SLOT_INTERFACE_END SLOT_INTERFACE_END
@ -813,8 +789,10 @@ static MACHINE_CONFIG_DERIVED( mbee56, mbeeic )
MCFG_CPU_IO_MAP(mbee56_io) MCFG_CPU_IO_MAP(mbee56_io)
MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee56 ) MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee56 )
MCFG_WD2793x_ADD("fdc", XTAL_4MHz / 4) // divided by 2 externally, then divided by 2 internally (/ENMF pin not emulated) MCFG_WD2793x_ADD("fdc", XTAL_4MHz / 4) // divided by 2 externally, then divided by 2 internally (/ENMF pin not emulated)
MCFG_FLOPPY_DRIVE_ADD("fdc:0", mbee_floppies, "525dd", mbee_state::floppy_formats) MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(mbee_state, fdc_intrq_w))
MCFG_FLOPPY_DRIVE_ADD("fdc:1", mbee_floppies, "35dd", mbee_state::floppy_formats) MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(mbee_state, fdc_drq_w))
MCFG_FLOPPY_DRIVE_ADD("fdc:0", mbee_floppies, "drive5a", floppy_image_device::default_floppy_formats)
MCFG_FLOPPY_DRIVE_ADD("fdc:1", mbee_floppies, "drive5b", floppy_image_device::default_floppy_formats)
MACHINE_CONFIG_END MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( mbee64, mbee56 ) static MACHINE_CONFIG_DERIVED( mbee64, mbee56 )
@ -830,12 +808,15 @@ static MACHINE_CONFIG_DERIVED( mbee128, mbeeppc )
MCFG_CPU_IO_MAP(mbee128_io) MCFG_CPU_IO_MAP(mbee128_io)
MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee128 ) MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee128 )
MCFG_WD2793x_ADD("fdc", XTAL_4MHz / 4) MCFG_WD2793x_ADD("fdc", XTAL_4MHz / 4)
MCFG_FLOPPY_DRIVE_ADD("fdc:0", mbee_floppies, "35dd", mbee_state::floppy_formats) MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(mbee_state, fdc_intrq_w))
MCFG_FLOPPY_DRIVE_ADD("fdc:1", mbee_floppies, "525dd", mbee_state::floppy_formats) MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(mbee_state, fdc_drq_w))
MCFG_FLOPPY_DRIVE_ADD("fdc:0", mbee_floppies, "drive5a", floppy_image_device::default_floppy_formats)
MCFG_FLOPPY_DRIVE_ADD("fdc:1", mbee_floppies, "drive5b", floppy_image_device::default_floppy_formats)
MACHINE_CONFIG_END MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( mbee256, mbee128 ) static MACHINE_CONFIG_DERIVED( mbee256, mbee128 )
MCFG_CPU_MODIFY( "maincpu" ) MCFG_CPU_MODIFY( "maincpu" )
MCFG_CPU_PROGRAM_MAP(mbee256_mem)
MCFG_CPU_IO_MAP(mbee256_io) MCFG_CPU_IO_MAP(mbee256_io)
MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee256 ) MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee256 )
MCFG_MC146818_ADD( "rtc", XTAL_32_768kHz ) MCFG_MC146818_ADD( "rtc", XTAL_32_768kHz )
@ -846,6 +827,10 @@ static MACHINE_CONFIG_DERIVED( mbee256, mbee128 )
MCFG_MC6845_CHAR_WIDTH(8) MCFG_MC6845_CHAR_WIDTH(8)
MCFG_MC6845_UPDATE_ROW_CB(mbee_state, mbeeppc_update_row) MCFG_MC6845_UPDATE_ROW_CB(mbee_state, mbeeppc_update_row)
MCFG_MC6845_ADDR_CHANGED_CB(mbee_state, mbee256_update_addr) MCFG_MC6845_ADDR_CHANGED_CB(mbee_state, mbee256_update_addr)
MCFG_DEVICE_REMOVE("fdc:0")
MCFG_DEVICE_REMOVE("fdc:1")
MCFG_FLOPPY_DRIVE_ADD("fdc:0", mbee_floppies, "drive3a", floppy_image_device::default_floppy_formats)
MCFG_FLOPPY_DRIVE_ADD("fdc:1", mbee_floppies, "drive3b", floppy_image_device::default_floppy_formats)
MACHINE_CONFIG_END MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( mbeett, mbeeppc ) static MACHINE_CONFIG_DERIVED( mbeett, mbeeppc )
@ -1160,16 +1145,19 @@ ROM_START( mbee128 ) // 128K
ROM_END ROM_END
ROM_START( mbee256 ) // 256tc ROM_START( mbee256 ) // 256tc
ROM_REGION(0x40000,"maincpu", ROMREGION_ERASEFF) ROM_REGION(0x40000, "rams", ROMREGION_ERASEFF)
ROM_REGION(0x7000,"bootrom", ROMREGION_ERASEFF) ROM_REGION(0x5000, "roms", 0) // rom plus dummy area
ROM_SYSTEM_BIOS( 0, "1.20", "Version 1.20" ) ROM_SYSTEM_BIOS( 0, "1.20", "Version 1.20" )
ROMX_LOAD("256tc_boot_1.20.rom", 0x0000, 0x4000, CRC(fe8d6a84) SHA1(a037a1b90b18a2180e9f5f216b829fcd480449a4), ROM_BIOS(1) ) ROMX_LOAD("256tc_boot_1.20.u38", 0x0000, 0x4000, CRC(fe8d6a84) SHA1(a037a1b90b18a2180e9f5f216b829fcd480449a4), ROM_BIOS(1) )
ROM_SYSTEM_BIOS( 1, "1.15", "Version 1.15" ) ROM_SYSTEM_BIOS( 1, "1.15", "Version 1.15" )
ROMX_LOAD("256tc_boot_1.15.rom", 0x0000, 0x4000, CRC(1902062d) SHA1(e4a1c0b3f4996e313da0bac0edb6d34e3270723e), ROM_BIOS(2) ) ROMX_LOAD("256tc_boot_1.15.u38", 0x0000, 0x4000, CRC(1902062d) SHA1(e4a1c0b3f4996e313da0bac0edb6d34e3270723e), ROM_BIOS(2) )
ROM_REGION(0x4000, "proms", 0)
ROM_LOAD( "silver.u39", 0x0000, 0x4000, CRC(c34aab64) SHA1(781fe648488dec90185760f8e081e488b73b68bf) )
ROM_REGION(0x9800, "gfx", 0) ROM_REGION(0x9800, "gfx", 0)
ROM_LOAD("char256.bin", 0x1000, 0x1000, CRC(9372af3c) SHA1(a63591822c0504de2fed52e88d64e1dbd6124b74) ) ROM_LOAD("char256.u53", 0x1000, 0x1000, CRC(9372af3c) SHA1(a63591822c0504de2fed52e88d64e1dbd6124b74) )
ROM_IGNORE( 0x1000 ) // throw away swedish characters for now ROM_IGNORE( 0x1000 ) // throw away swedish characters for now
ROM_COPY( "gfx", 0x1000, 0x0000, 0x1000 ) ROM_COPY( "gfx", 0x1000, 0x0000, 0x1000 )
@ -1184,7 +1172,7 @@ ROM_END
***************************************************************************/ ***************************************************************************/
/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME */ /* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME */
COMP( 1982, mbee, 0, 0, mbee, mbee, mbee_state, mbee, "Applied Technology", "Microbee 16 Standard" , 0 ) COMP( 1982, mbee, 0, 0, mbee, mbee, mbee_state, mbee, "Applied Technology", "Microbee 16 Standard" , 0 )
COMP( 1982, mbeeic, mbee, 0, mbeeic, mbee, mbee_state, mbeeic, "Applied Technology", "Microbee 32 IC" , 0 ) COMP( 1982, mbeeic, mbee, 0, mbeeic, mbee, mbee_state, mbeeic, "Applied Technology", "Microbee 32 IC" , 0 )
COMP( 1982, mbeepc, mbee, 0, mbeepc, mbee, mbee_state, mbeepc, "Applied Technology", "Microbee Personal Communicator" , 0 ) COMP( 1982, mbeepc, mbee, 0, mbeepc, mbee, mbee_state, mbeepc, "Applied Technology", "Microbee Personal Communicator" , 0 )

103
src/mess/includes/mbee.h
View File

@ -34,50 +34,51 @@ public:
}; };
mbee_state(const machine_config &mconfig, device_type type, const char *tag) mbee_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag), : driver_device(mconfig, type, tag)
m_maincpu(*this, "maincpu"), , m_palette(*this, "palette")
m_pio(*this, "z80pio"), , m_maincpu(*this, "maincpu")
m_cassette(*this, "cassette"), , m_pio(*this, "z80pio")
m_wave(*this, WAVE_TAG), , m_cassette(*this, "cassette")
m_speaker(*this, "speaker"), , m_wave(*this, WAVE_TAG)
m_centronics(*this, "centronics"), , m_speaker(*this, "speaker")
m_cent_data_out(*this, "cent_data_out"), , m_centronics(*this, "centronics")
m_crtc(*this, "crtc"), , m_cent_data_out(*this, "cent_data_out")
m_fdc(*this, "fdc"), , m_crtc(*this, "crtc")
m_floppy0(*this, "fdc:0"), , m_fdc(*this, "fdc")
m_floppy1(*this, "fdc:1"), , m_floppy0(*this, "fdc:0")
m_rtc(*this, "rtc"), , m_floppy1(*this, "fdc:1")
m_boot(*this, "boot"), , m_rtc(*this, "rtc")
m_pak(*this, "pak"), , m_boot(*this, "boot")
m_telcom(*this, "telcom"), , m_pak(*this, "pak")
m_basic(*this, "basic"), , m_telcom(*this, "telcom")
m_bankl(*this, "bankl"), , m_basic(*this, "basic")
m_bankh(*this, "bankh"), , m_bankl(*this, "bankl")
m_bank1(*this, "bank1"), , m_bankh(*this, "bankh")
m_bank8l(*this, "bank8l"), , m_bank1(*this, "bank1")
m_bank8h(*this, "bank8h"), , m_bank8l(*this, "bank8l")
m_bank9(*this, "bank9"), , m_bank8h(*this, "bank8h")
m_bankfl(*this, "bankfl"), , m_bank9(*this, "bank9")
m_bankfh(*this, "bankfh"), , m_bankfl(*this, "bankfl")
m_io_x0(*this, "X0"), , m_bankfh(*this, "bankfh")
m_io_x1(*this, "X1"), , m_io_x0(*this, "X0")
m_io_x2(*this, "X2"), , m_io_x1(*this, "X1")
m_io_x3(*this, "X3"), , m_io_x2(*this, "X2")
m_io_x4(*this, "X4"), , m_io_x3(*this, "X3")
m_io_x5(*this, "X5"), , m_io_x4(*this, "X4")
m_io_x6(*this, "X6"), , m_io_x5(*this, "X5")
m_io_x7(*this, "X7"), , m_io_x6(*this, "X6")
m_io_extra(*this, "EXTRA"), , m_io_x7(*this, "X7")
m_io_config(*this, "CONFIG"), , m_io_extra(*this, "EXTRA")
m_io_x8(*this, "X8"), , m_io_config(*this, "CONFIG")
m_io_x9(*this, "X9"), , m_io_x8(*this, "X8")
m_io_x10(*this, "X10"), , m_io_x9(*this, "X9")
m_io_x11(*this, "X11"), , m_io_x10(*this, "X10")
m_io_x12(*this, "X12"), , m_io_x11(*this, "X11")
m_io_x13(*this, "X13"), , m_io_x12(*this, "X12")
m_io_x14(*this, "X14"), , m_io_x13(*this, "X13")
m_screen(*this, "screen"), , m_io_x14(*this, "X14")
m_palette(*this, "palette") { } , m_screen(*this, "screen")
{ }
DECLARE_WRITE8_MEMBER( mbee_04_w ); DECLARE_WRITE8_MEMBER( mbee_04_w );
DECLARE_WRITE8_MEMBER( mbee_06_w ); DECLARE_WRITE8_MEMBER( mbee_06_w );
@ -148,6 +149,8 @@ public:
TIMER_CALLBACK_MEMBER(mbee_reset); TIMER_CALLBACK_MEMBER(mbee_reset);
DECLARE_QUICKLOAD_LOAD_MEMBER( mbee ); DECLARE_QUICKLOAD_LOAD_MEMBER( mbee );
DECLARE_QUICKLOAD_LOAD_MEMBER( mbee_z80bin ); DECLARE_QUICKLOAD_LOAD_MEMBER( mbee_z80bin );
WRITE_LINE_MEMBER(fdc_intrq_w);
WRITE_LINE_MEMBER(fdc_drq_w);
DECLARE_FLOPPY_FORMATS(floppy_formats); DECLARE_FLOPPY_FORMATS(floppy_formats);
UINT8 *m_p_videoram; UINT8 *m_p_videoram;
UINT8 *m_p_gfxram; UINT8 *m_p_gfxram;
@ -165,6 +168,7 @@ public:
MC6845_ON_UPDATE_ADDR_CHANGED(mbee_update_addr); MC6845_ON_UPDATE_ADDR_CHANGED(mbee_update_addr);
MC6845_ON_UPDATE_ADDR_CHANGED(mbee256_update_addr); MC6845_ON_UPDATE_ADDR_CHANGED(mbee256_update_addr);
required_device<palette_device> m_palette;
private: private:
size_t m_size; size_t m_size;
UINT8 m_clock_pulse; UINT8 m_clock_pulse;
@ -178,8 +182,12 @@ private:
UINT8 m_sy6545_status; UINT8 m_sy6545_status;
UINT8 m_sy6545_reg[32]; UINT8 m_sy6545_reg[32];
UINT8 m_sy6545_ind; UINT8 m_sy6545_ind;
UINT8 m_fdc_rq;
void mbee256_setup_banks(UINT8 data);
void sy6545_cursor_configure(); void sy6545_cursor_configure();
void keyboard_matrix_r(int offs); void keyboard_matrix_r(int offs);
void machine_reset_common_disk();
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
required_device<cpu_device> m_maincpu; required_device<cpu_device> m_maincpu;
required_device<z80pio_device> m_pio; required_device<z80pio_device> m_pio;
required_device<cassette_image_device> m_cassette; required_device<cassette_image_device> m_cassette;
@ -192,7 +200,7 @@ private:
optional_device<floppy_connector> m_floppy0; optional_device<floppy_connector> m_floppy0;
optional_device<floppy_connector> m_floppy1; optional_device<floppy_connector> m_floppy1;
optional_device<mc146818_device> m_rtc; optional_device<mc146818_device> m_rtc;
required_memory_bank m_boot; optional_memory_bank m_boot;
optional_memory_bank m_pak; optional_memory_bank m_pak;
optional_memory_bank m_telcom; optional_memory_bank m_telcom;
optional_memory_bank m_basic; optional_memory_bank m_basic;
@ -222,11 +230,6 @@ private:
optional_ioport m_io_x13; optional_ioport m_io_x13;
optional_ioport m_io_x14; optional_ioport m_io_x14;
required_device<screen_device> m_screen; required_device<screen_device> m_screen;
public:
required_device<palette_device> m_palette;
void machine_reset_common_disk();
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
}; };
#endif /* MBEE_H_ */ #endif /* MBEE_H_ */

195
src/mess/machine/mbee.c
View File

@ -89,12 +89,22 @@ READ8_MEMBER( mbee_state::pio_port_b_r )
*************************************************************************************/ *************************************************************************************/
WRITE_LINE_MEMBER( mbee_state::fdc_intrq_w )
{
m_fdc_rq = (m_fdc_rq & 2) | state;
}
WRITE_LINE_MEMBER( mbee_state::fdc_drq_w )
{
m_fdc_rq = (m_fdc_rq & 1) | (state << 1);
}
READ8_MEMBER( mbee_state::mbee_fdc_status_r ) READ8_MEMBER( mbee_state::mbee_fdc_status_r )
{ {
/* d7 indicate if IRQ or DRQ is occuring (1=happening) /* d7 indicate if IRQ or DRQ is occuring (1=happening)
d6..d0 not used */ d6..d0 not used */
return 0x7f | ((m_fdc->intrq_r() || m_fdc->drq_r()) ? 0x80 : 0); return m_fdc_rq ? 0xff : 0x7f;
} }
WRITE8_MEMBER( mbee_state::mbee_fdc_motor_w ) WRITE8_MEMBER( mbee_state::mbee_fdc_motor_w )
@ -131,7 +141,7 @@ WRITE8_MEMBER( mbee_state::mbee_fdc_motor_w )
TIMER_CALLBACK_MEMBER(mbee_state::mbee256_kbd) TIMER_CALLBACK_MEMBER(mbee_state::mbee256_kbd)
{ {
/* Keyboard scanner is a Mostek M3870 chip. Its speed of operation is determined by a 15k resistor on /* Keyboard scanner is a Mostek M3870 chip. Its speed of operation is determined by a 15k resistor on
pin 2 (XTL2) and is therefore unknown. If a key change is detected (up or down), the /strobe pin 2 (XTL2) and is therefore 2MHz. If a key change is detected (up or down), the /strobe
line activates, sending a high to bit 1 of port 2 (one of the pio input lines). The next read of line activates, sending a high to bit 1 of port 2 (one of the pio input lines). The next read of
port 18 will clear this line, and read the key scancode. It will also signal the 3870 that the key port 18 will clear this line, and read the key scancode. It will also signal the 3870 that the key
data has been read, on pin 38 (/extint). The 3870 can cache up to 9 keys. With no rom dump data has been read, on pin 38 (/extint). The 3870 can cache up to 9 keys. With no rom dump
@ -256,83 +266,79 @@ TIMER_CALLBACK_MEMBER(mbee_state::mbee_rtc_irq)
256TC Memory Banking 256TC Memory Banking
Bits 0, 1 and 5 select which bank goes into 0000-7FFF. Selection of ROM, RAM, and video access by the CPU is controlled by U39,
Bit 2 disables ROM, replacing it with RAM. a PAL14L8. When read as an ordinary rom it is 16k in size. The dumper has
Bit 3 disables Video, replacing it with RAM. arranged the pins as (bit0,1,..) (input = 1,23,2,3,4,5,6,7,8,9,10,11,14,13)
Bit 4 switches the video circuits between F000-FFFF and and (output = 22,21,20,19,18,17,16,15). The prom is also used to control
8000-8FFF. the refresh required by the dynamic rams, however we ignore this function.
In case of a clash, video overrides ROM which overrides RAM.
************************************************************/ ************************************************************/
void mbee_state::mbee256_setup_banks(UINT8 data)
{
data &= 0x3f; // U28 (bits 0-5 are referred to as S0-S5)
address_space &mem = m_maincpu->space(AS_PROGRAM);
UINT8 *prom = memregion("proms")->base();
UINT8 b_data = BITSWAP8(data, 7,5,3,2,4,6,1,0) & 0x3b; // arrange data bits to S0,S1,-,S4,S2,S3
UINT8 b_bank, b_byte, b_byte_t, b_addr;
UINT16 b_vid;
char banktag[10];
for (b_bank = 0; b_bank < 16; b_bank++)
{
b_vid = b_bank << 12;
mem.unmap_readwrite (b_vid, b_vid + 0xfff);
b_addr = BITSWAP8(b_bank, 7,4,5,3,1,2,6,0) & 0x1f; // arrange address bits to A12,-,A14,A13,A15
// Calculate read-bank
b_byte_t = prom[b_addr | (b_data << 8) | 0x82]; // read-bank (RDS and MREQ are low, RFSH is high)
b_byte = BITSWAP8(b_byte_t, 7,5,0,3,6,2,1,4); // rearrange so that bits 0-2 are rambank, bit 3 = rom select, bit 4 = video select, others not used
if (!BIT(data, 5))
b_byte &= 0xfb; // U42/1 - S17 only valid if S5 is on
if (!BIT(b_byte, 4))
{
// select video
mem.install_read_handler (b_vid, b_vid + 0x7ff, read8_delegate(FUNC(mbee_state::mbeeppc_low_r), this));
mem.install_read_handler (b_vid + 0x800, b_vid + 0xfff, read8_delegate(FUNC(mbee_state::mbeeppc_high_r), this));
}
else
{
sprintf(banktag, "bankr%d", b_bank);
mem.install_read_bank( b_vid, b_vid+0xfff, banktag );
if (!BIT(b_byte, 3))
membank(banktag)->set_entry(64 + (b_bank & 3)); // read from rom
else
membank(banktag)->set_entry((b_bank & 7) | ((b_byte & 7) << 3)); // ram
}
// Calculate write-bank
b_byte_t = prom[b_addr | (b_data << 8) | 0xc0]; // write-bank (XWR and MREQ are low, RFSH is high)
b_byte = BITSWAP8(b_byte_t, 7,5,0,3,6,2,1,4); // rearrange so that bits 0-2 are rambank, bit 3 = rom select, bit 4 = video select, others not used
if (!BIT(data, 5))
b_byte &= 0xfb; // U42/1 - S17 only valid if S5 is on
if (!BIT(b_byte, 4))
{
// select video
mem.install_write_handler (b_vid, b_vid + 0x7ff, write8_delegate(FUNC(mbee_state::mbeeppc_low_w), this));
mem.install_write_handler (b_vid + 0x800, b_vid + 0xfff, write8_delegate(FUNC(mbee_state::mbeeppc_high_w), this));
}
else
{
sprintf(banktag, "bankw%d", b_bank);
mem.install_write_bank( b_vid, b_vid+0xfff, banktag );
if (!BIT(b_byte, 3))
membank(banktag)->set_entry(64); // write to rom dummy area
else
membank(banktag)->set_entry((b_bank & 7) | ((b_byte & 7) << 3)); // ram
}
}
}
WRITE8_MEMBER( mbee_state::mbee256_50_w ) WRITE8_MEMBER( mbee_state::mbee256_50_w )
{ {
address_space &mem = m_maincpu->space(AS_PROGRAM); mbee256_setup_banks(data);
// primary low banks
m_boot->set_entry((data & 3) | ((data & 0x20) >> 3));
m_bank1->set_entry((data & 3) | ((data & 0x20) >> 3));
// 9000-EFFF
m_bank9->set_entry((data & 4) ? 1 : 0);
// 8000-8FFF, F000-FFFF
mem.unmap_readwrite (0x8000, 0x87ff);
mem.unmap_readwrite (0x8800, 0x8fff);
mem.unmap_readwrite (0xf000, 0xf7ff);
mem.unmap_readwrite (0xf800, 0xffff);
switch (data & 0x1c)
{
case 0x00:
mem.install_read_bank (0x8000, 0x87ff, "bank8l");
mem.install_read_bank (0x8800, 0x8fff, "bank8h");
mem.install_readwrite_handler (0xf000, 0xf7ff, read8_delegate(FUNC(mbee_state::mbeeppc_low_r), this), write8_delegate(FUNC(mbee_state::mbeeppc_low_w), this));
mem.install_readwrite_handler (0xf800, 0xffff, read8_delegate(FUNC(mbee_state::mbeeppc_high_r), this), write8_delegate(FUNC(mbee_state::mbeeppc_high_w), this));
m_bank8l->set_entry(0); // rom
m_bank8h->set_entry(0); // rom
break;
case 0x04:
mem.install_read_bank (0x8000, 0x87ff, "bank8l");
mem.install_read_bank (0x8800, 0x8fff, "bank8h");
mem.install_readwrite_handler (0xf000, 0xf7ff, read8_delegate(FUNC(mbee_state::mbeeppc_low_r), this), write8_delegate(FUNC(mbee_state::mbeeppc_low_w), this));
mem.install_readwrite_handler (0xf800, 0xffff, read8_delegate(FUNC(mbee_state::mbeeppc_high_r), this), write8_delegate(FUNC(mbee_state::mbeeppc_high_w), this));
m_bank8l->set_entry(1); // ram
m_bank8h->set_entry(1); // ram
break;
case 0x08:
case 0x18:
mem.install_read_bank (0x8000, 0x87ff, "bank8l");
mem.install_read_bank (0x8800, 0x8fff, "bank8h");
mem.install_read_bank (0xf000, 0xf7ff, "bankfl");
mem.install_read_bank (0xf800, 0xffff, "bankfh");
m_bank8l->set_entry(0); // rom
m_bank8h->set_entry(0); // rom
m_bankfl->set_entry(0); // ram
m_bankfh->set_entry(0); // ram
break;
case 0x0c:
case 0x1c:
mem.install_read_bank (0x8000, 0x87ff, "bank8l");
mem.install_read_bank (0x8800, 0x8fff, "bank8h");
mem.install_read_bank (0xf000, 0xf7ff, "bankfl");
mem.install_read_bank (0xf800, 0xffff, "bankfh");
m_bank8l->set_entry(1); // ram
m_bank8h->set_entry(1); // ram
m_bankfl->set_entry(0); // ram
m_bankfh->set_entry(0); // ram
break;
case 0x10:
case 0x14:
mem.install_readwrite_handler (0x8000, 0x87ff, read8_delegate(FUNC(mbee_state::mbeeppc_low_r), this), write8_delegate(FUNC(mbee_state::mbeeppc_low_w), this));
mem.install_readwrite_handler (0x8800, 0x8fff, read8_delegate(FUNC(mbee_state::mbeeppc_high_r), this), write8_delegate(FUNC(mbee_state::mbeeppc_high_w), this));
mem.install_read_bank (0xf000, 0xf7ff, "bankfl");
mem.install_read_bank (0xf800, 0xffff, "bankfh");
m_bankfl->set_entry(0); // ram
m_bankfh->set_entry(0); // ram
break;
}
} }
/*********************************************************** /***********************************************************
@ -508,6 +514,7 @@ TIMER_CALLBACK_MEMBER(mbee_state::mbee_reset)
void mbee_state::machine_reset_common_disk() void mbee_state::machine_reset_common_disk()
{ {
m_fdc_rq = 0;
} }
MACHINE_RESET_MEMBER(mbee_state,mbee) MACHINE_RESET_MEMBER(mbee_state,mbee)
@ -533,22 +540,20 @@ MACHINE_RESET_MEMBER(mbee_state,mbee64)
MACHINE_RESET_MEMBER(mbee_state,mbee128) MACHINE_RESET_MEMBER(mbee_state,mbee128)
{ {
address_space &mem = m_maincpu->space(AS_PROGRAM); address_space &mem = m_maincpu->space(AS_IO);
machine_reset_common_disk(); machine_reset_common_disk();
mbee128_50_w(mem,0,0); // set banks to default mbee128_50_w(mem,0,0); // set banks to default
m_boot->set_entry(4); // boot time m_boot->set_entry(8); // boot time
} }
MACHINE_RESET_MEMBER(mbee_state,mbee256) MACHINE_RESET_MEMBER(mbee_state,mbee256)
{ {
UINT8 i; UINT8 i;
address_space &mem = m_maincpu->space(AS_PROGRAM);
machine_reset_common_disk(); machine_reset_common_disk();
for (i = 0; i < 15; i++) m_mbee256_was_pressed[i] = 0; for (i = 0; i < 15; i++) m_mbee256_was_pressed[i] = 0;
m_mbee256_q_pos = 0; m_mbee256_q_pos = 0;
mbee256_50_w(mem,0,0); // set banks to default mbee256_setup_banks(0); // set banks to default
m_boot->set_entry(8); // boot time m_maincpu->set_pc(0x8000);
timer_set(attotime::from_usec(4), TIMER_MBEE_RESET);
} }
MACHINE_RESET_MEMBER(mbee_state,mbeett) MACHINE_RESET_MEMBER(mbee_state,mbeett)
@ -690,7 +695,7 @@ DRIVER_INIT_MEMBER(mbee_state,mbee128)
RAM = memregion("bootrom")->base(); RAM = memregion("bootrom")->base();
m_bank9->configure_entry(0, &RAM[0x1000]); // rom m_bank9->configure_entry(0, &RAM[0x1000]); // rom
m_boot->configure_entry(4, &RAM[0x0000]); // rom at boot for 4usec m_boot->configure_entry(8, &RAM[0x0000]); // rom at boot for 4usec
m_bank8l->configure_entry(0, &RAM[0x0000]); // rom m_bank8l->configure_entry(0, &RAM[0x0000]); // rom
m_bank8h->configure_entry(0, &RAM[0x0800]); // rom m_bank8h->configure_entry(0, &RAM[0x0800]); // rom
@ -699,23 +704,23 @@ DRIVER_INIT_MEMBER(mbee_state,mbee128)
DRIVER_INIT_MEMBER(mbee_state,mbee256) DRIVER_INIT_MEMBER(mbee_state,mbee256)
{ {
UINT8 *RAM = memregion("maincpu")->base(); UINT8 *RAM = memregion("rams")->base();
m_boot->configure_entries(0, 8, &RAM[0x0000], 0x8000); // standard banks 0000 UINT8 *ROM = memregion("roms")->base();
m_bank1->configure_entries(0, 8, &RAM[0x1000], 0x8000); // standard banks 1000 char banktag[10];
m_bank8l->configure_entry(1, &RAM[0x0000]); // shadow ram
m_bank8h->configure_entry(1, &RAM[0x0800]); // shadow ram
m_bank9->configure_entry(1, &RAM[0x1000]); // shadow ram
m_bankfl->configure_entry(0, &RAM[0xf000]); // shadow ram
m_bankfh->configure_entry(0, &RAM[0xf800]); // shadow ram
RAM = memregion("bootrom")->base(); for (UINT8 b_bank = 0; b_bank < 16; b_bank++)
m_bank9->configure_entry(0, &RAM[0x1000]); // rom {
m_boot->configure_entry(8, &RAM[0x0000]); // rom at boot for 4usec sprintf(banktag, "bankr%d", b_bank);
m_bank8l->configure_entry(0, &RAM[0x0000]); // rom membank(banktag)->configure_entries(0, 64, &RAM[0x0000], 0x1000); // RAM banks
m_bank8h->configure_entry(0, &RAM[0x0800]); // rom membank(banktag)->configure_entries(64, 4, &ROM[0x0000], 0x1000); // rom
sprintf(banktag, "bankw%d", b_bank);
membank(banktag)->configure_entries(0, 64, &RAM[0x0000], 0x1000); // RAM banks
membank(banktag)->configure_entries(64, 1, &ROM[0x4000], 0x1000); // dummy rom
}
timer_set(attotime::from_hz(1), TIMER_MBEE_RTC_IRQ); /* timer for rtc */ timer_set(attotime::from_hz(1), TIMER_MBEE_RTC_IRQ); /* timer for rtc */
timer_set(attotime::from_hz(25), TIMER_MBEE256_KBD); /* timer for kbd */ timer_set(attotime::from_hz(50), TIMER_MBEE256_KBD); /* timer for kbd */
m_size = 0x8000; m_size = 0x8000;
} }