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(MESS) excalibur : added rom banking. Fixed missing key in keyboard. (nw)
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@ -9,16 +9,17 @@ Skeleton driver created on 2014-12-09.
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Chips: Z80A, 8251, 8253, 8255, 6845
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We have Basic 1.1. Other known versions are 1.01, 2.1
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There are 2 versions of the colour prom, which have different palettes.
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We have the later version.
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Control W then Enter will switch between 40 and 80 characters per line.
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ToDo:
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- Some keys can be connected to more than one position in the matrix. Need to
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determine the correct positions.
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- The position of the "Line Insert" key is unknown.
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- Colours are approximate.
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- Disk controller
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- ROM banking
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- Graphics commands such as LINE and CIRCLE produce a syntax error.
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- Some commands such as HGRCLS are missing from the rom. Perhaps we need a later version?
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- SET command produces random graphics instead of the expected lo-res dot.
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- The schematic shows the audio counter connected to 2MHz, but this produces
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sounds that are too high. Connected to 1MHz for now.
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- Serial
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@ -103,7 +104,6 @@ static ADDRESS_MAP_START(excali64_io, AS_IO, 8, excali64_state)
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ADDRESS_MAP_END
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// Keyboard matrix is not included in schematics, so some guesswork
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static INPUT_PORTS_START( excali64 )
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PORT_START("KEY.0") /* line 0 */
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PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("R") PORT_CODE(KEYCODE_R) PORT_CHAR('r') PORT_CHAR('R') PORT_CHAR(0x12)
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@ -153,7 +153,7 @@ static INPUT_PORTS_START( excali64 )
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PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("DEL") PORT_CODE(KEYCODE_DEL) PORT_CHAR(0x7f) PORT_CHAR(0x7f) PORT_CHAR(0x1f)
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PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("ESC") PORT_CODE(KEYCODE_ESC) PORT_CHAR(0x1b)
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PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("1 !") PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!')
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PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_UNUSED) //1
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PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("INS") PORT_CODE(KEYCODE_INSERT)
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PORT_START("KEY.5") /* line 5 */
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PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("[ {") PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('[') PORT_CHAR('{') PORT_CHAR(0x1b)
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@ -245,8 +245,6 @@ WRITE8_MEMBER( excali64_state::port70_w )
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membank("bankr1")->set_entry(0);
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membank("bankr2")->set_entry(0);
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membank("bankr3")->set_entry(0);
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membank("bankr4")->set_entry(0);
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membank("bankw1")->set_entry(0);
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membank("bankw2")->set_entry(0);
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membank("bankw3")->set_entry(0);
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membank("bankw4")->set_entry(0);
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@ -258,8 +256,6 @@ WRITE8_MEMBER( excali64_state::port70_w )
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membank("bankr1")->set_entry(1);
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membank("bankr2")->set_entry(1);
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membank("bankr3")->set_entry(1);
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membank("bankr4")->set_entry(0);
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membank("bankw1")->set_entry(0);
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membank("bankw2")->set_entry(2);
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membank("bankw3")->set_entry(2);
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membank("bankw4")->set_entry(2);
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@ -270,12 +266,14 @@ WRITE8_MEMBER( excali64_state::port70_w )
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membank("bankr1")->set_entry(1);
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membank("bankr2")->set_entry(1);
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membank("bankr3")->set_entry(1);
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membank("bankr4")->set_entry(0);
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membank("bankw1")->set_entry(0);
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membank("bankw2")->set_entry(2);
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membank("bankw3")->set_entry(2);
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membank("bankw4")->set_entry(0);
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}
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// other half of ROM_1
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if ((data & 0x22) == 0x20)
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membank("bankr1")->set_entry(2);
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}
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MACHINE_RESET_MEMBER( excali64_state, excali64 )
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@ -342,6 +340,7 @@ PALETTE_INIT_MEMBER( excali64_state, excali64 )
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membank("bankw4")->configure_entry(0, &ram[0x4000]);//boot
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// rom_1
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membank("bankr1")->configure_entry(1, &main[0x0000]);//boot
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membank("bankr1")->configure_entry(2, &main[0x2000]);
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// rom_2
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membank("bankr2")->configure_entry(1, &main[0x4000]);//boot
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membank("bankr3")->configure_entry(1, &main[0x5000]);//boot
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