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remove many mainly PCI-related MCFG macros in favour of constructor

Browse Source 
overloads, remove some absolute device lookups, remove some absolute
device tags, and generally clean up stuff

fix incorrect device class for PCI APIC

(nw) xbox machine config looks ugly now - the devices should expose
proper constructor overloads that accept the parts of the PCI ID that
are in system PROM or customisable by the OEM and hard-code the parts
inherent to the device
This commit is contained in:
Vas Crabb 2018-05-25 22:28:49 +10:00
parent fada3dfc8b
commit 106e274784
52 changed files with 384 additions and 444 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/devices/bus/lpci/i82439tx.cpp
View File

@ -15,11 +15,11 @@
IMPLEMENTATION
***************************************************************************/
DEFINE_DEVICE_TYPE(I82439TX, i82439tx_device, "i82439tx", "Intel 82439TX")
DEFINE_DEVICE_TYPE(I82439TX_LEGACY, i82439tx_device, "i82439tx_legacy", "Intel 82439TX")
i82439tx_device::i82439tx_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: northbridge_device(mconfig, I82439TX, tag, owner, clock),
: northbridge_device(mconfig, I82439TX_LEGACY, tag, owner, clock),
pci_device_interface(mconfig, *this),
m_cpu_tag(nullptr),
m_region_tag(nullptr),

2
src/devices/bus/lpci/i82439tx.h
View File

@ -74,6 +74,6 @@ private:
};
// device type definition
DECLARE_DEVICE_TYPE(I82439TX, i82439tx_device)
DECLARE_DEVICE_TYPE(I82439TX_LEGACY, i82439tx_device)
#endif // MAME_BUS_LPCI_I82439TX_H

19
src/devices/machine/gt64xxx.cpp
View File

@ -24,7 +24,7 @@
*
*************************************/
#define TIMER_PERIOD attotime::from_hz(m_clock)
#define TIMER_PERIOD attotime::from_hz(clock())
#define PCI_BUS_CLOCK 33000000
// Number of dma words to transfer at a time, real hardware configurable between 8-32
#define DMA_BURST_SIZE 32
@ -161,12 +161,12 @@ void gt64xxx_device::cpu_map(address_map &map)
}
gt64xxx_device::gt64xxx_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: pci_host_device(mconfig, GT64XXX, tag, owner, clock),
m_be(0), m_autoconfig(0), m_irq_num(-1),
m_mem_config("memory_space", ENDIANNESS_LITTLE, 32, 32),
m_io_config("io_space", ENDIANNESS_LITTLE, 32, 32),
m_romRegion(*this, "rom"),
m_updateRegion(*this, "update")
: pci_host_device(mconfig, GT64XXX, tag, owner, clock)
, m_cpu(*this, finder_base::DUMMY_TAG), m_be(0), m_autoconfig(0), m_irq_num(-1)
, m_mem_config("memory_space", ENDIANNESS_LITTLE, 32, 32)
, m_io_config("io_space", ENDIANNESS_LITTLE, 32, 32)
, m_romRegion(*this, "rom")
, m_updateRegion(*this, "update")
{
for (int csIndex = 0; csIndex < 4; csIndex++) {
m_cs_devices[csIndex] = nullptr;
@ -191,7 +191,6 @@ device_memory_interface::space_config_vector gt64xxx_device::memory_space_config
void gt64xxx_device::device_start()
{
pci_host_device::device_start();
m_cpu = machine().device<mips3_device>(cpu_tag);
m_cpu_space = &m_cpu->space(AS_PCI_CONFIG);
memory_space = &space(AS_PCI_MEM);
io_space = &space(AS_PCI_IO);
@ -637,7 +636,7 @@ READ32_MEMBER (gt64xxx_device::cpu_if_r)
result = timer->count;
if (timer->active)
{
uint32_t elapsed = (timer->timer->elapsed() * m_clock).as_double();
uint32_t elapsed = (timer->timer->elapsed() * clock()).as_double();
result = (result > elapsed) ? (result - elapsed) : 0;
}
@ -780,7 +779,7 @@ WRITE32_MEMBER(gt64xxx_device::cpu_if_w)
}
else if (timer->active && !(data & mask))
{
uint32_t elapsed = (timer->timer->elapsed() * m_clock).as_double();
uint32_t elapsed = (timer->timer->elapsed() * clock()).as_double();
timer->active = 0;
timer->count = (timer->count > elapsed) ? (timer->count - elapsed) : 0;
timer->timer->adjust(attotime::never, which);

51
src/devices/machine/gt64xxx.h
View File

@ -14,59 +14,62 @@
// Supports R4600/4650/4700/R5000 CPUs
#define MCFG_GT64010_ADD(_tag, _cpu_tag, _clock, _irq_num) \
MCFG_PCI_HOST_ADD(_tag, GT64XXX, 0x11ab0146, 0x03, 0x00000000) \
downcast<gt64xxx_device *>(device)->set_cpu_tag(_cpu_tag); \
downcast<gt64xxx_device *>(device)->set_clock(_clock); \
downcast<gt64xxx_device *>(device)->set_irq_num(_irq_num);
MCFG_DEVICE_ADD(_tag, GT64XXX, _clock, _cpu_tag, _irq_num) \
downcast<gt64xxx_device &>(*device).set_ids_host(0x11ab0146, 0x03, 0x00000000);
// Supports the following 32-bit bus CPUs:
// IDT RC4640 and RC4650 (in 32-bit mode)
// QED RM523X
// NEC/Toshiba VR4300
#define MCFG_GT64111_ADD(_tag, _cpu_tag, _clock, _irq_num) \
MCFG_PCI_DEVICE_ADD(_tag, GT64XXX, 0x414611ab, 0x10, 0x058000, 0x00000000) \
downcast<gt64xxx_device *>(device)->set_cpu_tag(_cpu_tag); \
downcast<gt64xxx_device *>(device)->set_clock(_clock); \
downcast<gt64xxx_device *>(device)->set_irq_num(_irq_num);
MCFG_DEVICE_ADD(_tag, GT64XXX, _clock, _cpu_tag, _irq_num) \
downcast<gt64xxx_device &>(*device).set_ids(0x414611ab, 0x10, 0x058000, 0x00000000);
#define MCFG_GT64XXX_SET_BE_CPU(_be) \
downcast<gt64xxx_device *>(device)->set_be(_be);
downcast<gt64xxx_device &>(*device).set_be(_be);
#define MCFG_GT64XXX_IRQ_ADD(_irq_num) \
downcast<gt64xxx_device *>(device)->set_irq_info(_irq_num);
downcast<gt64xxx_device &>(*device).set_irq_info(_irq_num);
#define MCFG_GT64XXX_SET_CS(_cs_num, _map) \
downcast<gt64xxx_device *>(device)->set_map(_cs_num, address_map_constructor(&_map, #_map, this), this);
downcast<gt64xxx_device &>(*device).set_map(_cs_num, address_map_constructor(&_map, #_map, this), this);
#define MCFG_GT64XX_SET_SIMM(_index, _size) \
downcast<gt64xxx_device *>(device)->set_simm_size(_index, _size);
downcast<gt64xxx_device &>(*device).set_simm_size(_index, _size);
#define MCFG_GT64XX_SET_SIMM0(_size) \
downcast<gt64xxx_device *>(device)->set_simm0_size(_size);
downcast<gt64xxx_device &>(*device).set_simm0_size(_size);
#define MCFG_GT64XX_SET_SIMM1(_size) \
downcast<gt64xxx_device *>(device)->set_simm1_size(_size);
downcast<gt64xxx_device &>(*device).set_simm1_size(_size);
/*************************************
* Structures
*************************************/
class gt64xxx_device : public pci_host_device {
public:
template <typename T>
gt64xxx_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&cpu_tag, int irq_num)
: gt64xxx_device(mconfig, tag, owner, clock)
{
set_cpu_tag(std::forward<T>(cpu_tag));
set_irq_num(irq_num);
}
gt64xxx_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
virtual void reset_all_mappings() override;
virtual void map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space) override;
void set_cpu_tag(const char *tag) { cpu_tag = tag;}
void set_clock(const uint32_t clock) {m_clock = clock;}
void set_be(const int be) {m_be = be;}
void set_autoconfig(const int autoconfig) {m_autoconfig = autoconfig;}
void set_irq_num(const int irq_num) {m_irq_num = irq_num;}
template <typename T> void set_cpu_tag(T &&tag) { m_cpu.set_tag(std::forward<T>(tag)); }
void set_be(int be) { m_be = be; }
void set_autoconfig(int autoconfig) { m_autoconfig = autoconfig; }
void set_irq_num(int irq_num) { m_irq_num = irq_num; }
virtual void config_map(address_map &map) override;
void set_simm_size(const int index, const int size) { m_simm_size[index] = size; };
void set_simm0_size(const int size) { m_simm_size[0] = size; };
void set_simm1_size(const int size) { m_simm_size[1] = size; };
void set_simm_size(int index, int size) { m_simm_size[index] = size; };
void set_simm0_size(int size) { m_simm_size[0] = size; };
void set_simm1_size(int size) { m_simm_size[1] = size; };
DECLARE_WRITE_LINE_MEMBER(pci_stall);
@ -134,9 +137,7 @@ private:
galileo_addr_map() : low_addr(0xffffffff), high_addr(0x0) {}
};
mips3_device *m_cpu;
const char *cpu_tag;
uint32_t m_clock;
required_device<mips3_device> m_cpu;
int m_be, m_autoconfig;
int m_irq_num;
int m_simm_size[4];

11
src/devices/machine/i6300esb.cpp
View File

@ -90,12 +90,13 @@ void i6300esb_lpc_device::internal_io_map(address_map &map)
i6300esb_lpc_device::i6300esb_lpc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: pci_device(mconfig, I6300ESB_LPC, tag, owner, clock),
acpi(*this, "acpi"),
rtc (*this, "rtc"),
pit (*this, "pit"),
m_region(*this, DEVICE_SELF)
: pci_device(mconfig, I6300ESB_LPC, tag, owner, clock)
, acpi(*this, "acpi")
, rtc (*this, "rtc")
, pit (*this, "pit")
, m_region(*this, DEVICE_SELF)
{
set_ids(0x808625a1, 0x02, 0x060100, 0x00000000);
}
void i6300esb_lpc_device::device_start()

12
src/devices/machine/i6300esb.h
View File

@ -10,12 +10,6 @@
#include "lpc-rtc.h"
#include "lpc-pit.h"
#define MCFG_I6300ESB_LPC_ADD(_tag) \
MCFG_PCI_DEVICE_ADD(_tag, I6300ESB_LPC, 0x808625a1, 0x02, 0x060100, 0x00000000)
#define MCFG_I6300ESB_WATCHDOG_ADD(_tag, _subdevice_id) \
MCFG_PCI_DEVICE_ADD(_tag, I6300ESB_WATCHDOG, 0x808625ab, 0x02, 0x088000, _subdevice_id)
class i6300esb_lpc_device : public pci_device {
public:
i6300esb_lpc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
@ -26,7 +20,6 @@ public:
virtual void config_map(address_map &map) override;
protected:
virtual void device_start() override;
virtual void device_reset() override;
@ -145,6 +138,11 @@ private:
class i6300esb_watchdog_device : public pci_device {
public:
i6300esb_watchdog_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, uint32_t subdevice_id)
: i6300esb_watchdog_device(mconfig, tag, owner, clock)
{
set_ids(0x808625ab, 0x02, 0x088000, subdevice_id);
}
i6300esb_watchdog_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:

5
src/devices/machine/i82371sb.cpp
View File

@ -135,8 +135,8 @@ MACHINE_CONFIG_START(i82371sb_isa_device::device_add_mconfig)
MACHINE_CONFIG_END
i82371sb_isa_device::i82371sb_isa_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: pci_device(mconfig, I82371SB_ISA, tag, owner, clock),
i82371sb_isa_device::i82371sb_isa_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
pci_device(mconfig, I82371SB_ISA, tag, owner, clock),
m_smi_callback(*this),
m_boot_state_hook(*this),
m_maincpu(*this, ":maincpu"),
@ -149,6 +149,7 @@ i82371sb_isa_device::i82371sb_isa_device(const machine_config &mconfig, const ch
m_speaker(*this, "speaker"),
m_at_spkrdata(0), m_pit_out2(0), m_dma_channel(0), m_cur_eop(false), m_dma_high_byte(0), m_at_speaker(0), m_refresh(false), m_channel_check(0), m_nmi_enabled(0)
{
set_ids(0x80867000, 0x03, 0x060100, 0x00000000);
}
void i82371sb_isa_device::device_start()

4
src/devices/machine/i82371sb.h
View File

@ -1,7 +1,6 @@
// license:BSD-3-Clause
// copyright-holders:Olivier Galibert
// Intel i82371sb southbridge (PIIX3)
#ifndef MAME_MACHINE_I82371SB_H
#define MAME_MACHINE_I82371SB_H
@ -24,9 +23,6 @@
#include "machine/am9517a.h"
#define MCFG_I82371SB_ISA_ADD(_tag) \
MCFG_PCI_DEVICE_ADD(_tag, I82371SB_ISA, 0x80867000, 0x03, 0x060100, 0x00000000)
#define MCFG_I82371SB_SMI_CB(_devcb) \
devcb = &downcast<i82371sb_isa_device &>(*device).set_smi_callback(DEVCB_##_devcb);

7
src/devices/machine/i82439hx.cpp
View File

@ -25,14 +25,10 @@ void i82439hx_host_device::config_map(address_map &map)
i82439hx_host_device::i82439hx_host_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: pci_host_device(mconfig, I82439HX, tag, owner, clock)
, cpu(*this, finder_base::DUMMY_TAG)
{
}
void i82439hx_host_device::set_cpu_tag(const char *_cpu_tag)
{
cpu_tag = _cpu_tag;
}
void i82439hx_host_device::set_ram_size(int _ram_size)
{
ram_size = _ram_size;
@ -41,7 +37,6 @@ void i82439hx_host_device::set_ram_size(int _ram_size)
void i82439hx_host_device::device_start()
{
pci_host_device::device_start();
cpu = machine().device<cpu_device>(cpu_tag);
memory_space = &cpu->space(AS_PROGRAM);
io_space = &cpu->space(AS_IO);

18
src/devices/machine/i82439hx.h
View File

@ -9,16 +9,19 @@
#include "pci.h"
#define MCFG_I82439HX_ADD(_tag, _cpu_tag, _ram_size) \
MCFG_PCI_HOST_ADD(_tag, I82439HX, 0x80861250, 0x03, 0x00000000) \
downcast<i82439hx_host_device *>(device)->set_cpu_tag(_cpu_tag); \
downcast<i82439hx_host_device *>(device)->set_ram_size(_ram_size);
class i82439hx_host_device : public pci_host_device {
public:
template <typename T>
i82439hx_host_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&cpu_tag, int ram_size)
: i82439hx_host_device(mconfig, tag, owner, clock)
{
set_ids_host(0x80861250, 0x03, 0x00000000);
set_cpu_tag(std::forward<T>(cpu_tag));
set_ram_size(ram_size);
}
i82439hx_host_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
void set_cpu_tag(const char *tag);
template <typename T> void set_cpu_tag(T &&tag) { cpu.set_tag(std::forward<T>(tag)); }
void set_ram_size(int ram_size);
DECLARE_WRITE_LINE_MEMBER(smi_act_w);
@ -35,9 +38,8 @@ protected:
virtual void config_map(address_map &map) override;
private:
const char *cpu_tag;
int ram_size;
cpu_device *cpu;
required_device<device_memory_interface> cpu;
std::vector<uint32_t> ram;
uint8_t pcon, cc, dramec, dramc, dramt;

11
src/devices/machine/i82439tx.cpp
View File

@ -3,7 +3,7 @@
#include "emu.h"
#include "i82439tx.h"
DEFINE_DEVICE_TYPE(I82439TX_NEW, i82439tx_host_device, "i82439tx_new", "Intel 82439TX northbridge")
DEFINE_DEVICE_TYPE(I82439TX, i82439tx_host_device, "i82439tx", "Intel 82439TX northbridge")
void i82439tx_host_device::config_map(address_map &map)
{
@ -24,15 +24,11 @@ void i82439tx_host_device::config_map(address_map &map)
}
i82439tx_host_device::i82439tx_host_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: pci_host_device(mconfig, I82439TX_NEW, tag, owner, clock)
: pci_host_device(mconfig, I82439TX, tag, owner, clock)
, cpu(*this, finder_base::DUMMY_TAG)
{
}
void i82439tx_host_device::set_cpu_tag(const char *_cpu_tag)
{
cpu_tag = _cpu_tag;
}
void i82439tx_host_device::set_ram_size(int _ram_size)
{
ram_size = _ram_size;
@ -41,7 +37,6 @@ void i82439tx_host_device::set_ram_size(int _ram_size)
void i82439tx_host_device::device_start()
{
pci_host_device::device_start();
cpu = machine().device<cpu_device>(cpu_tag);
memory_space = &cpu->space(AS_PROGRAM);
io_space = &cpu->space(AS_IO);

20
src/devices/machine/i82439tx.h
View File

@ -9,16 +9,19 @@
#include "pci.h"
#define MCFG_I82439TX_ADD(_tag, _cpu_tag, _ram_size) \
MCFG_PCI_HOST_ADD(_tag, I82439TX_NEW, 0x80867100, 0x03, 0x00000000) \
downcast<i82439tx_host_device *>(device)->set_cpu_tag(_cpu_tag); \
downcast<i82439tx_host_device *>(device)->set_ram_size(_ram_size);
class i82439tx_host_device : public pci_host_device {
public:
template <typename T>
i82439tx_host_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&cpu_tag, int ram_size)
: i82439tx_host_device(mconfig, tag, owner, clock)
{
set_ids_host(0x80867100, 0x03, 0x00000000);
set_cpu_tag(std::forward<T>(cpu_tag));
set_ram_size(ram_size);
}
i82439tx_host_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
void set_cpu_tag(const char *tag);
template <typename T> void set_cpu_tag(T &&tag) { cpu.set_tag(std::forward<T>(tag)); }
void set_ram_size(int ram_size);
protected:
@ -33,9 +36,8 @@ protected:
virtual void config_map(address_map &map) override;
private:
const char *cpu_tag;
int ram_size;
cpu_device *cpu;
required_device<device_memory_interface> cpu;
std::vector<uint32_t> ram;
uint8_t pcon, cc, dramec, dramc, dramt;
@ -69,6 +71,6 @@ private:
DECLARE_READ8_MEMBER (errsyn_r);
};
DECLARE_DEVICE_TYPE(I82439TX_NEW, i82439tx_host_device)
DECLARE_DEVICE_TYPE(I82439TX, i82439tx_host_device)
#endif // MAME_MACHINE_I82439TX_H

8
src/devices/machine/i82541.h
View File

@ -7,11 +7,13 @@
#include "pci.h"
#define MCFG_I82541PI_ADD(_tag, _subdevice_id) \
MCFG_PCI_DEVICE_ADD(_tag, I82541, 0x8086107c, 0x05, 0x020000, _subdevice_id)
class i82541_device : public pci_device {
public:
i82541_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, uint32_t subdevice_id)
: i82541_device(mconfig, tag, owner, clock)
{
set_ids(0x8086107c, 0x05, 0x020000, subdevice_id);
}
i82541_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:

8
src/devices/machine/i82875p.cpp
View File

@ -45,14 +45,10 @@ void i82875p_host_device::config_map(address_map &map)
i82875p_host_device::i82875p_host_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: pci_host_device(mconfig, I82875P_HOST, tag, owner, clock)
, cpu(*this, finder_base::DUMMY_TAG)
{
}
void i82875p_host_device::set_cpu_tag(const char *_cpu_tag)
{
cpu_tag = _cpu_tag;
}
void i82875p_host_device::set_ram_size(int _ram_size)
{
ram_size = _ram_size;
@ -66,7 +62,6 @@ READ8_MEMBER(i82875p_host_device::capptr_r)
void i82875p_host_device::device_start()
{
pci_host_device::device_start();
cpu = machine().device<cpu_device>(cpu_tag);
memory_space = &cpu->space(AS_PROGRAM);
io_space = &cpu->space(AS_IO);
@ -431,6 +426,7 @@ void i82875p_host_device::map_extra(uint64_t memory_window_start, uint64_t memor
i82875p_agp_device::i82875p_agp_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: agp_bridge_device(mconfig, I82875P_AGP, tag, owner, clock)
{
set_ids_bridge(0x80862579, 0x02);
}
void i82875p_agp_device::device_start()

30
src/devices/machine/i82875p.h
View File

@ -9,22 +9,20 @@
#include "pci.h"
#define MCFG_I82875P_HOST_ADD(_tag, _subdevice_id, _cpu_tag, _ram_size) \
MCFG_PCI_HOST_ADD(_tag, I82875P_HOST, 0x80862578, 0x02, _subdevice_id) \
downcast<i82875p_host_device *>(device)->set_cpu_tag(_cpu_tag); \
downcast<i82875p_host_device *>(device)->set_ram_size(_ram_size);
#define MCFG_I82875P_AGP_ADD(_tag) \
MCFG_AGP_BRIDGE_ADD(_tag, I82875P_AGP, 0x80862579, 0x02)
#define MCFG_I82875P_OVERFLOW_ADD(_tag, _subdevice_id) \
MCFG_PCI_DEVICE_ADD(_tag, I82875P_OVERFLOW, 0x8086257e, 0x02, 0x088000, _subdevice_id)
class i82875p_host_device : public pci_host_device {
public:
template <typename T>
i82875p_host_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, uint32_t subdevice_id, T &&cpu_tag, int ram_size)
: i82875p_host_device(mconfig, tag, owner, clock)
{
set_ids_host(0x80862578, 0x02, subdevice_id);
set_cpu_tag(std::forward<T>(cpu_tag));
set_ram_size(ram_size);
}
i82875p_host_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
void set_cpu_tag(const char *tag);
template <typename T> void set_cpu_tag(T &&tag) { cpu.set_tag(std::forward<T>(tag)); }
void set_ram_size(int ram_size);
virtual DECLARE_READ8_MEMBER(capptr_r) override;
@ -43,9 +41,8 @@ protected:
private:
void agp_translation_map(address_map &map);
const char *cpu_tag;
int ram_size;
cpu_device *cpu;
required_device<device_memory_interface> cpu;
std::vector<uint32_t> ram;
uint8_t agpm, fpllcont, pam[8], smram, esmramc;
@ -109,6 +106,11 @@ protected:
class i82875p_overflow_device : public pci_device {
public:
i82875p_overflow_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, uint32_t subdevice_id)
: i82875p_overflow_device(mconfig, tag, owner, clock)
{
set_ids(0x8086257e, 0x02, 0x088000, subdevice_id);
}
i82875p_overflow_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
private:

3
src/devices/machine/lpc-acpi.h
View File

@ -7,9 +7,6 @@
#include "lpc.h"
#define MCFG_LPC_ACPI_ADD(_tag) \
MCFG_DEVICE_ADD(_tag, LPC_ACPI, 0)
class lpc_acpi_device : public lpc_device {
public:
lpc_acpi_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);

3
src/devices/machine/lpc-pit.h
View File

@ -7,9 +7,6 @@
#include "lpc.h"
#define MCFG_LPC_PIT_ADD(_tag) \
MCFG_DEVICE_ADD(_tag, LPC_PIT, 0)
class lpc_pit_device : public lpc_device {
public:
lpc_pit_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);

3
src/devices/machine/lpc-rtc.h
View File

@ -7,9 +7,6 @@
#include "lpc.h"
#define MCFG_LPC_RTC_ADD(_tag) \
MCFG_DEVICE_ADD(_tag, LPC_RTC, 0)
class lpc_rtc_device : public lpc_device {
public:
lpc_rtc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);

8
src/devices/machine/pci-apic.h
View File

@ -7,11 +7,13 @@
#include "pci.h"
#define MCFG_APIC_ADD(_tag, _main_id, _revision, _subdevice_id) \
MCFG_PCI_DEVICE_ADD(_tag, APIC, _main_id, _revision, 0x0c0320, _subdevice_id)
class apic_device : public pci_device {
public:
apic_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, uint32_t main_id, uint32_t revision, uint32_t subdevice_id)
: apic_device(mconfig, tag, owner, clock)
{
set_ids(main_id, revision, 0x080010, subdevice_id);
}
apic_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:

20
src/devices/machine/pci-ide.cpp
View File

@ -5,11 +5,10 @@
DEFINE_DEVICE_TYPE(IDE_PCI, ide_pci_device, "ide_pci", "PCI IDE interface")
ide_pci_device::ide_pci_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: pci_device(mconfig, IDE_PCI, tag, owner, clock),
ide_pci_device::ide_pci_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
pci_device(mconfig, IDE_PCI, tag, owner, clock),
m_ide(*this, "ide"),
m_ide2(*this, "ide2"),
m_irq_num(-1),
m_irq_handler(*this),
m_legacy_top(0x000),
m_pif(0x8a)
@ -64,17 +63,8 @@ MACHINE_CONFIG_START(ide_pci_device::device_add_mconfig)
MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(":pci:00.0", AS_DATA)
MACHINE_CONFIG_END
void ide_pci_device::set_irq_info(const char *tag, const int irq_num)
{
m_cpu_tag = tag;
m_irq_num = irq_num;
}
void ide_pci_device::device_start()
{
if (m_irq_num != -1)
m_cpu = machine().device<cpu_device>(m_cpu_tag);
pci_device::device_start();
add_map(8, M_IO, FUNC(ide_pci_device::chan1_data_command_map));
@ -151,10 +141,6 @@ WRITE32_MEMBER(ide_pci_device::ide2_write_cs1)
WRITE_LINE_MEMBER(ide_pci_device::ide_interrupt)
{
// Assert/Clear the interrupt if the irq num is set.
if (m_irq_num != -1) {
m_cpu->set_input_line(m_irq_num, state);
}
// Call the callback
m_irq_handler(state);
@ -166,7 +152,7 @@ WRITE_LINE_MEMBER(ide_pci_device::ide_interrupt)
m_config_data[0x10 / 4] &= ~0x4;
}
if (0)
logerror("%s:ide_interrupt %i set to %i\n", machine().describe_context(), m_irq_num, state);
logerror("%s:ide_interrupt set to %i\n", machine().describe_context(), state);
}
WRITE8_MEMBER(ide_pci_device::prog_if_w)

20
src/devices/machine/pci-ide.h
View File

@ -19,29 +19,26 @@ TODO:
#include "pci.h"
#include "idectrl.h"
#define MCFG_IDE_PCI_ADD(_tag, _main_id, _revision, _subdevice_id) \
MCFG_PCI_DEVICE_ADD(_tag, IDE_PCI, _main_id, _revision, 0x01018a, _subdevice_id)
// Setting this to a value other than -1 will cause the ide_pci_device to assert/clear the cpu interrupt directly.
#define MCFG_IDE_PCI_IRQ_ADD(_cpu_tag, _irq_num) \
downcast<ide_pci_device *>(device)->set_irq_info(_cpu_tag, _irq_num);
#define MCFG_IDE_PCI_IRQ_HANDLER(_devcb) \
devcb = &downcast<ide_pci_device &>(*device).set_irq_handler(DEVCB_##_devcb);
// This will set the top 12 bits for address decoding in legacy mode. Needed for seattle driver.
#define MCFG_IDE_PCI_SET_LEGACY_TOP(_val) \
downcast<ide_pci_device *>(device)->set_legacy_top(_val);
downcast<ide_pci_device &>(*device).set_legacy_top(_val);
// Sets the default Programming Interface (PIF) register
#define MCFG_IDE_PCI_SET_PIF(_val) \
downcast<ide_pci_device *>(device)->set_pif(_val);
downcast<ide_pci_device &>(*device).set_pif(_val);
class ide_pci_device : public pci_device {
public:
ide_pci_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, uint32_t main_id, uint32_t revision, uint32_t subdevice_id)
: ide_pci_device(mconfig, tag, owner, clock)
{
set_ids(main_id, revision, 0x01018a, subdevice_id);
}
ide_pci_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
void set_irq_info(const char *tag, const int irq_num);
template <class Object> devcb_base &set_irq_handler(Object &&cb) { return m_irq_handler.set_callback(std::forward<Object>(cb)); }
void set_legacy_top(int val) { m_legacy_top = val & 0xfff; };
void set_pif(int val) { m_pif = val & 0xff; };
@ -71,9 +68,6 @@ private:
required_device<bus_master_ide_controller_device> m_ide;
required_device<bus_master_ide_controller_device> m_ide2;
const char *m_cpu_tag;
cpu_device *m_cpu;
int m_irq_num;
devcb_write_line m_irq_handler;
uint32_t pci_bar[6];
// Bits 31-20 for legacy mode hack

8
src/devices/machine/pci-sata.h
View File

@ -7,11 +7,13 @@
#include "pci.h"
#define MCFG_SATA_ADD(_tag, _main_id, _revision, _subdevice_id) \
MCFG_PCI_DEVICE_ADD(_tag, SATA, _main_id, _revision, 0x01018a, _subdevice_id)
class sata_device : public pci_device {
public:
sata_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, uint32_t main_id, uint32_t revision, uint32_t subdevice_id)
: sata_device(mconfig, tag, owner, clock)
{
set_ids(main_id, revision, 0x01018a, subdevice_id);
}
sata_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:

8
src/devices/machine/pci-smbus.h
View File

@ -5,11 +5,13 @@
#include "pci.h"
#define MCFG_SMBUS_ADD(_tag, _main_id, _revision, _subdevice_id) \
MCFG_PCI_DEVICE_ADD(_tag, SMBUS, _main_id, _revision, 0x0c0500, _subdevice_id)
class smbus_device : public pci_device {
public:
smbus_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, uint32_t main_id, uint32_t revision, uint32_t subdevice_id)
: smbus_device(mconfig, tag, owner, clock)
{
set_ids(main_id, revision, 0x0c0500, subdevice_id);
}
smbus_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:

24
src/devices/machine/pci-usb.h
View File

@ -7,17 +7,13 @@
#include "pci.h"
#define MCFG_USB_OHCI_ADD(_tag, _main_id, _revision, _subdevice_id) \
MCFG_PCI_DEVICE_ADD(_tag, USB_OHCI, _main_id, _revision, 0x0c0310, _subdevice_id)
#define MCFG_USB_UHCI_ADD(_tag, _main_id, _revision, _subdevice_id) \
MCFG_PCI_DEVICE_ADD(_tag, USB_UHCI, _main_id, _revision, 0x0c0300, _subdevice_id)
#define MCFG_USB_EHCI_ADD(_tag, _main_id, _revision, _subdevice_id) \
MCFG_PCI_DEVICE_ADD(_tag, USB_EHCI, _main_id, _revision, 0x0c0320, _subdevice_id)
class usb_ohci_device : public pci_device {
public:
usb_ohci_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, uint32_t main_id, uint32_t revision, uint32_t subdevice_id)
: usb_ohci_device(mconfig, tag, owner, clock)
{
set_ids(main_id, revision, 0x0c0310, subdevice_id);
}
usb_ohci_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
@ -30,6 +26,11 @@ private:
class usb_uhci_device : public pci_device {
public:
usb_uhci_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, uint32_t main_id, uint32_t revision, uint32_t subdevice_id)
: usb_uhci_device(mconfig, tag, owner, clock)
{
set_ids(main_id, revision, 0x0c0300, subdevice_id);
}
usb_uhci_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
@ -42,6 +43,11 @@ private:
class usb_ehci_device : public pci_device {
public:
usb_ehci_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, uint32_t main_id, uint32_t revision, uint32_t subdevice_id)
: usb_ehci_device(mconfig, tag, owner, clock)
{
set_ids(main_id, revision, 0x0c0320, subdevice_id);
}
usb_ehci_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:

27
src/devices/machine/pci.h
View File

@ -6,25 +6,6 @@
#pragma once
#define MCFG_PCI_ROOT_ADD(_tag) \
MCFG_DEVICE_ADD(_tag, PCI_ROOT, 0)
#define MCFG_PCI_DEVICE_ADD(_tag, _type, _main_id, _revision, _pclass, _subsystem_id) \
MCFG_DEVICE_ADD(_tag, _type, 0) \
downcast<pci_device *>(device)->set_ids(_main_id, _revision, _pclass, _subsystem_id);
#define MCFG_AGP_DEVICE_ADD(_tag, _type, _main_id, _revision, _subsystem_id) \
MCFG_PCI_DEVICE_ADD(_tag, _type, _main_id, _revision, 0x030000, _subsystem_id)
#define MCFG_PCI_HOST_ADD(_tag, _type, _main_id, _revision, _subsystem_id) \
MCFG_PCI_DEVICE_ADD(_tag, _type, _main_id, _revision, 0x060000, _subsystem_id)
#define MCFG_PCI_BRIDGE_ADD(_tag, _main_id, _revision) \
MCFG_PCI_DEVICE_ADD(_tag, PCI_BRIDGE, _main_id, _revision, 0x060400, 0x00000000)
#define MCFG_AGP_BRIDGE_ADD(_tag, _type, _main_id, _revision) \
MCFG_PCI_DEVICE_ADD(_tag, _type, _main_id, _revision, 0x060400, 0x00000000)
class pci_device : public device_t {
public:
typedef delegate<void ()> mapper_cb;
@ -32,6 +13,9 @@ public:
mapper_cb remap_cb, remap_config_cb;
void set_ids(uint32_t main_id, uint8_t revision, uint32_t pclass, uint32_t subsystem_id);
void set_ids_host(uint32_t main_id, uint32_t revision, uint64_t subsystem_id) { set_ids(main_id, revision, 0x060000, subsystem_id); }
void set_ids_bridge(uint32_t main_id, uint32_t revision) { set_ids(main_id, revision, 0x060400, 0x00000000); }
void set_ids_agp(uint64_t main_id, uint32_t revision, uint32_t subsystem_id) { set_ids(main_id, revision, 0x030000, subsystem_id); }
void set_multifunction_device(bool enable);
virtual void set_remap_cb(mapper_cb _remap_cb);
@ -156,6 +140,11 @@ protected:
class pci_bridge_device : public pci_device, public device_memory_interface {
public:
pci_bridge_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, uint32_t main_id, uint32_t revision)
: pci_bridge_device(mconfig, tag, owner, clock)
{
set_ids_bridge(main_id, revision);
}
pci_bridge_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
virtual void set_remap_cb(mapper_cb _remap_cb) override;

5
src/devices/machine/pci9050.cpp
View File

@ -40,9 +40,10 @@ void pci9050_device::map(address_map &map)
}
pci9050_device::pci9050_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: pci_device(mconfig, PCI9050, tag, owner, clock),
m_user_input_handler(*this), m_user_output_handler(*this)
: pci_device(mconfig, PCI9050, tag, owner, clock)
, m_user_input_handler(*this), m_user_output_handler(*this)
{
set_ids(0x10b59050, 0x01, 0x06800000, 0x10b59050);
for(int i=0; i<4; i++) {
m_devices[i] = nullptr;
m_names[i] = nullptr;

3
src/devices/machine/pci9050.h
View File

@ -15,9 +15,6 @@
#include "machine/pci.h"
#define MCFG_PCI9050_ADD(_tag) \
MCFG_PCI_DEVICE_ADD(_tag, PCI9050, 0x10b59050, 0x01, 0x06800000, 0x10b59050)
#define MCFG_PCI9050_SET_MAP(id, map) \
downcast<pci9050_device *>(device)->set_map(id, address_map_constructor(&map, #map, this), this);

15
src/devices/machine/vrc4373.cpp
View File

@ -95,12 +95,13 @@ void vrc4373_device::target2_map(address_map &map)
}
vrc4373_device::vrc4373_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: pci_host_device(mconfig, VRC4373, tag, owner, clock),
m_cpu_space(nullptr), m_irq_cb(*this), m_cpu(nullptr), cpu_tag(nullptr), m_ram_size(0x0), m_simm0_size(0x0),
m_mem_config("memory_space", ENDIANNESS_LITTLE, 32, 32),
m_io_config("io_space", ENDIANNESS_LITTLE, 32, 32), m_pci1_laddr(0), m_pci2_laddr(0), m_pci_io_laddr(0), m_target1_laddr(0), m_target2_laddr(0),
m_romRegion(*this, "rom")
: pci_host_device(mconfig, VRC4373, tag, owner, clock)
, m_cpu_space(nullptr), m_irq_cb(*this), m_cpu(*this, finder_base::DUMMY_TAG), m_ram_size(0x0), m_simm0_size(0x0)
, m_mem_config("memory_space", ENDIANNESS_LITTLE, 32, 32)
, m_io_config("io_space", ENDIANNESS_LITTLE, 32, 32), m_pci1_laddr(0), m_pci2_laddr(0), m_pci_io_laddr(0), m_target1_laddr(0), m_target2_laddr(0)
, m_romRegion(*this, "rom")
{
set_ids_host(0x1033005B, 0x00, 0x00000000);
}
device_memory_interface::space_config_vector vrc4373_device::memory_space_config() const
@ -114,13 +115,13 @@ device_memory_interface::space_config_vector vrc4373_device::memory_space_config
void vrc4373_device::device_start()
{
pci_host_device::device_start();
m_cpu = machine().device<mips3_device>(cpu_tag);
m_cpu_space = &m_cpu->space(AS_PCI_CONFIG);
memory_space = &space(AS_PCI_MEM);
io_space = &space(AS_PCI_IO);
is_multifunction_device = false;
memset(m_cpu_regs, 0, sizeof(m_cpu_regs));
std::fill(std::begin(m_cpu_regs), std::end(m_cpu_regs), 0);
memory_window_start = 0;
memory_window_end = 0xffffffff;

24
src/devices/machine/vrc4373.h
View File

@ -10,15 +10,11 @@
#include "pci.h"
#include "cpu/mips/mips3.h"
#define MCFG_VRC4373_ADD(_tag, _cpu_tag) \
MCFG_PCI_HOST_ADD(_tag, VRC4373, 0x1033005B, 0x00, 0x00000000) \
downcast<vrc4373_device *>(device)->set_cpu_tag(_cpu_tag);
#define MCFG_VRC4373_SET_RAM(_size) \
downcast<vrc4373_device *>(device)->set_ram_size(_size);
downcast<vrc4373_device &>(*device).set_ram_size(_size);
#define MCFG_VRC4373_SET_SIMM0(_size) \
downcast<vrc4373_device *>(device)->set_simm0_size(_size);
downcast<vrc4373_device &>(*device).set_simm0_size(_size);
#define MCFG_VRC4373_IRQ_CB(_devcb) \
devcb = &ide_pci_device::set_irq_cb(*device, DEVCB_##_devcb);
@ -26,6 +22,13 @@
class vrc4373_device : public pci_host_device {
public:
template <typename T>
vrc4373_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&cpu_tag)
: vrc4373_device(mconfig, tag, owner, clock)
{
set_cpu_tag(std::forward<T>(cpu_tag));
}
vrc4373_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
virtual void reset_all_mappings() override;
@ -34,9 +37,9 @@ public:
virtual void device_post_load() override;
template <class Object> devcb_base &set_irq_cb(Object &&cb) { return m_irq_cb.set_callback(std::forward<Object>(cb)); }
void set_cpu_tag(const char *tag) { cpu_tag = tag; }
void set_ram_size(const int size) { m_ram_size = size; };
void set_simm0_size(const int size) { m_simm0_size = size; };
template <typename T> void set_cpu_tag(T &&tag) { m_cpu.set_tag(std::forward<T>(tag)); }
void set_ram_size(int size) { m_ram_size = size; };
void set_simm0_size(int size) { m_simm0_size = size; };
virtual void config_map(address_map &map) override;
@ -86,8 +89,7 @@ private:
devcb_write_line m_irq_cb;
mips3_device *m_cpu;
const char *cpu_tag;
required_device<mips3_device> m_cpu;
int m_ram_size;
int m_simm0_size;

16
src/devices/machine/vrc5074.cpp
View File

@ -156,15 +156,17 @@ MACHINE_CONFIG_START(vrc5074_device::device_add_mconfig)
MCFG_RS232_CTS_HANDLER(WRITELINE("uart", ns16550_device, cts_w))
MACHINE_CONFIG_END
vrc5074_device::vrc5074_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: pci_host_device(mconfig, VRC5074, tag, owner, clock),
vrc5074_device::vrc5074_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
pci_host_device(mconfig, VRC5074, tag, owner, clock),
m_uart(*this, "uart"),
m_cpu_space(nullptr), m_cpu(nullptr), cpu_tag(nullptr),
m_cpu_space(nullptr), m_cpu(*this, finder_base::DUMMY_TAG),
m_mem_config("memory_space", ENDIANNESS_LITTLE, 32, 32),
m_io_config("io_space", ENDIANNESS_LITTLE, 32, 32),
m_romRegion(*this, "rom"),
m_updateRegion(*this, "update")
{
set_ids_host(0x1033005a, 0x04, 0x00000000);
for (int i = 0; i < 2; i++)
m_sdram_size[i] = 0x0;
@ -192,7 +194,6 @@ device_memory_interface::space_config_vector vrc5074_device::memory_space_config
void vrc5074_device::device_start()
{
pci_host_device::device_start();
m_cpu = machine().device<mips3_device>(cpu_tag);
m_cpu_space = &m_cpu->space(AS_PROGRAM);
memory_space = &space(AS_DATA);
io_space = &space(AS_IO);
@ -382,13 +383,6 @@ void vrc5074_device::reset_all_mappings()
pci_device::reset_all_mappings();
}
void vrc5074_device::set_cpu_tag(const char *_cpu_tag)
{
if (LOG_NILE)
logerror("%s: set_cpu_tag\n", tag());
cpu_tag = _cpu_tag;
}
READ32_MEMBER(vrc5074_device::sdram_addr_r)
{
return 0;

22
src/devices/machine/vrc5074.h
View File

@ -12,18 +12,21 @@
#include "machine/ins8250.h"
#include "bus/rs232/rs232.h"
#define MCFG_VRC5074_ADD(_tag, _cpu_tag) \
MCFG_PCI_HOST_ADD(_tag, VRC5074, 0x1033005a, 0x04, 0x00000000) \
downcast<vrc5074_device *>(device)->set_cpu_tag(_cpu_tag);
#define MCFG_VRC5074_SET_SDRAM(_index, _size) \
downcast<vrc5074_device *>(device)->set_sdram_size(_index, _size);
downcast<vrc5074_device &>(*device).set_sdram_size(_index, _size);
#define MCFG_VRC5074_SET_CS(_cs_num, _map) \
downcast<vrc5074_device *>(device)->set_map(_cs_num, address_map_constructor(&_map, #_map, this), this);
downcast<vrc5074_device &>(*device).set_map(_cs_num, address_map_constructor(&_map, #_map, this), this);
class vrc5074_device : public pci_host_device {
public:
template <typename T>
vrc5074_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&cpu_tag)
: vrc5074_device(mconfig, tag, owner, clock)
{
set_cpu_tag(std::forward<T>(cpu_tag));
}
vrc5074_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
required_device<ns16550_device> m_uart;
@ -33,8 +36,8 @@ public:
uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space) override;
virtual void device_post_load() override;
void set_cpu_tag(const char *tag);
void set_sdram_size(const int index, const int size) { m_sdram_size[index] = size; };
template <typename T> void set_cpu_tag(T &&tag) { m_cpu.set_tag(std::forward<T>(tag)); }
void set_sdram_size(int index, int size) { m_sdram_size[index] = size; };
void set_map(int id, const address_map_constructor &map, device_t *device);
@ -86,8 +89,7 @@ private:
AS_PCI_IO = 2
};
mips3_device *m_cpu;
const char *cpu_tag;
required_device<mips3_device> m_cpu;
int m_sdram_size[2];
address_space_config m_mem_config, m_io_config;

26
src/devices/sound/es1373.cpp
View File

@ -84,17 +84,17 @@ void es1373_device::map(address_map &map)
}
es1373_device::es1373_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: pci_device(mconfig, ES1373, tag, owner, clock),
device_sound_interface(mconfig, *this), m_stream(nullptr),
m_eslog(nullptr), m_tempCount(0), m_timer(nullptr), m_memory_space(nullptr), m_cpu_tag(nullptr), m_cpu(nullptr),
m_irq_num(-1)
: pci_device(mconfig, ES1373, tag, owner, clock)
, device_sound_interface(mconfig, *this), m_stream(nullptr)
, m_eslog(nullptr), m_tempCount(0), m_timer(nullptr), m_memory_space(nullptr), m_irq_handler(*this)
{
set_ids(0x12741371, 0x04, 0x040100, 0x12741371);
}
void es1373_device::set_irq_info(const char *tag, const int irq_num)
void es1373_device::device_resolve_objects()
{
m_cpu_tag = tag;
m_irq_num = irq_num;
pci_device::device_resolve_objects();
m_irq_handler.resolve_safe();
}
//-------------------------------------------------
@ -115,7 +115,6 @@ void es1373_device::device_stop()
//-------------------------------------------------
void es1373_device::device_start()
{
m_cpu = machine().device<cpu_device>(m_cpu_tag);
pci_device::device_start();
add_map(0x40, M_IO, FUNC(es1373_device::map));
@ -169,11 +168,11 @@ void es1373_device::device_start()
save_item(NAME(m_adc.pci_addr));
save_item(NAME(m_adc.pci_count));
save_item(NAME(m_adc.pci_size));
machine().save().register_postload(save_prepost_delegate(FUNC(es1373_device::postload), this));
}
void es1373_device::postload()
void es1373_device::device_post_load()
{
pci_device::device_post_load();
remap_cb();
}
@ -285,10 +284,7 @@ void es1373_device::sound_stream_update(sound_stream &stream, stream_sample_t **
if (m_es_regs[ES_INT_CS_STATUS]&(ICSTATUS_DAC1_INT_MASK|ICSTATUS_DAC2_INT_MASK|ICSTATUS_ADC_INT_MASK)) {
m_es_regs[ES_INT_CS_STATUS] |= ICSTATUS_INTR_MASK;
// Assert interrupt
//m_cpu->set_input_line(ES_IRQ_NUM, ASSERT_LINE);
if (m_irq_num!=-1) {
m_cpu->set_input_line(m_irq_num, ASSERT_LINE);
}
m_irq_handler(1);
}
}
@ -536,7 +532,7 @@ WRITE32_MEMBER(es1373_device::reg_w)
if (!(m_es_regs[ES_INT_CS_STATUS]&(ICSTATUS_DAC1_INT_MASK|ICSTATUS_DAC2_INT_MASK|ICSTATUS_ADC_INT_MASK))) {
// Deassert interrupt
if (m_es_regs[ES_INT_CS_STATUS]&ICSTATUS_INTR_MASK && m_irq_num!=-1) {
m_cpu->set_input_line(m_irq_num, CLEAR_LINE);
m_irq_handler(0);
m_es_regs[ES_INT_CS_STATUS] &= ~ICSTATUS_INTR_MASK;
if (0 && LOG_ES_REG)
logerror("%s: es1373_device::reg_w Clearing interrupt\n", machine().describe_context());

17
src/devices/sound/es1373.h
View File

@ -1,7 +1,6 @@
// license:BSD-3-Clause
// copyright-holders:Ted Green
// Creative Labs Ensonic AudioPCI97 ES1373
#ifndef MAME_SOUND_ES1373_H
#define MAME_SOUND_ES1373_H
@ -9,12 +8,8 @@
#include "machine/pci.h"
// No interrupts
#define MCFG_ES1373_ADD(_tag) \
MCFG_PCI_DEVICE_ADD(_tag, ES1373, 0x12741371, 0x04, 0x040100, 0x12741371)
#define MCFG_ES1373_IRQ_ADD(_cpu_tag, _irq_num) \
downcast<es1373_device *>(device)->set_irq_info(_cpu_tag, _irq_num);
#define MCFG_ES1373_IRQ_HANDLER(cb) \
devcb = &downcast<es1373_device &>(*device).set_irq_handler(DEVCB_##cb);
class es1373_device : public pci_device, public device_sound_interface
{
@ -24,18 +19,19 @@ public:
virtual void map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space) override;
void set_irq_info(const char *tag, const int irq_num);
void postload(void);
template <typename T> devcb_base &set_irq_handler(T &&cb) { return m_irq_handler.set_callback(std::forward<T>(cb)); }
DECLARE_READ32_MEMBER (reg_r);
DECLARE_WRITE32_MEMBER(reg_w);
protected:
virtual void device_resolve_objects() override;
virtual void device_start() override;
virtual void device_stop() override;
virtual void device_reset() override;
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
virtual void device_add_mconfig(machine_config &config) override;
virtual void device_post_load() override;
virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples) override;
// Sound stream
@ -67,8 +63,7 @@ private:
uint32_t m_tempCount;
emu_timer *m_timer;
address_space *m_memory_space;
const char *m_cpu_tag;
cpu_device *m_cpu;
devcb_write_line m_irq_handler;
int m_irq_num;
void map(address_map &map);
uint16_t m_ac97_regs[0x80];

8
src/devices/sound/pci-ac97.h
View File

@ -7,11 +7,13 @@
#include "machine/pci.h"
#define MCFG_AC97_ADD(_tag, _main_id, _revision, _subdevice_id) \
MCFG_PCI_DEVICE_ADD(_tag, AC97, _main_id, _revision, 0x040300, _subdevice_id)
class ac97_device : public pci_device {
public:
ac97_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, uint32_t main_id, uint32_t revision, uint32_t subdevice_id)
: ac97_device(mconfig, tag, owner, clock)
{
set_ids(main_id, revision, 0x040300, subdevice_id);
}
ac97_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:

8
src/devices/sound/sb0400.h
View File

@ -7,11 +7,13 @@
#include "machine/pci.h"
#define MCFG_SB0400_ADD(_tag, _subdevice_id) \
MCFG_PCI_DEVICE_ADD(_tag, SB0400, 0x11020008, 0x00, 0x040100, _subdevice_id)
class sb0400_device : public pci_device {
public:
sb0400_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, uint32_t subdevice_id)
: sb0400_device(mconfig, tag, owner, clock)
{
set_ids(0x11020008, 0x00, 0x040100, subdevice_id);
}
sb0400_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:

8
src/devices/video/gf7600gs.h
View File

@ -7,11 +7,13 @@
#include "machine/pci.h"
#define MCFG_GEFORCE_7600GS_ADD(_tag, _subdevice_id) \
MCFG_AGP_DEVICE_ADD(_tag, GEFORCE_7600GS, 0x10de02e1, 0xa1, _subdevice_id)
class geforce_7600gs_device : public pci_device {
public:
geforce_7600gs_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, uint32_t subdevice_id)
: geforce_7600gs_device(mconfig, tag, owner, clock)
{
set_ids_agp(0x10de02e1, 0xa1, subdevice_id);
}
geforce_7600gs_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:

1
src/devices/video/mga2064w.cpp
View File

@ -8,6 +8,7 @@ DEFINE_DEVICE_TYPE(MGA2064W, mga2064w_device, "mga2064w", "Matrox Millennium")
mga2064w_device::mga2064w_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: pci_device(mconfig, MGA2064W, tag, owner, clock)
{
set_ids(0x102b0519, 0x01, 0x030000, 0x00000000);
}
void mga2064w_device::device_start()

3
src/devices/video/mga2064w.h
View File

@ -7,9 +7,6 @@
#include "machine/pci.h"
#define MCFG_MGA2064W_ADD(_tag) \
MCFG_PCI_DEVICE_ADD(_tag, MGA2064W, 0x102b0519, 0x01, 0x030000, 0x00000000)
class mga2064w_device : public pci_device {
public:
mga2064w_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);

46
src/mame/drivers/atlantis.cpp
View File

@ -806,15 +806,15 @@ DEVICE_INPUT_DEFAULTS_END
MACHINE_CONFIG_START(atlantis_state::mwskins)
/* basic machine hardware */
MCFG_DEVICE_ADD("maincpu", VR4310LE, 166666666) // clock is TRUSTED
MCFG_DEVICE_ADD(m_maincpu, VR4310LE, 166666666) // clock is TRUSTED
MCFG_MIPS3_ICACHE_SIZE(16384)
MCFG_MIPS3_DCACHE_SIZE(16384)
MCFG_MIPS3_SYSTEM_CLOCK(66666666)
MCFG_PCI_ROOT_ADD( ":pci")
MCFG_VRC4373_ADD( PCI_ID_NILE, ":maincpu")
MCFG_DEVICE_ADD(":pci", PCI_ROOT, 0)
MCFG_DEVICE_ADD(PCI_ID_NILE, VRC4373, 0, m_maincpu)
MCFG_VRC4373_SET_RAM(0x00800000)
MCFG_PCI9050_ADD( PCI_ID_9050)
MCFG_DEVICE_ADD(PCI_ID_9050, PCI9050, 0)
MCFG_PCI9050_SET_MAP(0, atlantis_state::map0)
MCFG_PCI9050_SET_MAP(1, atlantis_state::map1)
MCFG_PCI9050_SET_MAP(2, atlantis_state::map2)
@ -822,11 +822,11 @@ MACHINE_CONFIG_START(atlantis_state::mwskins)
MCFG_PCI9050_USER_OUTPUT_CALLBACK(WRITE32(*this, atlantis_state, user_io_output))
MCFG_PCI9050_USER_INPUT_CALLBACK(READ32(*this, atlantis_state, user_io_input))
MCFG_M48T37_ADD("rtc")
MCFG_M48T37_ADD(m_rtc)
MCFG_M48T37_RESET_HANDLER(WRITELINE(*this, atlantis_state, watchdog_reset))
MCFG_M48T37_IRQ_HANDLER(WRITELINE(*this, atlantis_state, watchdog_irq))
MCFG_IDE_PCI_ADD(PCI_ID_IDE, 0x10950646, 0x07, 0x0)
MCFG_DEVICE_ADD(m_ide, IDE_PCI, 0, 0x10950646, 0x07, 0x0)
MCFG_IDE_PCI_IRQ_HANDLER(WRITELINE(*this, atlantis_state, ide_irq))
// The pci-ide by default expects the system controller to be pci:00.0 so need to fix here
MCFG_DEVICE_MODIFY(PCI_ID_IDE":ide")
@ -835,7 +835,7 @@ MACHINE_CONFIG_START(atlantis_state::mwskins)
MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(PCI_ID_NILE, AS_DATA)
/* video hardware */
MCFG_DEVICE_ADD("zeus2", ZEUS2, ZEUS2_VIDEO_CLOCK)
MCFG_DEVICE_ADD(m_zeus, ZEUS2, ZEUS2_VIDEO_CLOCK)
MCFG_ZEUS2_FLOAT_MODE(1)
MCFG_ZEUS2_IRQ_CB(WRITELINE(*this, atlantis_state, zeus_irq))
MCFG_ZEUS2_VBLANK_CB(WRITELINE(*this, atlantis_state, vblank_irq))
@ -846,49 +846,49 @@ MACHINE_CONFIG_START(atlantis_state::mwskins)
MCFG_SCREEN_UPDATE_DEVICE("zeus2", zeus2_device, screen_update)
/* sound hardware */
MCFG_DEVICE_ADD("dcs", DCS2_AUDIO_DENVER, 0)
MCFG_DEVICE_ADD(m_dcs, DCS2_AUDIO_DENVER, 0)
MCFG_DCS2_AUDIO_DRAM_IN_MB(4)
MCFG_DCS2_AUDIO_POLLING_OFFSET(0xe33)
MCFG_DEVICE_ADD("ioasic", MIDWAY_IOASIC, 0)
MCFG_DEVICE_ADD(m_ioasic, MIDWAY_IOASIC, 0)
MCFG_MIDWAY_IOASIC_SHUFFLE(MIDWAY_IOASIC_STANDARD)
MCFG_MIDWAY_SERIAL_PIC2_YEAR_OFFS(80)
MCFG_MIDWAY_IOASIC_UPPER(342) // 325
MCFG_MIDWAY_IOASIC_IRQ_CALLBACK(WRITELINE(*this, atlantis_state, ioasic_irq))
MCFG_MIDWAY_IOASIC_AUTO_ACK(1)
if DEBUG_CONSOLE {
MCFG_MIDWAY_IOASIC_OUT_TX_CB(WRITE8("uart0", generic_terminal_device, write))
MCFG_DEVICE_ADD("uart0", GENERIC_TERMINAL, 0)
MCFG_MIDWAY_IOASIC_OUT_TX_CB(WRITE8(m_uart0, generic_terminal_device, write))
MCFG_DEVICE_ADD(m_uart0, GENERIC_TERMINAL, 0)
MCFG_GENERIC_TERMINAL_KEYBOARD_CB(DEVPUT("ioasic", midway_ioasic_device, serial_rx_w))
}
// TL16C552 UART
MCFG_DEVICE_ADD("uart1", NS16550, XTAL(24'000'000))
MCFG_DEVICE_ADD(m_uart1, NS16550, XTAL(24'000'000))
MCFG_INS8250_OUT_TX_CB(WRITELINE("com1", rs232_port_device, write_txd))
MCFG_INS8250_OUT_DTR_CB(WRITELINE("com1", rs232_port_device, write_dtr))
MCFG_INS8250_OUT_RTS_CB(WRITELINE("com1", rs232_port_device, write_rts))
MCFG_INS8250_OUT_INT_CB(WRITELINE(*this, atlantis_state, duart_irq_callback))
MCFG_DEVICE_ADD("uart2", NS16550, XTAL(24'000'000))
MCFG_DEVICE_ADD(m_uart2, NS16550, XTAL(24'000'000))
MCFG_INS8250_OUT_TX_CB(WRITELINE("com2", rs232_port_device, write_txd))
MCFG_INS8250_OUT_DTR_CB(WRITELINE("com2", rs232_port_device, write_dtr))
MCFG_INS8250_OUT_RTS_CB(WRITELINE("com2", rs232_port_device, write_rts))
MCFG_INS8250_OUT_INT_CB(WRITELINE(*this, atlantis_state, duart_irq_callback))
MCFG_DEVICE_ADD("com1", RS232_PORT, default_rs232_devices, nullptr)
MCFG_RS232_RXD_HANDLER(WRITELINE("uart1", ins8250_uart_device, rx_w))
MCFG_RS232_DCD_HANDLER(WRITELINE("uart1", ins8250_uart_device, dcd_w))
MCFG_RS232_DSR_HANDLER(WRITELINE("uart1", ins8250_uart_device, dsr_w))
MCFG_RS232_RI_HANDLER(WRITELINE("uart1", ins8250_uart_device, ri_w))
MCFG_RS232_CTS_HANDLER(WRITELINE("uart1", ins8250_uart_device, cts_w))
MCFG_RS232_RXD_HANDLER(WRITELINE(m_uart1, ins8250_uart_device, rx_w))
MCFG_RS232_DCD_HANDLER(WRITELINE(m_uart1, ins8250_uart_device, dcd_w))
MCFG_RS232_DSR_HANDLER(WRITELINE(m_uart1, ins8250_uart_device, dsr_w))
MCFG_RS232_RI_HANDLER(WRITELINE(m_uart1, ins8250_uart_device, ri_w))
MCFG_RS232_CTS_HANDLER(WRITELINE(m_uart1, ins8250_uart_device, cts_w))
//MCFG_SLOT_OPTION_DEVICE_INPUT_DEFAULTS("com1", mwskins_comm)
MCFG_DEVICE_ADD("com2", RS232_PORT, default_rs232_devices, nullptr)
MCFG_RS232_RXD_HANDLER(WRITELINE("uart2", ins8250_uart_device, rx_w))
MCFG_RS232_DCD_HANDLER(WRITELINE("uart2", ins8250_uart_device, dcd_w))
MCFG_RS232_DSR_HANDLER(WRITELINE("uart2", ins8250_uart_device, dsr_w))
MCFG_RS232_RI_HANDLER(WRITELINE("uart2", ins8250_uart_device, ri_w))
MCFG_RS232_CTS_HANDLER(WRITELINE("uart2", ins8250_uart_device, cts_w))
MCFG_RS232_RXD_HANDLER(WRITELINE(m_uart2, ins8250_uart_device, rx_w))
MCFG_RS232_DCD_HANDLER(WRITELINE(m_uart2, ins8250_uart_device, dcd_w))
MCFG_RS232_DSR_HANDLER(WRITELINE(m_uart2, ins8250_uart_device, dsr_w))
MCFG_RS232_RI_HANDLER(WRITELINE(m_uart2, ins8250_uart_device, ri_w))
MCFG_RS232_CTS_HANDLER(WRITELINE(m_uart2, ins8250_uart_device, cts_w))
MACHINE_CONFIG_END

2
src/mame/drivers/atpci.cpp
View File

@ -79,7 +79,7 @@ static void isa_internal_devices(device_slot_interface &device)
static void pci_devices(device_slot_interface &device)
{
device.option_add_internal("i82439tx", I82439TX);
device.option_add_internal("i82439tx", I82439TX_LEGACY);
device.option_add_internal("i82371ab", I82371AB);
device.option_add_internal("i82371sb", I82371SB);
}

24
src/mame/drivers/iteagle.cpp
View File

@ -119,8 +119,8 @@ class iteagle_state : public driver_device
{
public:
iteagle_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu")
: driver_device(mconfig, type, tag)
, m_maincpu(*this, "maincpu")
{}
required_device<mips3_device> m_maincpu;
@ -164,31 +164,31 @@ void iteagle_state::machine_reset()
MACHINE_CONFIG_START(iteagle_state::iteagle)
/* basic machine hardware */
MCFG_DEVICE_ADD("maincpu", VR4310LE, 166666666)
MCFG_DEVICE_ADD(m_maincpu, VR4310LE, 166666666)
MCFG_MIPS3_ICACHE_SIZE(16384)
MCFG_MIPS3_DCACHE_SIZE(8192)
MCFG_MIPS3_SYSTEM_CLOCK(66666667)
MCFG_PCI_ROOT_ADD( ":pci")
MCFG_VRC4373_ADD( PCI_ID_NILE, ":maincpu")
MCFG_DEVICE_ADD(":pci", PCI_ROOT, 0)
MCFG_DEVICE_ADD(PCI_ID_NILE, VRC4373, 0, m_maincpu)
MCFG_VRC4373_SET_RAM(0x00800000)
MCFG_VRC4373_SET_SIMM0(0x02000000)
MCFG_ITEAGLE_PERIPH_ADD( PCI_ID_PERIPH)
MCFG_IDE_PCI_ADD( PCI_ID_IDE, 0x1080C693, 0x00, 0x0)
MCFG_IDE_PCI_IRQ_ADD( ":maincpu", MIPS3_IRQ2)
MCFG_DEVICE_ADD( PCI_ID_PERIPH, ITEAGLE_PERIPH, 0)
MCFG_DEVICE_ADD( PCI_ID_IDE, IDE_PCI, 0, 0x1080C693, 0x00, 0x0)
MCFG_IDE_PCI_IRQ_HANDLER( INPUTLINE(m_maincpu, MIPS3_IRQ2))
MCFG_ITEAGLE_FPGA_ADD( PCI_ID_FPGA, ":maincpu", MIPS3_IRQ1, MIPS3_IRQ4)
MCFG_ES1373_ADD( PCI_ID_SOUND)
MCFG_DEVICE_ADD( PCI_ID_FPGA, ITEAGLE_FPGA, 0, "screen", m_maincpu, MIPS3_IRQ1, MIPS3_IRQ4)
MCFG_DEVICE_ADD( PCI_ID_SOUND, ES1373, 0)
MCFG_SOUND_ROUTE(0, PCI_ID_SOUND":lspeaker", 1.0)
MCFG_SOUND_ROUTE(1, PCI_ID_SOUND":rspeaker", 1.0)
MCFG_ES1373_IRQ_ADD( ":maincpu", MIPS3_IRQ3)
MCFG_ES1373_IRQ_HANDLER( INPUTLINE(m_maincpu, MIPS3_IRQ3))
MCFG_DEVICE_ADD(PCI_ID_VIDEO, VOODOO_3_PCI, 0, m_maincpu, "screen")
MCFG_VOODOO_PCI_FBMEM(16)
MCFG_DEVICE_MODIFY(PCI_ID_VIDEO":voodoo")
MCFG_VOODOO_VBLANK_CB(WRITELINE(PCI_ID_FPGA, iteagle_fpga_device, vblank_update))
MCFG_ITEAGLE_EEPROM_ADD( PCI_ID_EEPROM)
MCFG_DEVICE_ADD( PCI_ID_EEPROM, ITEAGLE_EEPROM, 0)
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)

48
src/mame/drivers/lindbergh.cpp
View File

@ -393,28 +393,28 @@ void lindbergh_state::machine_reset()
MACHINE_CONFIG_START(lindbergh_state::lindbergh)
MCFG_DEVICE_ADD("maincpu", PENTIUM4, 28000000U*5) /* Actually Celeron D at 2,8 GHz */
MCFG_PCI_ROOT_ADD( ":pci")
MCFG_I82875P_HOST_ADD( ":pci:00.0", 0x103382c0, ":maincpu", 512*1024*1024)
MCFG_I82875P_AGP_ADD( ":pci:01.0")
MCFG_GEFORCE_7600GS_ADD( ":pci:01.0:00.0", 0x10de02e1)
MCFG_I82875P_OVERFLOW_ADD( ":pci:06.0", 0x103382c0)
MCFG_PCI_BRIDGE_ADD( ":pci:1c.0", 0x808625ae, 0x02)
MCFG_I82541PI_ADD( ":pci:1c.0:00.0", 0x103382c0)
MCFG_USB_UHCI_ADD( ":pci:1d.0", 0x808625a9, 0x02, 0x103382c0)
MCFG_USB_UHCI_ADD( ":pci:1d.1", 0x808625aa, 0x02, 0x103382c0)
MCFG_I6300ESB_WATCHDOG_ADD( ":pci:1d.4", 0x103382c0)
MCFG_APIC_ADD( ":pci:1d.5", 0x808625ac, 0x02, 0x103382c0)
MCFG_USB_EHCI_ADD( ":pci:1d.7", 0x808625ad, 0x02, 0x103382c0)
MCFG_PCI_BRIDGE_ADD( ":pci:1e.0", 0x8086244e, 0x0a)
MCFG_SB0400_ADD( ":pci:1e.0:02.0", 0x11021101)
MCFG_SEGA_LINDBERGH_BASEBOARD_ADD(":pci:1e.0:03.0")
MCFG_I6300ESB_LPC_ADD( ":pci:1f.0")
MCFG_LPC_ACPI_ADD( ":pci:1f.0:acpi")
MCFG_LPC_RTC_ADD( ":pci:1f.0:rtc")
MCFG_LPC_PIT_ADD( ":pci:1f.0:pit")
MCFG_SATA_ADD( ":pci:1f.2", 0x808625a3, 0x02, 0x103382c0)
MCFG_SMBUS_ADD( ":pci:1f.3", 0x808625a4, 0x02, 0x103382c0)
MCFG_AC97_ADD( ":pci:1f.5", 0x808625a6, 0x02, 0x103382c0)
PCI_ROOT (config, ":pci", 0);
I82875P_HOST (config, ":pci:00.0", 0, 0x103382c0, "maincpu", 512*1024*1024);
I82875P_AGP (config, ":pci:01.0", 0);
GEFORCE_7600GS (config, ":pci:01.0:00.0", 0, 0x10de02e1);
I82875P_OVERFLOW (config, ":pci:06.0", 0, 0x103382c0);
PCI_BRIDGE (config, ":pci:1c.0", 0, 0x808625ae, 0x02);
I82541 (config, ":pci:1c.0:00.0", 0, 0x103382c0);
USB_UHCI (config, ":pci:1d.0", 0, 0x808625a9, 0x02, 0x103382c0);
USB_UHCI (config, ":pci:1d.1", 0, 0x808625aa, 0x02, 0x103382c0);
I6300ESB_WATCHDOG (config, ":pci:1d.4", 0, 0x103382c0);
APIC (config, ":pci:1d.5", 0, 0x808625ac, 0x02, 0x103382c0);
USB_EHCI (config, ":pci:1d.7", 0, 0x808625ad, 0x02, 0x103382c0);
PCI_BRIDGE (config, ":pci:1e.0", 0, 0x8086244e, 0x0a);
SB0400 (config, ":pci:1e.0:02.0", 0, 0x11021101);
SEGA_LINDBERGH_BASEBOARD(config, ":pci:1e.0:03.0", 0);
I6300ESB_LPC (config, ":pci:1f.0", 0);
LPC_ACPI (config, ":pci:1f.0:acpi", 0);
LPC_RTC (config, ":pci:1f.0:rtc", 0);
LPC_PIT (config, ":pci:1f.0:pit", 0);
SATA (config, ":pci:1f.2", 0, 0x808625a3, 0x02, 0x103382c0);
SMBUS (config, ":pci:1f.3", 0, 0x808625a4, 0x02, 0x103382c0);
AC97 (config, ":pci:1f.5", 0, 0x808625a6, 0x02, 0x103382c0);
MACHINE_CONFIG_END
#define LINDBERGH_BIOS \
@ -425,10 +425,10 @@ MACHINE_CONFIG_END
ROMX_LOAD("6.0.0009.bin", 0x00000, 0x100000, CRC(5ffdfbf8) SHA1(605bc4967b749b4e6d13fc2ebb845ba956a259a7), ROM_BIOS(2) ) \
ROM_SYSTEM_BIOS(2, "bios2", "6.0.0010") \
ROMX_LOAD("6.0.0010.bin", 0x00000, 0x100000, CRC(ea2bf888) SHA1(c9c5b6f0d4f4f36620939b15dd2f128a74347e37), ROM_BIOS(3) ) \
\
\
ROM_REGION(0x400000, ":pci:1e.0:03.0", 0) /* Baseboard MPC firmware */ \
ROM_LOAD("fpr-24370b.ic6", 0x000000, 0x400000, CRC(c3b021a4) SHA1(1b6938a50fe0e4ae813864649eb103838c399ac0)) \
\
\
ROM_REGION32_LE(0x10000, ":pci:01.0:00.0", 0) /* Geforce bios extension (custom for the card) */ \
ROM_LOAD("vid_bios.u504", 0x00000, 0x10000, CRC(f78d14d7) SHA1(f129787e487984edd23bf344f2e9500c85052275)) \
DISK_REGION("cf") \

20
src/mame/drivers/pcipc.cpp
View File

@ -488,13 +488,13 @@ MACHINE_CONFIG_START(pcipc_state::pcipc)
MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("pci:07.0:pic8259_master", pic8259_device, inta_cb)
MCFG_I386_SMIACT(WRITELINE("pci:00.0", i82439hx_host_device, smi_act_w))
MCFG_PCI_ROOT_ADD( ":pci")
MCFG_I82439HX_ADD( ":pci:00.0", ":maincpu", 256*1024*1024)
MCFG_I82371SB_ISA_ADD(":pci:07.0")
MCFG_DEVICE_ADD( ":pci", PCI_ROOT, 0)
MCFG_DEVICE_ADD( ":pci:00.0", I82439HX, 0, "maincpu", 256*1024*1024)
MCFG_DEVICE_ADD( ":pci:07.0", I82371SB_ISA, 0)
MCFG_I82371SB_BOOT_STATE_HOOK(WRITE8(*this, pcipc_state, boot_state_phoenix_ver40_rev6_w))
MCFG_I82371SB_SMI_CB(INPUTLINE(":maincpu", INPUT_LINE_SMI))
// MCFG_IDE_PCI_ADD( ":pci:07.1", 0x80867010, 0x03, 0x00000000)
// MCFG_MGA2064W_ADD( ":pci:12.0")
// MCFG_DEVICE_ADD( ":pci:07.1", IDE_PCI, 0, 0x80867010, 0x03, 0x00000000)
// MCFG_DEVICE_ADD( ":pci:12.0", MGA2064W, 0)
MCFG_DEVICE_ADD("board4", ISA16_SLOT, 0, "pci:07.0:isabus", isa_internal_devices, "fdc37c93x", true)
MCFG_SLOT_OPTION_MACHINE_CONFIG("fdc37c93x", superio_config)
@ -509,12 +509,12 @@ MACHINE_CONFIG_START(pcipc_state::pcipctx)
MCFG_DEVICE_ADD("maincpu", PENTIUM, 60000000)
MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("pci:07.0:pic8259_master", pic8259_device, inta_cb)
MCFG_PCI_ROOT_ADD( ":pci")
MCFG_I82439TX_ADD( ":pci:00.0", ":maincpu", 256*1024*1024)
MCFG_I82371SB_ISA_ADD(":pci:07.0")
MCFG_DEVICE_ADD( ":pci", PCI_ROOT, 0)
MCFG_DEVICE_ADD( ":pci:00.0", I82439TX, 0, ":maincpu", 256*1024*1024)
MCFG_DEVICE_ADD( ":pci:07.0", I82371SB_ISA, 0)
MCFG_I82371SB_BOOT_STATE_HOOK(WRITE8(*this, pcipc_state, boot_state_award_w))
// MCFG_IDE_PCI_ADD( ":pci:07.1", 0x80867010, 0x03, 0x00000000)
MCFG_MGA2064W_ADD( ":pci:12.0")
// MCFG_DEVICE_ADD( ":pci:07.1", IDE_PCI, 0, 0x80867010, 0x03, 0x00000000)
MCFG_DEVICE_ADD( ":pci:12.0", MGA2064W, 0)
MACHINE_CONFIG_END
ROM_START(pcipc)

6
src/mame/drivers/seattle.cpp
View File

@ -1879,7 +1879,7 @@ MACHINE_CONFIG_START(seattle_state::seattle_common)
MCFG_MIPS3_SYSTEM_CLOCK(SYSTEM_CLOCK)
// PCI Bus Devices
MCFG_PCI_ROOT_ADD(":pci")
MCFG_DEVICE_ADD(":pci", PCI_ROOT, 0)
MCFG_GT64010_ADD(PCI_ID_GALILEO, ":maincpu", SYSTEM_CLOCK, GALILEO_IRQ_NUM)
MCFG_GT64XXX_SET_CS(0, seattle_state::seattle_cs0_map)
@ -1888,8 +1888,8 @@ MACHINE_CONFIG_START(seattle_state::seattle_common)
MCFG_GT64XXX_SET_CS(3, seattle_state::seattle_cs3_map)
MCFG_GT64XX_SET_SIMM0(0x00800000)
MCFG_IDE_PCI_ADD(PCI_ID_IDE, 0x100b0002, 0x01, 0x0)
MCFG_IDE_PCI_IRQ_ADD(":maincpu", IDE_IRQ_NUM)
MCFG_DEVICE_ADD(PCI_ID_IDE, IDE_PCI, 0, 0x100b0002, 0x01, 0x0)
MCFG_IDE_PCI_IRQ_HANDLER(INPUTLINE(m_maincpu, IDE_IRQ_NUM))
MCFG_IDE_PCI_SET_LEGACY_TOP(0x0a0)
MCFG_DEVICE_ADD(PCI_ID_VIDEO, VOODOO_1_PCI, 0, m_maincpu, m_screen)

6
src/mame/drivers/vegas.cpp
View File

@ -1723,9 +1723,9 @@ MACHINE_CONFIG_START(vegas_state::vegascore)
MCFG_MIPS3_SYSTEM_CLOCK(vegas_state::SYSTEM_CLOCK)
// PCI Bus Devices
MCFG_PCI_ROOT_ADD(":pci")
MCFG_DEVICE_ADD(":pci", PCI_ROOT, 0)
MCFG_VRC5074_ADD(PCI_ID_NILE, ":maincpu")
MCFG_DEVICE_ADD(PCI_ID_NILE, VRC5074, 0, m_maincpu)
MCFG_VRC5074_SET_SDRAM(0, 0x00800000)
MCFG_VRC5074_SET_CS(2, vegas_state::vegas_cs2_map)
MCFG_VRC5074_SET_CS(3, vegas_state::vegas_cs3_map)
@ -1734,7 +1734,7 @@ MACHINE_CONFIG_START(vegas_state::vegascore)
MCFG_VRC5074_SET_CS(6, vegas_state::vegas_cs6_map)
MCFG_VRC5074_SET_CS(7, vegas_state::vegas_cs7_map)
MCFG_IDE_PCI_ADD(PCI_ID_IDE, 0x10950646, 0x05, 0x0)
MCFG_DEVICE_ADD(PCI_ID_IDE, IDE_PCI, 0, 0x10950646, 0x05, 0x0)
MCFG_IDE_PCI_IRQ_HANDLER(WRITELINE(PCI_ID_NILE, vrc5074_device, pci_intr_d))
//MCFG_IDE_PCI_SET_PIF(0x8f)

40
src/mame/includes/xbox_pci.h
View File

@ -14,25 +14,28 @@
class nv2a_host_device : public pci_host_device {
public:
template <typename T>
nv2a_host_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&cpu_tag)
: nv2a_host_device(mconfig, tag, owner, clock)
{
set_ids_host(0x10de02a5, 0, 0);
set_cpu_tag(std::forward<T>(cpu_tag));
}
nv2a_host_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
virtual void map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space) override;
void set_cpu_tag(const char *cpu_tag);
uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space) override;
template <typename T> void set_cpu_tag(T &&cpu_tag) { cpu.set_tag(std::forward<T>(cpu_tag)); }
protected:
virtual void device_start() override;
virtual void device_reset() override;
private:
const char *cpu_tag;
cpu_device *cpu;
required_device<device_memory_interface> cpu;
};
DECLARE_DEVICE_TYPE(NV2A_HOST, nv2a_host_device)
#define MCFG_NV2A_HOST_ADD(_tag, _cpu_tag) MCFG_PCI_HOST_ADD(_tag, NV2A_HOST, 0x10de02a5, 0, 0) \
downcast<nv2a_host_device *>(device)->set_cpu_tag(_cpu_tag);
/*
* Ram
*/
@ -180,8 +183,14 @@ DECLARE_DEVICE_TYPE(MCPX_ETH, mcpx_eth_device)
class mcpx_apu_device : public pci_device {
public:
template <typename T>
mcpx_apu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&cpu_tag)
: mcpx_apu_device(mconfig, tag, owner, clock)
{
set_cpu_tag(std::forward<T>(cpu_tag));
}
mcpx_apu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
void set_cpu_tag(const char *cpu_tag);
template <typename T> void set_cpu_tag(T &&cpu_tag) { cpu.set_tag(std::forward<T>(cpu_tag)); }
DECLARE_READ32_MEMBER(apu_r);
DECLARE_WRITE32_MEMBER(apu_w);
@ -192,8 +201,7 @@ protected:
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
private:
const char *cpu_tag;
cpu_device *cpu;
required_device<device_memory_interface> cpu;
// APU contains 3 dsps: voice processor (VP) global processor (GP) encode processor (EP)
struct apu_state {
uint32_t memory[0x60000 / 4];
@ -221,9 +229,6 @@ private:
DECLARE_DEVICE_TYPE(MCPX_APU, mcpx_apu_device)
#define MCFG_MCPX_APU_ADD(_tag, _cpu_tag) MCFG_PCI_DEVICE_ADD(_tag, MCPX_APU, 0x10de01b0, 0, 0, 0) \
downcast<mcpx_apu_device *>(device)->set_cpu_tag(_cpu_tag);
/*
* AC97 Audio Controller
*/
@ -298,6 +303,11 @@ DECLARE_DEVICE_TYPE(MCPX_IDE, mcpx_ide_device)
class nv2a_agp_device : public agp_bridge_device {
public:
nv2a_agp_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, uint32_t main_id, uint32_t revision)
: nv2a_agp_device(mconfig, tag, owner, clock)
{
set_ids_bridge(main_id, revision);
}
nv2a_agp_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
@ -314,7 +324,7 @@ DECLARE_DEVICE_TYPE(NV2A_AGP, nv2a_agp_device)
class nv2a_gpu_device : public pci_device {
public:
nv2a_gpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
void set_cpu_tag(const char *cpu_tag);
template <typename T> void set_cpu_tag(T &&cpu_tag) { cpu.set_tag(std::forward<T>(cpu_tag)); }
nv2a_renderer *debug_get_renderer() { return nvidia_nv2a; }
template<class Object> devcb_base &set_interrupt_handler(Object &&cb) { return m_interrupt_handler.set_callback(std::forward<Object>(cb)); }
@ -330,7 +340,7 @@ protected:
private:
nv2a_renderer *nvidia_nv2a;
const char *cpu_tag;
required_device<device_memory_interface> cpu;
devcb_write_line m_interrupt_handler;
address_space *m_program;
void nv2a_mmio(address_map &map);

21
src/mame/machine/iteagle_fpga.cpp
View File

@ -34,9 +34,10 @@ void iteagle_fpga_device::ram_map(address_map &map)
}
iteagle_fpga_device::iteagle_fpga_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: pci_device(mconfig, ITEAGLE_FPGA, tag, owner, clock),
m_rtc(*this, "eagle2_rtc"), m_e1_nvram(*this, "eagle1_bram"), m_scc1(*this, AM85C30_TAG), m_version(0), m_seq_init(0)
: pci_device(mconfig, ITEAGLE_FPGA, tag, owner, clock)
, m_rtc(*this, "eagle2_rtc"), m_e1_nvram(*this, "eagle1_bram"), m_scc1(*this, AM85C30_TAG), m_screen(*this, finder_base::DUMMY_TAG), m_cpu(*this, finder_base::DUMMY_TAG), m_version(0), m_seq_init(0)
{
set_ids(0x55cc33aa, 0xaa, 0xaaaaaa, 0x00);
}
MACHINE_CONFIG_START(iteagle_fpga_device::device_add_mconfig)
@ -63,8 +64,6 @@ MACHINE_CONFIG_END
void iteagle_fpga_device::device_start()
{
m_screen = downcast<screen_device *>(machine().device("screen"));
// RTC M48T02
m_rtc->set_base(m_rtc_regs, sizeof(m_rtc_regs));
@ -104,7 +103,6 @@ void iteagle_fpga_device::device_start()
void iteagle_fpga_device::device_reset()
{
remap_cb();
m_cpu = machine().device<cpu_device>(m_cpu_tag);
memset(m_fpga_regs, 0, sizeof(m_fpga_regs));
m_seq = m_seq_init;
m_seq_rem1 = 0;
@ -471,7 +469,7 @@ WRITE32_MEMBER( iteagle_fpga_device::fpga_w )
//*************************************
//* AM85c30 serial controller
//*************************************
void iteagle_am85c30::reset(void)
void iteagle_am85c30::reset()
{
memset(m_rr_regs, 0, 0x10 * 2);
memset(m_wr_regs, 0, 0x10 * 2);
@ -656,9 +654,11 @@ MACHINE_CONFIG_START(iteagle_eeprom_device::device_add_mconfig)
MACHINE_CONFIG_END
iteagle_eeprom_device::iteagle_eeprom_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: pci_device(mconfig, ITEAGLE_EEPROM, tag, owner, clock),
m_sw_version(0), m_hw_version(0), m_eeprom(*this, "eeprom")
: pci_device(mconfig, ITEAGLE_EEPROM, tag, owner, clock)
, m_sw_version(0), m_hw_version(0), m_eeprom(*this, "eeprom")
{
set_ids(0x80861229, 0x02, 0x020000, 0x00);
// When corrupt writes 0x3=2, 0x3e=2, 0xa=0, 0x30=0
// 0x4 = HW Version - 6-8 is GREEN board PCB, 9 is RED board PCB
// 0x5 = Serial Num + top byte of 0x4
@ -777,9 +777,10 @@ void iteagle_periph_device::ctrl_map(address_map &map)
}
iteagle_periph_device::iteagle_periph_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: pci_device(mconfig, ITEAGLE_PERIPH, tag, owner, clock),
m_rtc(*this, "eagle1_rtc")
: pci_device(mconfig, ITEAGLE_PERIPH, tag, owner, clock)
, m_rtc(*this, "eagle1_rtc")
{
set_ids(0x1080c693, 0x00, 0x060100, 0x00);
}
void iteagle_periph_device::device_start()

47
src/mame/machine/iteagle_fpga.h
View File

@ -13,31 +13,18 @@
#include "bus/rs232/rs232.h"
#include "screen.h"
//MCFG_PCI_DEVICE_ADD(_tag, _type, _main_id, _revision, _pclass, _subsystem_id)
#define MCFG_ITEAGLE_FPGA_ADD(_tag, _cpu_tag, _irq_num, _serial_irq_num) \
MCFG_PCI_DEVICE_ADD(_tag, ITEAGLE_FPGA, 0x55CC33AA, 0xAA, 0xAAAAAA, 0x00) \
downcast<iteagle_fpga_device *>(device)->set_irq_info(_cpu_tag, _irq_num, _serial_irq_num);
#define MCFG_ITEAGLE_FPGA_INIT(_version, _seq_init) \
downcast<iteagle_fpga_device *>(device)->set_init_info(_version, _seq_init);
#define MCFG_ITEAGLE_EEPROM_ADD(_tag) \
MCFG_PCI_DEVICE_ADD(_tag, ITEAGLE_EEPROM, 0x80861229, 0x02, 0x020000, 0x00)
downcast<iteagle_fpga_device &>(*device).set_init_info(_version, _seq_init);
#define MCFG_ITEAGLE_EEPROM_INIT(_sw_version, _hw_version) \
downcast<iteagle_eeprom_device *>(device)->set_info(_sw_version, _hw_version);
// Mimic Cypress CY82C693 Peripheral Controller
#define MCFG_ITEAGLE_PERIPH_ADD(_tag) \
MCFG_PCI_DEVICE_ADD(_tag, ITEAGLE_PERIPH, 0x1080C693, 0x00, 0x060100, 0x00)
downcast<iteagle_eeprom_device &>(*device).set_info(_sw_version, _hw_version);
// Functional emulation of AMD AM85C30 serial controller
// Two channels, A & B
class iteagle_am85c30
{
public:
void reset(void);
void reset();
void write_control(uint8_t data, int channel);
uint8_t read_control(int channel);
void write_data(uint8_t data, int channel);
@ -45,7 +32,7 @@ public:
void write_rx_str(int channel, std::string resp);
std::string get_tx_str(int channel) { return m_serial_tx[channel]; };
void clear_tx_str(int channel) { m_serial_tx[channel].clear(); };
bool check_interrupt(void) { return (m_rr_regs[0][3] != 0); };
bool check_interrupt() { return (m_rr_regs[0][3] != 0); };
private:
uint8_t m_rr_regs[2][16];
uint8_t m_wr_regs[2][16];
@ -56,16 +43,19 @@ private:
class iteagle_fpga_device : public pci_device
{
public:
template <typename T, typename U>
iteagle_fpga_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&screen_tag, U &&cpu_tag, int irq_num, int serial_num)
: iteagle_fpga_device(mconfig, tag, owner, clock)
{
set_screen_tag(std::forward<T>(screen_tag));
set_irq_info(std::forward<U>(cpu_tag), irq_num, serial_num);
}
iteagle_fpga_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
required_device<nvram_device> m_rtc;
optional_device<nvram_device> m_e1_nvram;
required_device<scc85c30_device> m_scc1;
screen_device *m_screen;
void set_init_info(int version, int seq_init) {m_version=version; m_seq_init=seq_init;}
void set_irq_info(const char *tag, const int irq_num, const int serial_num) {
m_cpu_tag = tag; m_irq_num = irq_num; m_serial_irq_num = serial_num;}
template <typename T> void set_screen_tag(T &&tag) { m_screen.set_tag(std::forward<T>(tag)); }
template <typename T> void set_irq_info(T &&tag, const int irq_num, int serial_num) {
m_cpu.set_tag(std::forward<T>(tag)); m_irq_num = irq_num; m_serial_irq_num = serial_num; }
DECLARE_WRITE_LINE_MEMBER(vblank_update);
DECLARE_WRITE8_MEMBER(serial_rx_w);
@ -77,9 +67,13 @@ protected:
virtual void device_add_mconfig(machine_config &config) override;
private:
required_device<nvram_device> m_rtc;
optional_device<nvram_device> m_e1_nvram;
required_device<scc85c30_device> m_scc1;
required_device<screen_device> m_screen;
emu_timer * m_timer;
const char *m_cpu_tag;
cpu_device *m_cpu;
required_device<device_execute_interface> m_cpu;
int m_irq_num;
int m_serial_irq_num;
@ -148,6 +142,7 @@ private:
required_device<eeprom_serial_93cxx_device> m_eeprom;
};
// Mimic Cypress CY82C693 Peripheral Controller
class iteagle_periph_device : public pci_device {
public:
iteagle_periph_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);

1
src/mame/machine/segabb.cpp
View File

@ -20,6 +20,7 @@ void sega_lindbergh_baseboard_device::map3(address_map &map)
sega_lindbergh_baseboard_device::sega_lindbergh_baseboard_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: pci_device(mconfig, SEGA_LINDBERGH_BASEBOARD, tag, owner, clock)
{
set_ids(0x105718c1, 0x10, 0x068000, 0x11db067b);
}
void sega_lindbergh_baseboard_device::device_start()

3
src/mame/machine/segabb.h
View File

@ -9,9 +9,6 @@
#include "machine/pci.h"
#define MCFG_SEGA_LINDBERGH_BASEBOARD_ADD(_tag) \
MCFG_PCI_DEVICE_ADD(_tag, SEGA_LINDBERGH_BASEBOARD, 0x105718c1, 0x10, 0x068000, 0x11db067b)
class sega_lindbergh_baseboard_device : public pci_device {
public:
sega_lindbergh_baseboard_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);

34
src/mame/machine/xbox.cpp
View File

@ -862,32 +862,32 @@ void xbox_base_state::xbox_base_map_io(address_map &map)
MACHINE_CONFIG_START(xbox_base_state::xbox_base)
/* basic machine hardware */
MCFG_DEVICE_ADD("maincpu", PENTIUM3, 733333333) /* Wrong! family 6 model 8 stepping 10 */
MCFG_DEVICE_ADD(m_maincpu, PENTIUM3, 733333333) /* Wrong! family 6 model 8 stepping 10 */
MCFG_DEVICE_PROGRAM_MAP(xbox_base_map)
MCFG_DEVICE_IO_MAP(xbox_base_map_io)
MCFG_DEVICE_IRQ_ACKNOWLEDGE_DRIVER(xbox_base_state, irq_callback)
MCFG_QUANTUM_TIME(attotime::from_hz(6000))
MCFG_PCI_ROOT_ADD( ":pci")
MCFG_NV2A_HOST_ADD( ":pci:00.0", "maincpu")
MCFG_PCI_DEVICE_ADD(":pci:00.3", NV2A_RAM, 0x10de02a6, 0, 0, 0)
MCFG_PCI_DEVICE_ADD(":pci:01.0", MCPX_LPC, 0x10de01b2, 0xb4, 0, 0) // revision id must be at least 0xb4, otherwise usb will require a hub
MCFG_PCI_DEVICE_ADD(":pci:01.1", MCPX_SMBUS, 0x10de01b4, 0, 0, 0)
MCFG_DEVICE_ADD(":pci", PCI_ROOT, 0)
MCFG_DEVICE_ADD(":pci:00.0", NV2A_HOST, 0, m_maincpu)
MCFG_DEVICE_ADD(":pci:00.3", NV2A_RAM, 0) downcast<pci_device &>(*device).set_ids(0x10de02a6, 0, 0, 0);
MCFG_DEVICE_ADD(":pci:01.0", MCPX_LPC, 0) downcast<pci_device &>(*device).set_ids(0x10de01b2, 0xb4, 0, 0); // revision id must be at least 0xb4, otherwise usb will require a hub
MCFG_DEVICE_ADD(":pci:01.1", MCPX_SMBUS, 0) downcast<pci_device &>(*device).set_ids(0x10de01b4, 0, 0, 0);
MCFG_MCPX_SMBUS_INTERRUPT_HANDLER(WRITELINE(*this, xbox_base_state, xbox_smbus_interrupt_changed))
MCFG_PCI_DEVICE_ADD(":pci:02.0", MCPX_OHCI, 0x10de01c2, 0, 0, 0)
MCFG_DEVICE_ADD(":pci:02.0", MCPX_OHCI, 0) downcast<pci_device &>(*device).set_ids(0x10de01c2, 0, 0, 0);
MCFG_MCPX_OHCI_INTERRUPT_HANDLER(WRITELINE(*this, xbox_base_state, xbox_ohci_usb_interrupt_changed))
MCFG_PCI_DEVICE_ADD(":pci:03.0", MCPX_OHCI, 0x10de01c2, 0, 0, 0)
MCFG_PCI_DEVICE_ADD(":pci:04.0", MCPX_ETH, 0x10de01c3, 0, 0, 0)
MCFG_MCPX_APU_ADD( ":pci:05.0", "maincpu")
MCFG_PCI_DEVICE_ADD(":pci:06.0", MCPX_AC97_AUDIO, 0x10de01b1, 0, 0, 0)
MCFG_PCI_DEVICE_ADD(":pci:06.1", MCPX_AC97_MODEM, 0x10de01c1, 0, 0, 0)
MCFG_PCI_BRIDGE_ADD(":pci:08.0", 0x10de01b8, 0)
MCFG_PCI_DEVICE_ADD(":pci:09.0", MCPX_IDE, 0x10de01bc, 0, 0, 0)
MCFG_DEVICE_ADD(":pci:03.0", MCPX_OHCI, 0) downcast<pci_device &>(*device).set_ids(0x10de01c2, 0, 0, 0);
MCFG_DEVICE_ADD(":pci:04.0", MCPX_ETH, 0) downcast<pci_device &>(*device).set_ids(0x10de01c3, 0, 0, 0);
MCFG_DEVICE_ADD(":pci:05.0", MCPX_APU, 0, m_maincpu)
MCFG_DEVICE_ADD(":pci:06.0", MCPX_AC97_AUDIO, 0) downcast<pci_device &>(*device).set_ids(0x10de01b1, 0, 0, 0);
MCFG_DEVICE_ADD(":pci:06.1", MCPX_AC97_MODEM, 0) downcast<pci_device &>(*device).set_ids(0x10de01c1, 0, 0, 0);
MCFG_DEVICE_ADD(":pci:08.0", PCI_BRIDGE, 0, 0x10de01b8, 0)
MCFG_DEVICE_ADD(":pci:09.0", MCPX_IDE, 0) downcast<pci_device &>(*device).set_ids(0x10de01bc, 0, 0, 0);
MCFG_MCPX_IDE_INTERRUPT_HANDLER(WRITELINE("pic8259_2", pic8259_device, ir6_w))
MCFG_AGP_BRIDGE_ADD(":pci:1e.0", NV2A_AGP, 0x10de01b7, 0)
MCFG_PCI_DEVICE_ADD(":pci:1e.0:00.0", NV2A_GPU, 0x10de02a0, 0, 0, 0)
MCFG_MCPX_NV2A_GPU_CPU("maincpu")
MCFG_DEVICE_ADD(":pci:1e.0", NV2A_AGP, 0, 0x10de01b7, 0)
MCFG_DEVICE_ADD(":pci:1e.0:00.0", NV2A_GPU, 0) downcast<pci_device &>(*device).set_ids(0x10de02a0, 0, 0, 0);
MCFG_MCPX_NV2A_GPU_CPU(m_maincpu)
MCFG_MCPX_NV2A_GPU_INTERRUPT_HANDLER(WRITELINE(*this, xbox_base_state, xbox_nv2a_interrupt_changed))
MCFG_DEVICE_ADD("pic8259_1", PIC8259, 0)

40
src/mame/machine/xbox_pci.cpp
View File

@ -15,11 +15,11 @@
DEFINE_DEVICE_TYPE(NV2A_HOST, nv2a_host_device, "nv2a_host", "NV2A PCI Bridge Device - Host Bridge")
nv2a_host_device::nv2a_host_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: pci_host_device(mconfig, NV2A_HOST, tag, owner, clock),
cpu_tag(nullptr),
cpu(nullptr)
nv2a_host_device::nv2a_host_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
pci_host_device(mconfig, NV2A_HOST, tag, owner, clock),
cpu(*this, finder_base::DUMMY_TAG)
{
set_ids(0x10de01b0, 0, 0, 0);
}
void nv2a_host_device::map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
@ -28,15 +28,9 @@ void nv2a_host_device::map_extra(uint64_t memory_window_start, uint64_t memory_w
io_space->install_device(0, 0xffff, *static_cast<pci_host_device *>(this), &pci_host_device::io_configuration_access_map);
}
void nv2a_host_device::set_cpu_tag(const char *_cpu_tag)
{
cpu_tag = _cpu_tag;
}
void nv2a_host_device::device_start()
{
pci_host_device::device_start();
cpu = machine().device<cpu_device>(cpu_tag);
memory_space = &cpu->space(AS_PROGRAM);
io_space = &cpu->space(AS_IO);
@ -382,18 +376,12 @@ void mcpx_apu_device::apu_mmio(address_map &map)
map(0x00000000, 0x00007ffff).rw(this, FUNC(mcpx_apu_device::apu_r), FUNC(mcpx_apu_device::apu_w));
}
mcpx_apu_device::mcpx_apu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: pci_device(mconfig, MCPX_APU, tag, owner, clock),
cpu_tag(nullptr),
cpu(nullptr)
mcpx_apu_device::mcpx_apu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
pci_device(mconfig, MCPX_APU, tag, owner, clock),
cpu(*this, finder_base::DUMMY_TAG)
{
}
void mcpx_apu_device::set_cpu_tag(const char *_cpu_tag)
{
cpu_tag = _cpu_tag;
}
void mcpx_apu_device::device_start()
{
pci_device::device_start();
@ -406,7 +394,6 @@ void mcpx_apu_device::device_start()
memset(apust.voices_position_start, 0, sizeof(apust.voices_position_start));
memset(apust.voices_position_end, 0, sizeof(apust.voices_position_end));
memset(apust.voices_position_increment, 0, sizeof(apust.voices_position_increment));
cpu = machine().device<cpu_device>(cpu_tag);
apust.space = &cpu->space();
apust.timer = timer_alloc(0);
apust.timer->enable(false);
@ -762,20 +749,15 @@ void nv2a_gpu_device::nv2a_mirror(address_map &map)
map(0x00000000, 0x07ffffff).ram().rw(this, FUNC(nv2a_gpu_device::nv2a_mirror_r), FUNC(nv2a_gpu_device::nv2a_mirror_w));
}
nv2a_gpu_device::nv2a_gpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: pci_device(mconfig, NV2A_GPU, tag, owner, clock),
nv2a_gpu_device::nv2a_gpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
pci_device(mconfig, NV2A_GPU, tag, owner, clock),
nvidia_nv2a(nullptr),
cpu_tag(nullptr),
cpu(*this, finder_base::DUMMY_TAG),
m_interrupt_handler(*this),
m_program(nullptr)
{
}
void nv2a_gpu_device::set_cpu_tag(const char *_cpu_tag)
{
cpu_tag = _cpu_tag;
}
void nv2a_gpu_device::device_start()
{
pci_device::device_start();
@ -784,7 +766,7 @@ void nv2a_gpu_device::device_start()
bank_infos[0].adr = 0xfd000000;
add_map(0x08000000, M_MEM, FUNC(nv2a_gpu_device::nv2a_mirror));
bank_infos[1].adr = 0xf0000000;
m_program = &machine().device<cpu_device>(cpu_tag)->space();
m_program = &cpu->space(AS_PROGRAM); // FIXME: isn't there a proper way to map stuff or do DMA via the PCI device interface?
nvidia_nv2a = new nv2a_renderer(machine());
nvidia_nv2a->set_irq_callbaclk(
[&](int state)