mirror of
https://github.com/holub/mame
synced 2025-04-25 01:40:16 +03:00
i8251: Preliminary addition of synchronous support.
- Can transmit - Can receive with one sync byte - bisync still being worked on
This commit is contained in:
Robbbert
parent
fd882987e0
commit
1076f566a4
@ -80,10 +80,9 @@ void i8251_device::device_start()
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m_rxrdy_handler.resolve_safe();
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m_txrdy_handler.resolve_safe();
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m_txempty_handler.resolve_safe();
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m_syndet_handler.resolve_safe();
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save_item(NAME(m_flags));
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save_item(NAME(m_sync_byte_offset));
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save_item(NAME(m_sync_byte_count));
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save_item(NAME(m_sync_bytes));
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save_item(NAME(m_status));
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save_item(NAME(m_command));
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save_item(NAME(m_mode_byte));
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@ -154,12 +153,95 @@ void i8251_device::receive_clock()
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}
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}
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bool i8251_device::calc_parity(u8 ch)
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{
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bool data = 0;
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for (u8 b = 0; b < 8; b++)
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data ^= BIT(ch, b);
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return data;
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}
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void i8251_device::sync1_rxc()
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{
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// is rx enabled?
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if (!BIT(m_command, 2))
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return;
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// if ext sync, and syndet low, quit
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// Todo: what should happen here?
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if (m_syndet_pin && !m_ext_syn_set)
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return;
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u8 need_parity = BIT(m_mode_byte, 4);
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// see about parity
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if (need_parity && (m_rxd_bits == m_data_bits_count))
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{
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if (calc_parity(m_sync1) != m_rxd)
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m_status |= I8251_STATUS_PARITY_ERROR;
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// and then continue on as if everything was ok
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}
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else
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{
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// add bit to byte
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m_sync1 = (m_sync1 >> 1) | (m_rxd << (m_data_bits_count-1));
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}
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// if we are in hunt mode, the byte loaded has to
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// be the sync byte. If not, go around again.
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// if we leave hunt mode now, the sync byte must not go to the receive buffer
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bool was_in_hunt_mode = false;
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if (m_hunt_on)
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{
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if (m_sync1 == m_sync8)
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{
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m_rxd_bits = m_data_bits_count;
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m_hunt_on = false;
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was_in_hunt_mode = true;
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}
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else
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return;
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}
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// is byte complete? if not, quit
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m_rxd_bits++;
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if (m_rxd_bits < (m_data_bits_count + need_parity))
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return;
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// now we have a synchronised byte, and parity has been dealt with
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// copy byte to rx buffer
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if (!was_in_hunt_mode)
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receive_character(m_sync1);
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// Is it a sync byte? syndet gets indicated whenever
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// a sync byte passes by, regardless of hunt_mode status.
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if (m_sync1 == m_sync8)
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update_syndet(true);
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m_rxd_bits = 0;
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m_sync1 = 0;
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}
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void i8251_device::sync2_rxc()
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{
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// is rx enabled?
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if (!BIT(m_command, 2))
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return;
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// if ext sync, and syndet low, quit
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if (m_syndet_pin && !m_ext_syn_set)
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return;
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// remainder yet to be written
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}
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/*-------------------------------------------------
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is_tx_enabled
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-------------------------------------------------*/
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bool i8251_device::is_tx_enabled() const
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{
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return BIT(m_command , 0) && !m_cts;
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return BIT(m_command, 0) && !m_cts;
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}
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/*-------------------------------------------------
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@ -196,7 +278,7 @@ void i8251_device::transmit_clock()
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if (is_transmit_register_empty())
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{
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if ((m_status & I8251_STATUS_TX_READY) == 0 && (is_tx_enabled() || (m_flags & I8251_DELAYED_TX_EN) != 0))
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if ((m_status & I8251_STATUS_TX_READY) == 0 && (is_tx_enabled() || m_delayed_tx_en))
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start_tx();
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else
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m_status |= I8251_STATUS_TX_EMPTY;
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@ -211,33 +293,6 @@ void i8251_device::transmit_clock()
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uint8_t data = transmit_register_get_data_bit();
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m_txd_handler(data);
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}
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#if 0
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/* hunt mode? */
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/* after each bit has been shifted in, it is compared against the current sync byte */
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if (BIT(m_command, 7))
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{
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/* data matches sync byte? */
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if (m_data == m_sync_bytes[m_sync_byte_offset])
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{
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/* sync byte matches */
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/* update for next sync byte? */
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m_sync_byte_offset++;
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/* do all sync bytes match? */
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if (m_sync_byte_offset == m_sync_byte_count)
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{
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/* ent hunt mode */
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m_command &= ~(1<<7);
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}
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}
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else
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{
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/* if there is no match, reset */
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m_sync_byte_offset = 0;
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}
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}
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#endif
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}
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@ -281,6 +336,32 @@ void i8251_device::update_tx_empty()
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/*---------------------------------------------------
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update_syndet - indicates that a sync
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character string has been received
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1 = valid sync; 0 = hunt mode on, or status read
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-----------------------------------------------------*/
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void i8251_device::update_syndet(bool voltage)
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{
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LOG("I8251: Syndet %d\n",voltage);
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// Sanity check
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if (voltage && m_hunt_on)
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printf("I8251: Syndet - invalid parameters\n");
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// Adjust status register
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if (voltage)
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m_status |= 0x40;
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else
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m_status &= ~0x40;
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// If syndet is set as an output pin, indicate new status
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if (!m_syndet_pin)
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m_syndet_handler(voltage);
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}
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//-------------------------------------------------
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// device_reset - device-specific reset
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//-------------------------------------------------
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@ -301,11 +382,8 @@ void i8251_device::device_reset()
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transmit_register_reset();
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receive_register_reset();
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m_flags = 0;
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/* expecting mode byte */
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m_flags |= I8251_EXPECTING_MODE;
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/* not expecting a sync byte */
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m_flags &= ~I8251_EXPECTING_SYNC_BYTE;
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m_flags = I8251_NEXT_MODE;
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/* no character to read by cpu */
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/* transmitter is ready and is empty */
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@ -401,9 +479,20 @@ void i8251_device::command_w(uint8_t data)
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// datasheet says "returns to mode format", not
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// completely resets the chip. behavior of DEC Rainbow
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// backs this up.
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m_flags |= I8251_EXPECTING_MODE;
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m_flags = I8251_NEXT_MODE;
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}
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// Hunt mode
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m_hunt_on = false;
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update_syndet(false);
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if (m_sync_byte_count)
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m_hunt_on = BIT(data, 7);
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if (m_hunt_on)
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m_ext_syn_set = false;
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if (BIT(data, 3))
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m_txd_handler(0);
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check_for_tx_start();
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update_rx_ready();
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update_tx_ready();
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@ -412,13 +501,10 @@ void i8251_device::command_w(uint8_t data)
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void i8251_device::mode_w(uint8_t data)
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{
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LOG("I8251: Mode byte = %X\n", data);
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LOG("I8251: Mode byte = %02X\n", data);
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m_mode_byte = data;
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/* Synchronous or Asynchronous? */
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if ((data & 0x03) != 0)
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{
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/* Asynchronous
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bit 7,6: stop bit length
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@ -442,159 +528,144 @@ void i8251_device::mode_w(uint8_t data)
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1 = x1
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2 = x16
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3 = x64
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*/
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Synchronous
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bit 7: Number of sync characters
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0 = 1 character
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1 = 2 character
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bit 6: Synchronous mode
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0 = Internal synchronisation
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1 = External synchronisation
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bit 5: parity type
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0 = parity odd
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1 = parity even
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bit 4: parity test enable
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0 = disable
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1 = enable
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bit 3,2: character length
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0 = 5 bits
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1 = 6 bits
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2 = 7 bits
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3 = 8 bits
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bit 1,0 = 0
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*/
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m_data_bits_count = ((data >> 2) & 0x03) + 5;
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LOG("Character length: %d\n", m_data_bits_count);
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parity_t parity = PARITY_NONE;
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switch (data & 0x30)
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{
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case 0x10:
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LOG("Enable ODD parity checking.\n");
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parity = PARITY_ODD;
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break;
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case 0x30:
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LOG("Enable EVEN parity checking.\n");
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parity = PARITY_EVEN;
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break;
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default:
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LOG("Disable parity check.\n");
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}
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stop_bits_t stop_bits = STOP_BITS_0;
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m_br_factor = 1;
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m_flags = I8251_NEXT_COMMAND;
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m_sync_byte_count = 0;
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m_syndet_pin = false;
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/* Synchronous or Asynchronous? */
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if (data & 0x03)
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{
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LOG("I8251: Asynchronous operation\n");
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const int data_bits_count = ((data >> 2) & 0x03) + 5;
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LOG("Character length: %d\n", data_bits_count);
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switch (data & 0xc0)
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{
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case 0x40:
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stop_bits = STOP_BITS_1;
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LOG("stop bit: 1 bit\n");
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break;
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parity_t parity;
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if (BIT(data, 4))
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{
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if (BIT(data, 5))
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{
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LOG("enable parity checking (even parity)\n");
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parity = PARITY_EVEN;
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}
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else
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{
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LOG("enable parity checking (odd parity)\n");
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parity = PARITY_ODD;
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}
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}
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else
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{
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LOG("parity check disabled\n");
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parity = PARITY_NONE;
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case 0x80:
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stop_bits = STOP_BITS_1_5;
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LOG("stop bit: 1.5 bits\n");
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break;
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case 0xc0:
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stop_bits = STOP_BITS_2;
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LOG("stop bit: 2 bits\n");
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break;
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default:
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LOG("stop bit: inhibit\n");
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break;
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}
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stop_bits_t stop_bits;
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switch ((data >> 6) & 0x03)
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{
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case 0:
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default:
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stop_bits = STOP_BITS_0;
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LOG("stop bit: inhibit\n");
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break;
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case 1:
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stop_bits = STOP_BITS_1;
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LOG("stop bit: 1 bit\n");
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break;
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case 2:
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stop_bits = STOP_BITS_1_5;
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LOG("stop bit: 1.5 bits\n");
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break;
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case 3:
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stop_bits = STOP_BITS_2;
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LOG("stop bit: 2 bits\n");
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break;
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}
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set_data_frame(1, data_bits_count, parity, stop_bits);
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receive_register_reset();
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set_data_frame(1, m_data_bits_count, parity, stop_bits);
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switch (data & 0x03)
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{
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case 1: m_br_factor = 1; break;
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case 2: m_br_factor = 16; break;
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case 3: m_br_factor = 64; break;
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case 2:
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m_br_factor = 16;
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break;
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case 3:
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m_br_factor = 64;
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break;
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}
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m_txc_count = 0;
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#if 0
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/* data bits */
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m_receive_char_length = (((data >> 2) & 0x03) + 5);
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if (BIT(data, 4))
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{
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/* parity */
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m_receive_char_length++;
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}
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/* stop bits */
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m_receive_char_length++;
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m_receive_flags &= ~I8251_TRANSFER_RECEIVE_SYNCHRONISED;
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m_receive_flags |= I8251_TRANSFER_RECEIVE_WAITING_FOR_START_BIT;
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#endif
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/* not expecting mode byte now */
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m_flags &= ~I8251_EXPECTING_MODE;
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// m_status = I8251_STATUS_TX_EMPTY | I8251_STATUS_TX_READY;
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}
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else
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{
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/* bit 7: Number of sync characters
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0 = 1 character
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1 = 2 character
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bit 6: Synchronous mode
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0 = Internal synchronisation
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1 = External synchronisation
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bit 5: parity type
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0 = parity odd
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1 = parity even
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bit 4: parity test enable
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0 = disable
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1 = enable
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bit 3,2: character length
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0 = 5 bits
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1 = 6 bits
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2 = 7 bits
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3 = 8 bits
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bit 1,0 = 0
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*/
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LOG("I8251: Synchronous operation\n");
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/* setup for sync byte(s) */
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m_flags |= I8251_EXPECTING_SYNC_BYTE;
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m_sync_byte_offset = 0;
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if (BIT(data, 7))
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{
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m_sync_byte_count = 1;
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}
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else
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{
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m_sync_byte_count = 2;
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}
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m_flags = BIT(data, 7) ? I8251_NEXT_SYNC2 : I8251_NEXT_SYNC1;
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m_sync_byte_count = BIT(data, 7) ? 1 : 2;
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set_data_frame(0, m_data_bits_count, parity, stop_bits);
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m_syndet_pin = BIT(data, 6);
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m_sync8 = 0;
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m_sync16 = 0;
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m_rxd_bits = 0;
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m_sync1 = 0;
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}
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receive_register_reset();
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m_txc_count = 0;
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// m_status = I8251_STATUS_TX_EMPTY | I8251_STATUS_TX_READY;
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}
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void i8251_device::sync1_w(uint8_t data)
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{
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m_sync16 = (data << 8);
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m_flags = I8251_NEXT_SYNC2;
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}
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void i8251_device::sync2_w(uint8_t data)
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{
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if (m_sync_byte_count == 2)
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m_sync16 |= data;
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else
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m_sync8 = data;
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m_flags = I8251_NEXT_COMMAND;
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}
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void i8251_device::control_w(uint8_t data)
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{
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if (m_flags & I8251_EXPECTING_MODE)
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{
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if (m_flags & I8251_EXPECTING_SYNC_BYTE)
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{
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LOG("I8251: Sync byte\n");
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LOG("Sync byte: %02x\n", data);
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/* store sync byte written */
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m_sync_bytes[m_sync_byte_offset] = data;
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m_sync_byte_offset++;
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if (m_sync_byte_offset == m_sync_byte_count)
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{
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/* finished transfering sync bytes, now expecting command */
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m_flags &= ~(I8251_EXPECTING_MODE | I8251_EXPECTING_SYNC_BYTE);
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m_sync_byte_offset = 0;
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// m_status = I8251_STATUS_TX_EMPTY | I8251_STATUS_TX_READY;
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}
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}
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else
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{
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mode_w(data);
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}
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}
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if (m_flags == I8251_NEXT_SYNC1)
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sync1_w(data);
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else
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if (m_flags == I8251_NEXT_SYNC2)
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sync2_w(data);
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else
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if (m_flags == I8251_NEXT_MODE)
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mode_w(data);
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else
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{
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command_w(data);
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}
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}
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@ -608,6 +679,9 @@ uint8_t i8251_device::status_r()
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uint8_t status = (m_dsr << 7) | m_status;
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LOG("status: %02x\n", status);
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// Syndet always goes off after status read
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update_syndet(false);
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return status;
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}
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@ -621,20 +695,15 @@ void i8251_device::data_w(uint8_t data)
|
||||
{
|
||||
m_tx_data = data;
|
||||
|
||||
LOG("data_w %02x\n" , data);
|
||||
LOG("data_w %02x\n", data);
|
||||
|
||||
/* writing clears */
|
||||
m_status &=~I8251_STATUS_TX_READY;
|
||||
update_tx_ready();
|
||||
|
||||
// Store state of tx enable when writing to DB buffer
|
||||
if (is_tx_enabled()) {
|
||||
m_flags |= I8251_DELAYED_TX_EN;
|
||||
} else {
|
||||
m_flags &= ~I8251_DELAYED_TX_EN;
|
||||
}
|
||||
|
||||
check_for_tx_start();
|
||||
// Store state of tx enable when writing to DB buffer
|
||||
m_delayed_tx_en = is_tx_enabled();
|
||||
check_for_tx_start();
|
||||
|
||||
/* if transmitter is active, then tx empty will be signalled */
|
||||
|
||||
@ -685,7 +754,7 @@ uint8_t i8251_device::data_r()
|
||||
|
||||
uint8_t i8251_device::read(offs_t offset)
|
||||
{
|
||||
if (BIT(offset, 0))
|
||||
if (offset)
|
||||
return status_r();
|
||||
else
|
||||
return data_r();
|
||||
@ -693,7 +762,7 @@ uint8_t i8251_device::read(offs_t offset)
|
||||
|
||||
void i8251_device::write(offs_t offset, uint8_t data)
|
||||
{
|
||||
if (BIT(offset, 0))
|
||||
if (offset)
|
||||
control_w(data);
|
||||
else
|
||||
data_w(data);
|
||||
@ -722,13 +791,18 @@ WRITE_LINE_MEMBER(i8251_device::write_dsr)
|
||||
|
||||
WRITE_LINE_MEMBER(i8251_device::write_rxc)
|
||||
{
|
||||
if (m_rxc != state)
|
||||
if (!m_rxc && state)
|
||||
{
|
||||
m_rxc = state;
|
||||
|
||||
if (m_rxc)
|
||||
if (m_sync_byte_count == 1)
|
||||
sync1_rxc();
|
||||
else
|
||||
if (m_sync_byte_count == 2)
|
||||
sync2_rxc();
|
||||
else
|
||||
receive_clock();
|
||||
}
|
||||
|
||||
m_rxc = state;
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(i8251_device::write_txc)
|
||||
@ -742,6 +816,17 @@ WRITE_LINE_MEMBER(i8251_device::write_txc)
|
||||
}
|
||||
}
|
||||
|
||||
// forcibly kill hunt mode
|
||||
WRITE_LINE_MEMBER(i8251_device::write_syn)
|
||||
{
|
||||
if (m_syndet_pin && state) // must be set as input
|
||||
{
|
||||
m_ext_syn_set = true;
|
||||
m_hunt_on = false;
|
||||
update_syndet(true);
|
||||
}
|
||||
}
|
||||
|
||||
READ_LINE_MEMBER(i8251_device::txrdy_r)
|
||||
{
|
||||
return is_tx_enabled() && (m_status & I8251_STATUS_TX_READY) != 0;
|
||||
|
||||
@ -44,6 +44,7 @@ public:
|
||||
DECLARE_WRITE_LINE_MEMBER( write_dsr );
|
||||
DECLARE_WRITE_LINE_MEMBER( write_txc );
|
||||
DECLARE_WRITE_LINE_MEMBER( write_rxc );
|
||||
DECLARE_WRITE_LINE_MEMBER( write_syn );
|
||||
|
||||
DECLARE_READ_LINE_MEMBER(txrdy_r);
|
||||
|
||||
@ -86,9 +87,10 @@ protected:
|
||||
|
||||
enum
|
||||
{
|
||||
I8251_EXPECTING_MODE = 0x01,
|
||||
I8251_EXPECTING_SYNC_BYTE = 0x02,
|
||||
I8251_DELAYED_TX_EN = 0x04
|
||||
I8251_NEXT_COMMAND = 0,
|
||||
I8251_NEXT_MODE,
|
||||
I8251_NEXT_SYNC1,
|
||||
I8251_NEXT_SYNC2,
|
||||
};
|
||||
|
||||
private:
|
||||
@ -100,25 +102,33 @@ private:
|
||||
devcb_write_line m_txempty_handler;
|
||||
devcb_write_line m_syndet_handler;
|
||||
|
||||
void sync1_rxc();
|
||||
void sync2_rxc();
|
||||
void update_syndet(bool voltage);
|
||||
bool calc_parity(u8 ch);
|
||||
|
||||
/* flags controlling how i8251_control_w operates */
|
||||
uint8_t m_flags;
|
||||
/* offset into sync_bytes used during sync byte transfer */
|
||||
uint8_t m_sync_byte_offset;
|
||||
//uint8_t m_sync_byte_offset;
|
||||
/* number of sync bytes written so far */
|
||||
uint8_t m_sync_byte_count;
|
||||
/* the sync bytes written */
|
||||
uint8_t m_sync_bytes[2];
|
||||
//uint8_t m_sync_bytes[2];
|
||||
u8 m_sync1;
|
||||
u16 m_sync2;
|
||||
/* status of i8251 */
|
||||
uint8_t m_status;
|
||||
uint8_t m_command;
|
||||
/* mode byte - bit definitions depend on mode - e.g. synchronous, asynchronous */
|
||||
uint8_t m_mode_byte;
|
||||
bool m_delayed_tx_en;
|
||||
|
||||
int m_cts;
|
||||
int m_dsr;
|
||||
int m_rxd;
|
||||
int m_rxc;
|
||||
int m_txc;
|
||||
bool m_cts;
|
||||
bool m_dsr;
|
||||
bool m_rxd;
|
||||
bool m_rxc;
|
||||
bool m_txc;
|
||||
int m_rxc_count;
|
||||
int m_txc_count;
|
||||
int m_br_factor;
|
||||
@ -127,6 +137,18 @@ private:
|
||||
uint8_t m_rx_data;
|
||||
/* tx buffer */
|
||||
uint8_t m_tx_data;
|
||||
void sync1_w(uint8_t data);
|
||||
void sync2_w(uint8_t data);
|
||||
uint8_t m_sync8;
|
||||
uint16_t m_sync16;
|
||||
// 1 = ext sync enabled via command
|
||||
bool m_syndet_pin;
|
||||
bool m_hunt_on;
|
||||
// 1 = ext syndet pin has been set high; 0 = hunt mode activated
|
||||
bool m_ext_syn_set;
|
||||
// count of rxd bits
|
||||
u8 m_rxd_bits;
|
||||
u8 m_data_bits_count;
|
||||
};
|
||||
|
||||
class v5x_scu_device : public i8251_device
|
||||
|
||||
@ -415,10 +415,9 @@ void device_serial_interface::transmit_register_setup(u8 data_byte)
|
||||
}
|
||||
|
||||
/* stop bit(s) + 1 extra bit as delay between bytes, needed to get 1 stop bit to work. */
|
||||
for (i=0; i<=m_df_stop_bit_count; i++)
|
||||
{
|
||||
transmit_register_add_bit(1);
|
||||
}
|
||||
if (m_df_stop_bit_count) // no stop bits for synchronous
|
||||
for (i=0; i<=m_df_stop_bit_count; i++) // ToDo - see if the hack on this line is still needed (was added 2016-04-10)
|
||||
transmit_register_add_bit(1);
|
||||
}
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user