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snes.c: temporarily reverted implementation of mult/div through timers since it breaks some SNES games on the MESS side [Fabio Priuli]

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this basically comments out timers added by judge in svn 7849, until other timing issues are understood and fixed
This commit is contained in:
Fabio Priuli 2010-03-01 20:55:22 +00:00
parent f548daef05
commit 10a044a144
1 changed files with 31 additions and 3 deletions
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34
src/mame/machine/snes.c
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@ -295,6 +295,8 @@ static TIMER_CALLBACK( snes_hblank_tick )
timer_adjust_oneshot(snes_scanline_timer, video_screen_get_time_until_pos(machine->primary_screen, nextscan, 0), 0); timer_adjust_oneshot(snes_scanline_timer, video_screen_get_time_until_pos(machine->primary_screen, nextscan, 0), 0);
} }
/* FIXME: multiplication should take 8 CPU cycles & division 16 CPU cycles, but
using these timers breaks e.g. Chrono Trigger intro and Super Tennis gameplay. */
static TIMER_CALLBACK(snes_div_callback) static TIMER_CALLBACK(snes_div_callback)
{ {
@ -1323,13 +1325,39 @@ WRITE8_HANDLER( snes_w_io )
case WRMPYA: /* Multiplier A */ case WRMPYA: /* Multiplier A */
break; break;
case WRMPYB: /* Multiplier B */ case WRMPYB: /* Multiplier B */
timer_adjust_oneshot(snes_mult_timer, cputag_clocks_to_attotime(space->machine, "maincpu", 8), 0); snes_ram[WRMPYB] = data;
// timer_adjust_oneshot(snes_mult_timer, cputag_clocks_to_attotime(space->machine, "maincpu", 8), 0);
{
UINT32 c = snes_ram[WRMPYA] * snes_ram[WRMPYB];
snes_ram[RDMPYL] = c & 0xff;
snes_ram[RDMPYH] = (c >> 8) & 0xff;
}
break; break;
case WRDIVL: /* Dividend (low) */ case WRDIVL: /* Dividend (low) */
case WRDIVH: /* Dividend (high) */ case WRDIVH: /* Dividend (high) */
break; break;
case WRDVDD: /* Divisor */ case WRDVDD: /* Divisor */
timer_adjust_oneshot(snes_div_timer, cputag_clocks_to_attotime(space->machine, "maincpu", 8), 0); snes_ram[WRDVDD] = data;
// timer_adjust_oneshot(snes_div_timer, cputag_clocks_to_attotime(space->machine, "maincpu", 16), 0);
{
UINT16 value, dividend, remainder;
dividend = remainder = 0;
value = (snes_ram[WRDIVH] << 8) + snes_ram[WRDIVL];
if (snes_ram[WRDVDD] > 0)
{
dividend = value / data;
remainder = value % data;
}
else
{
dividend = 0xffff;
remainder = value;
}
snes_ram[RDDIVL] = dividend & 0xff;
snes_ram[RDDIVH] = (dividend >> 8) & 0xff;
snes_ram[RDMPYL] = remainder & 0xff;
snes_ram[RDMPYH] = (remainder >> 8) & 0xff;
}
break; break;
case HTIMEL: /* H-Count timer settings (low) */ case HTIMEL: /* H-Count timer settings (low) */
case HTIMEH: /* H-Count timer settings (high) */ case HTIMEH: /* H-Count timer settings (high) */
@ -1337,7 +1365,7 @@ WRITE8_HANDLER( snes_w_io )
case VTIMEH: /* V-Count timer settings (high) */ case VTIMEH: /* V-Count timer settings (high) */
break; break;
case MDMAEN: /* GDMA channel designation and trigger */ case MDMAEN: /* GDMA channel designation and trigger */
snes_gdma( space, data ); snes_gdma(space, data);
data = 0; /* Once DMA is done we need to reset all bits to 0 */ data = 0; /* Once DMA is done we need to reset all bits to 0 */
break; break;
case HDMAEN: /* HDMA channel designation */ case HDMAEN: /* HDMA channel designation */