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https://github.com/holub/mame
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NoteTaker: More floppy hookup, started tracing video writes. [Lord Nightmare]
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Lord-Nightmare
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e9c1a1e474
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10df10fa71
@ -356,10 +356,12 @@ WRITE16_MEMBER(notetaker_state::FIFOBus_w)
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WRITE16_MEMBER( notetaker_state::DiskReg_w )
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{
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// See http://bitsavers.trailing-edge.com/pdf/xerox/notetaker/memos/19781023_More_NoteTaker_IO_Information.pdf but note that bit 12 (called bit 3 in documentation) was changed between oct 1978 and 1979 to reset the disk controller digital-PLL as ClrDiskCont' rather than acting as ProgBitClk0, which is permanently wired high instead, meaning only the 4.5Mhz - 18Mhz dot clocks are available for the CRTC.
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m_ADCSpd0 = (data&0x8000)?1:0;
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m_ADCSpd1 = (data&0x4000)?1:0;
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m_StopWordClock_q = (data&0x2000)?1:0;
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m_ClrDiskCont_q = (data&0x1000)?1:0;
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//if ((!(m_ClrDiskCont_q)) && (data&0x1000)) m_floppy->device_reset(); // reset on rising edge
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m_ClrDiskCont_q = (data&0x1000)?1:0; // originally ProgBitClk0, but co-opted later to reset the FDC's external PLL
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m_ProgBitClk1 = (data&0x0800)?1:0;
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m_ProgBitClk2 = (data&0x0400)?1:0;
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m_ProgBitClk3 = (data&0x0200)?1:0;
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@ -367,11 +369,40 @@ WRITE16_MEMBER( notetaker_state::DiskReg_w )
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m_AnSel2 = (data&0x80)?1:0;
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m_AnSel1 = (data&0x40)?1:0;
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m_DriveSel1 = (data&0x20)?1:0;
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m_DriveSel2 = (data&0x10)?1:0;
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m_DriveSel3 = (data&0x08)?1:0;
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m_DriveSel2 = (data&0x10)?1:0; // drive 2 not present on hardware, but could work if present
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m_DriveSel3 = (data&0x08)?1:0; // drive 3 not present on hardware, but could work if present
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m_SideSelect = (data&0x04)?1:0;
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m_Disk5VOn = (data&0x02)?1:0;
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m_Disk12VOn = (data&0x01)?1:0;
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// ADC stuff
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//TODO
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// FDC stuff
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// first handle the motor stuff; we'll clobber whatever was in m_floppy, then reset it to what it should be
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m_floppy = m_floppy0->get_device();
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m_floppy->mon_w(!(m_Disk5VOn && m_Disk12VOn)); // Disk5VOn and 12VOn can be thought of as a crude MotorOn signal as the motor won't run with either? of them missing.
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//m_floppy = m_floppy0->get_device();
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//m_floppy->mon_w(!(m_Disk5VOn && m_Disk12VOn)); // Disk5VOn and 12VOn can be thought of as a crude MotorOn signal as the motor won't run with either? of them missing.
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//m_floppy = m_floppy0->get_device();
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//m_floppy->mon_w(!(m_Disk5VOn && m_Disk12VOn)); // Disk5VOn and 12VOn can be thought of as a crude MotorOn signal as the motor won't run with either? of them missing.
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// now restore m_floppy state to what it should be
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if (m_DriveSel1) m_floppy = m_floppy0->get_device();
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//else if (m_DriveSel2) m_floppy = m_floppy1->get_device();
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//else if (m_DriveSel3) m_floppy = m_floppy2->get_device();
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else m_floppy = nullptr;
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m_fdc->set_floppy(m_floppy); // select the floppy
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if (m_floppy)
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{
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m_floppy->ss_w(m_SideSelect);
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}
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// Disk5VOn and 12VOn can be thought of as a crude MotorOn signal as the motor won't run with either? of them missing.
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//m_floppy0->mon_w(!(m_Disk5VOn && m_Disk12VOn));
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//m_floppy1->mon_w(!(m_Disk5VOn && m_Disk12VOn));
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//m_floppy2->mon_w(!(m_Disk5VOn && m_Disk12VOn));
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// CRTC clock rate stuff
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//TODO
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}
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WRITE16_MEMBER( notetaker_state::LoadDispAddr_w )
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@ -557,7 +588,7 @@ static ADDRESS_MAP_START(notetaker_iocpu_io, AS_IO, 16, notetaker_state)
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AM_RANGE(0x60, 0x61) AM_MIRROR(0x7E1E) AM_WRITE(FIFOReg_w) // DAC sample and hold and frequency setup
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//AM_RANGE(0xa0, 0xa1) AM_MIRROR(0x7E18) AM_DEVREADWRITE("debug8255", 8255_device, read, write) // debugger board 8255
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AM_RANGE(0xc0, 0xc1) AM_MIRROR(0x7E1E) AM_WRITE(FIFOBus_w) // DAC data write to FIFO
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AM_RANGE(0x100, 0x101) AM_MIRROR(0x7E1E) AM_WRITE(DiskReg_w) // I/O register (adc speed, crtc pixel clock enable, +5 and +12v relays for floppy, etc)
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AM_RANGE(0x100, 0x101) AM_MIRROR(0x7E1E) AM_WRITE(DiskReg_w) // I/O register (adc speed, crtc pixel clock and clock enable, +5 and +12v relays for floppy, etc)
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AM_RANGE(0x120, 0x127) AM_MIRROR(0x7E18) AM_DEVREADWRITE8("wd1791", fd1791_t, read, write, 0x00FF) // floppy controller
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AM_RANGE(0x140, 0x15f) AM_MIRROR(0x7E00) AM_DEVREADWRITE8("crt5027", crt5027_device, read, write, 0x00FF) // crt controller
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AM_RANGE(0x160, 0x161) AM_MIRROR(0x7E1E) AM_WRITE(LoadDispAddr_w) // loads the start address for the display framebuffer
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@ -584,8 +615,8 @@ irq7 VSync (interrupt from the VSYN VSync pin from the crt5027)
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/* writes during boot of io roms v2.0:
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0x88 to port 0x020 (PCR; BootSeqDone(1), processor not locked(0), battery charger off(0), rom not disabled(0) correction off&cr4 off(1), cr3 on(0), cr2 on(0), cr1 on (0);)
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0x02 to port 0x100 (IOR write: enable 5v only relay control)
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0x03 to port 0x100 (IOR write: in addition to above, enable 12v relay control)
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0x0002 to port 0x100 (IOR write: enable 5v only relay control)
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0x0003 to port 0x100 (IOR write: in addition to above, enable 12v relay control)
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<dram memory 0x00000-0x3ffff is zeroed here>
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0x13 to port 0x000 PIC (ICW1, 8085 vector 0b000[ignored], edge trigger mode, interval of 8, single mode (no cascade/ICW3), ICW4 needed )
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0x08 to port 0x002 PIC (ICW2, T7-T3 = 0b00001)
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@ -595,14 +626,14 @@ irq7 VSync (interrupt from the VSYN VSync pin from the crt5027)
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0x0000 to port 0x1ae (reset UART)
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0x0016 to port 0x048 (kbd control reg write)
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0x0005 to port 0x1a8 (UART control reg write)
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0x5f to port 0x140 \
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0xf2 to port 0x142 \
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0x7d to port 0x144 \
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0x1d to port 0x146 \_ set up CRTC
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0x04 to port 0x148 /
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0x10 to port 0x14a /
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0x00 to port 0x154 /
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0x1e to port 0x15a /
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0x5f to port 0x140 (reg0 95 horizontal lines) \
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0xf2 to port 0x142 (reg1 interlaced, hswidth=0xE, hsdelay=2) \
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0x7d to port 0x144 (reg2 16 scans/row, 5 chars/datarow) \
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0x1d to port 0x146 (reg3 0 skew bits, 0x1D datarows/frame) \_ set up CRTC
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0x04 to port 0x148 (reg4 4 scan lines/frame /
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0x10 to port 0x14a (reg5 0x10 vdatastart) /
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0x00 to port 0x154 (reset the crtc) /
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0x1e to port 0x15a (reg8 load cursor line address = 0x1e) /
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0x0a03 to port 0x100 (IOR write: set bit clock to 12Mhz)
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0x2a03 to port 0x100 (IOR write: enable crtc clock chain)
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0x00 to port 0x15c (fire off crtc timing chain)
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@ -613,8 +644,8 @@ read from 0x44 (byte wide) to check input fifo status
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... more stuff here missing relating to making the beep tone through fifo
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(around pc=6b6) read keyboard uart until mouse button is clicked (WaitNoBug)
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(around pc=6bc) read keyboard uart until mouse button is released (WaitBug)
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0x2a23 to port 0x100 (select drive 2)
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0x2a23 to port 0x100 (select drive 2)
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0x2a23 to port 0x100 (select drive 1)
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0x2a23 to port 0x100 (select drive 1)
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0x3a23 to port 0x100 (unset disk separator clear (allow disk head reading))
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0x3a27 to port 0x100 (select disk side 1)
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0x3a07 to port 0x100 (unselect all drives)
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@ -653,8 +684,12 @@ void notetaker_state::machine_start()
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// allocate the DAC timer, and set it to fire NEVER. We'll set it up properly in IPReset.
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m_FIFO_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(notetaker_state::timer_fifoclk),this));
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m_FIFO_timer->adjust(attotime::never);
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// floppy stuff
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m_floppy = NULL;
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// FDC: /DDEN is tied permanently LOW so MFM mode is ALWAYS ON
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m_fdc->dden_w(0);
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// Keyboard UART: /SWE is tied permanently LOW
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m_kbduart->set_input_pin(AY31015_SWE, 0); // status word outputs are permanently enabled (pin 16 SFD(SWE) tied low, active)
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// EIA UART: /SWE is tied permanently LOW
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m_eiauart->set_input_pin(AY31015_SWE, 0); // status word outputs are permanently enabled (pin 16 SFD(SWE) tied low, active)
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// savestate stuff
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// TODO: add me!
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}
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@ -669,11 +704,12 @@ void notetaker_state::machine_reset()
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/* IP Reset; this emulates the IPReset' signal */
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void notetaker_state::ip_reset()
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{
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// not-really-reset related, set line on Keybaord UART
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m_kbduart->set_input_pin(AY31015_SWE, 0); // status word outputs are permanently enabled (pin 16 SFD(SWE) tied low, active)
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// reset the Keyboard UART
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m_kbduart->set_input_pin(AY31015_XR, 0); // MR - pin 21
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m_kbduart->set_input_pin(AY31015_XR, 1); // ''
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// reset the EIA UART
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m_eiauart->set_input_pin(AY31015_XR, 0); // MR - pin 21
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m_eiauart->set_input_pin(AY31015_XR, 1); // ''
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// reset the IPConReg latch at #f1
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m_BootSeqDone = 0;
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m_ProcLock = 0;
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@ -683,6 +719,9 @@ void notetaker_state::ip_reset()
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m_LedInd6 = 0;
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m_LedInd7 = 0;
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m_LedInd8 = 0;
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// Clear the DAC FIFO
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for (int i=0; i<16; i++) m_outfifo[i] = 0;
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m_outfifo_count = m_outfifo_tail_ptr = m_outfifo_head_ptr = 0;
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// reset the FIFOReg latch at #h9
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m_TabletYOn = 0;
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m_TabletXOn = 0;
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@ -692,7 +731,10 @@ void notetaker_state::ip_reset()
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m_SHConB = 0;
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m_SHConA = 0;
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m_SetSH = 0;
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// reset the DiskReg latches at #c4 and #b4 on the disk/display controller board
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// handle consequences of above
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m_FIFO_timer->adjust(attotime::from_hz(((XTAL_960kHz/10)/4)/((m_FrSel0<<3)+(m_FrSel1<<2)+(m_FrSel2<<1)+1))); // FIFO timer is clocked by 960khz divided by 10 (74ls162 decade counter), divided by 4 (mc14568B with divider 1 pins set to 4), divided by 1,3,5,7,9,11,13,15 (or 0,2,4,6,8,10,12,14?)
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// todo: handle tablet and sample/hold stuff as well
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// reset the DiskReg latches at #c4 and #b4 on the disk/display/eia controller board
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m_ADCSpd0 = 0;
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m_ADCSpd1 = 0;
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m_StopWordClock_q = 0;
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@ -709,19 +751,17 @@ void notetaker_state::ip_reset()
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m_SideSelect = 0;
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m_Disk5VOn = 0;
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m_Disk12VOn = 0;
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// Clear the DAC FIFO
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for (int i=0; i<16; i++) m_outfifo[i] = 0;
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m_outfifo_count = m_outfifo_tail_ptr = m_outfifo_head_ptr = 0;
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// Reset the DAC Timer
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m_FIFO_timer->adjust(attotime::from_hz(((XTAL_960kHz/10)/4)/((m_FrSel0<<3)+(m_FrSel1<<2)+(m_FrSel2<<1)+1))); // FIFO timer is clocked by 960khz divided by 10 (74ls162 decade counter), divided by 4 (mc14568B with divider 1 pins set to 4), divided by 1,3,5,7,9,11,13,15 (or 0,2,4,6,8,10,12,14?)
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// stuff on display/eia board also reset by IPReset:
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// handle the consequences of the above.
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// Disk12VOn probably runs the drive motor, and MotorOn is hard-wired to low/active, so turn the motor for all drives OFF
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m_floppy = m_floppy0->get_device();
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m_floppy->mon_w(1);
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//m_floppy = m_floppy1->get_device();
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//m_floppy->mon_w(1);
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//m_floppy = m_floppy2->get_device();
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//m_floppy->mon_w(1);
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m_floppy = nullptr; // select no drive
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// reset the Framebuffer Display Address:
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m_DispAddr = 0;
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// reset the EIA UART
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m_eiauart->set_input_pin(AY31015_XR, 0); // MR - pin 21
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m_eiauart->set_input_pin(AY31015_XR, 1); // ''
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// reset the DiskReg latches at #c4 and #b4 on the disk/display/eia board
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// write me!
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}
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/* EP Reset; this emulates the EPReset' signal */
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