tms32082: Added first few opcodes.

.gitattributes

@@ -876,6 +876,7 @@ src/emu/cpu/tms32051/dis32051.c svneol=native#text/plain
 src/emu/cpu/tms32051/tms32051.c svneol=native#text/plain
 src/emu/cpu/tms32051/tms32051.h svneol=native#text/plain
 src/emu/cpu/tms32082/dis32082.c svneol=native#text/plain
+src/emu/cpu/tms32082/mp_ops.c svneol=native#text/plain
 src/emu/cpu/tms32082/tms32082.c svneol=native#text/plain
 src/emu/cpu/tms32082/tms32082.h svneol=native#text/plain
 src/emu/cpu/tms34010/34010dsm.c svneol=native#text/plain

src/emu/cpu/cpu.mak

@@ -1999,11 +1999,12 @@ $(CPUOBJ)/tms32051/tms32051.o:  $(CPUSRC)/tms32051/tms32051.c \
 
 ifneq ($(filter TMS32082,$(CPUS)),)
 OBJDIRS += $(CPUOBJ)/tms32082
-CPUOBJS += $(CPUOBJ)/tms32082/tms32082.o
+CPUOBJS += $(CPUOBJ)/tms32082/tms32082.o $(CPUOBJ)/tms32082/mp_ops.o
 DASMOBJS += $(CPUOBJ)/tms32082/dis32082.o
 endif
 
 $(CPUOBJ)/tms32082/tms32082.o:  $(CPUSRC)/tms32082/tms32082.c \
+								$(CPUSRC)/tms32082/mp_ops.c \
 								$(CPUSRC)/tms32082/tms32082.h
 
 

src/emu/cpu/tms32082/mp_ops.c

@@ -0,0 +1,123 @@
+// TMS320C82 Master Processor core execution
+
+#include "emu.h"
+#include "tms32082.h"
+
+
+#define OP_LINK() ((m_ir >> 27) & 0x1f)
+#define OP_RD() ((m_ir >> 27) & 0x1f)
+#define OP_RS() ((m_ir >> 22) & 0x1f)
+#define OP_BASE() ((m_ir >> 22) & 0x1f)
+#define OP_SIMM15() ((m_ir & 0x4000) ? (0xffffe000 | (m_ir & 0x7fff)) : (m_ir & 0x7fff))
+#define OP_UIMM15() (m_ir & 0x7fff)
+#define OP_BITNUM() ((m_ir >> 27) & 0x1f)
+
+
+
+void tms32082_mp_device::execute_short_imm()
+{
+	switch ((m_ir >> 15) & 0x7f)
+	{
+		case 0x17:			// or
+		{
+			int rd = OP_RD();
+			int rs = OP_RS();
+			UINT32 imm = OP_UIMM15();
+
+			if (rd)
+				m_reg[rd] = m_reg[rs] | imm;
+			break;
+		}
+
+		case 0x49:			// bbz.a
+		{
+			int bitnum = OP_BITNUM();
+			INT32 offset = OP_SIMM15();
+			int rs = OP_RS();
+
+			if ((m_reg[rs] & (1 << bitnum)) == 0)
+			{
+				m_fetchpc = m_pc + (offset * 4);
+			}
+			break;
+		}
+
+		default:
+			fatalerror("tms32082_mp_device::execute_short_imm(): opcode %08X (%02X)", m_ir, (m_ir >> 15) & 0x7f);
+	}
+}
+
+void tms32082_mp_device::execute_reg_long_imm()
+{
+	UINT32 imm32 = 0;
+
+	if (m_ir & (1 << 12))
+		imm32 = fetch();
+
+	switch ((m_ir >> 12) & 0xff)
+	{
+		case 0x2f:			// or
+		{
+			int rd = OP_RD();
+			int rs = OP_RS();
+
+			if (rd)
+				m_reg[rd] = m_reg[rs] | imm32;
+			break;
+		}
+
+		case 0x43:			// ld.h
+		case 0x4b:
+		{
+			int shift = (m_ir & (1 << 11)) ? 1 : 0;
+			int m = m_ir & (1 << 15);
+
+			int base = OP_BASE();
+			int rd = OP_RD();
+
+			UINT32 address = m_reg[base] + (imm32 << shift);
+			if (rd)
+			{
+				m_reg[rd] = m_program->read_word(address);
+				if (m_reg[rd] & 0x8000)
+					m_reg[rd] |= 0xffff0000;
+			}
+
+			if (m && base)
+				m_reg[base] = address;
+			break;
+		}
+
+		case 0x8b:			// jsr.a
+		{
+			int link = OP_LINK();
+			int base = OP_BASE();
+
+			if (link)
+				m_reg[link] = m_fetchpc;
+
+			m_fetchpc = m_reg[base] + (INT32)(imm32);
+			break;
+		}
+
+		default:
+			fatalerror("tms32082_mp_device::execute_reg_long_imm(): opcode %08X (%02X)", m_ir, (m_ir >> 12) & 0xff);
+	}
+}
+
+
+void tms32082_mp_device::execute()
+{
+	switch ((m_ir >> 20) & 3)
+	{
+		case 0:
+		case 1:
+		case 2:
+			execute_short_imm();
+			break;
+
+		case 3:
+			execute_reg_long_imm();
+			break;
+	}
+}

src/emu/cpu/tms32082/tms32082.c

@@ -81,6 +81,9 @@ void tms32082_mp_device::device_start()
 
 	state_add(STATE_GENPC, "curpc", m_pc).noshow();
 
+	m_program = &space(AS_PROGRAM);
+	m_direct = &m_program->direct();
+
 	m_icountptr = &m_icount;
 }
 
@@ -110,11 +113,25 @@ void tms32082_mp_device::device_reset()
 	m_acc[3] = 0;
 }
 
+UINT32 tms32082_mp_device::fetch()
+{
+	UINT32 w = m_direct->read_decrypted_dword(m_fetchpc);
+	m_fetchpc += 4;
+	return w;
+}
+
 void tms32082_mp_device::execute_run()
 {
-	m_pc = m_fetchpc;
-	debugger_instruction_hook(this, m_pc);
+	while (m_icount > 0)
+	{
+		m_pc = m_fetchpc;
+		debugger_instruction_hook(this, m_pc);
+
+		m_ir = fetch();
+		execute();
+
+		m_icount--;
+	};
 
-	m_icount = 0;
 	return;
 }

src/emu/cpu/tms32082/tms32082.h

@@ -86,10 +86,17 @@ protected:
 	UINT32 m_fetchpc;
 	UINT32 m_reg[32];
 	UINT64 m_acc[4];
+	UINT32 m_ir;
 
 	int m_icount;
 
 	address_space *m_program;
+	direct_read_data* m_direct;
+
+	UINT32 fetch();
+	void execute();
+	void execute_short_imm();
+	void execute_reg_long_imm();
 };
 
 extern const device_type TMS32082_MP;