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https://github.com/holub/mame
synced 2025-10-04 08:28:39 +03:00
Add AMD/Plessey 2812 FIFO device (for WIP Star Rider driver)
This commit is contained in:
Vas Crabb
parent
e837e67101
commit
112062f7bb
@ -177,6 +177,18 @@ if (MACHINES["LSI53C810"]~=null) then
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}
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end
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---------------------------------------------------
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--
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--@src/devices/machine/2812fifo.h,MACHINES["2812FIFO"] = true
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---------------------------------------------------
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if (MACHINES["2812FIFO"]~=null) then
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files {
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MAME_DIR .. "src/devices/machine/2812fifo.cpp",
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MAME_DIR .. "src/devices/machine/2812fifo.h",
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}
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end
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---------------------------------------------------
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--
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--@src/devices/machine/6522via.h,MACHINES["6522VIA"] = true
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@ -371,6 +371,7 @@ MACHINES["DMAC"] = true
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MACHINES["GAYLE"] = true
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MACHINES["NCR53C7XX"] = true
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MACHINES["LSI53C810"] = true
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MACHINES["2812FIFO"] = true
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MACHINES["6522VIA"] = true
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MACHINES["TPI6525"] = true
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MACHINES["RIOT6532"] = true
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235
src/devices/machine/2812fifo.cpp
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235
src/devices/machine/2812fifo.cpp
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@ -0,0 +1,235 @@
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// license:BSD-3-Clause
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// copyright-holders:Vas Crabb
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/**************************************************************************
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2812 32*8 First-In First-Out Memory (AMD, Plessey, and others)
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These devices contain a file of 32 data registers and corresponding
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control registers indicating when the data registers are valid.
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Data ripples from the input register towards the output until it
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reaches a register containing valid data. The first and last data
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registers support serial operation.
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The half-full flag responds to the number of valid locations. It
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favours glitch-free operation over precision. It's never asserted
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when fewer than 13 registers are valid, and it's always asserted
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when at least 16 registers are valid.
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TODO:
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* Propagation delays
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* Serial I/O
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* Am2813 32*9 version without serial I/O
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**************************************************************************/
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#include "emu.h"
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#include "2812fifo.h"
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#include <algorithm>
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#include <cassert>
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DEFINE_DEVICE_TYPE(FIFO2812, fifo2812_device, "fifo2812", "2812 32*8 FIFO Memory");
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fifo2812_device::fifo2812_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock) :
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device_t(mconfig, FIFO2812, tag, owner, clock),
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m_q_cb(*this),
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m_ir_cb(*this),
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m_or_cb(*this),
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m_flag_cb(*this),
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m_control(0U),
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m_count(0U),
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m_d(0U), m_mr(1U), m_pl(0U), m_pd(0U), m_oe(1U)
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{
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std::fill(std::begin(m_data), std::end(m_data), 0U);
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}
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WRITE_LINE_MEMBER(fifo2812_device::mr_w)
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{
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if (bool(state) != bool(m_mr))
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{
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m_mr = state ? 1U : 0U;
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if (!m_mr)
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device_reset();
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}
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}
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WRITE_LINE_MEMBER(fifo2812_device::pl_w)
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{
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if (bool(state) != bool(m_pl))
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{
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m_pl = state ? 1U : 0U;
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if (m_mr)
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{
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if (m_pl)
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{
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m_data[0] = m_d;
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if (!BIT(m_control, 0))
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{
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m_control |= u32(1) << 0;
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m_ir_cb(1);
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if (15U == ++m_count)
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m_flag_cb(1);
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}
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}
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else if (BIT(m_control, 0) && !BIT(m_control, 1))
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{
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unsigned bit(1);
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m_data[bit] = m_data[bit - 1];
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m_control |= u32(1) << bit;
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m_control &= ~(u32(1) << (bit - 1));
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m_ir_cb(0);
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for (++bit; ((LENGTH - 1) > bit) && !BIT(m_control, bit); ++bit)
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{
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m_data[bit] = m_data[bit - 1];
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m_control |= u32(1) << bit;
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m_control &= ~(u32(1) << (bit - 1));
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}
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if (!m_pd && ((LENGTH - 1) == bit) && !BIT(m_control, bit))
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{
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if (m_data[bit] != m_data[bit - 1])
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{
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m_data[bit] = m_data[bit - 1];
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if (m_oe)
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m_q_cb(0U, m_data[bit], 0xffU);
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}
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m_control |= u32(1) << bit;
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m_control &= ~(u32(1) << (bit - 1));
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m_or_cb(1);
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}
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}
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}
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}
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}
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WRITE_LINE_MEMBER(fifo2812_device::pd_w)
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{
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if (bool(state) != bool(m_pd))
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{
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m_pd = state ? 1U : 0U;
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if (m_mr)
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{
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if (m_pd)
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{
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if (BIT(m_control, LENGTH - 1))
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{
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m_control &= ~(u32(1) << (LENGTH - 1));
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m_or_cb(0);
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if (15U == m_count--)
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m_flag_cb(0);
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}
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}
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else if (BIT(m_control, LENGTH - 2))
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{
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unsigned bit(LENGTH - 2);
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if (m_data[bit + 1] != m_data[bit])
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{
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m_data[bit + 1] = m_data[bit];
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if (m_oe)
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m_q_cb(0U, m_data[bit + 1], 0xffU);
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}
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m_control |= u32(1) << (bit + 1);
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m_control &= ~(u32(1) << bit);
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m_or_cb(1);
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for (--bit; (0U < bit) && BIT(m_control, bit); --bit)
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{
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m_data[bit + 1] = m_data[bit];
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m_control |= u32(1) << (bit + 1);
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m_control &= ~(u32(1) << bit);
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}
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if (!m_pl && (0U == bit) && BIT(m_control, bit))
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{
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m_data[bit + 1] = m_data[bit];
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m_control |= u32(1) << (bit + 1);
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m_control &= ~(u32(1) << bit);
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m_ir_cb(0);
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}
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}
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}
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}
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}
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WRITE_LINE_MEMBER(fifo2812_device::oe_w)
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{
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if (bool(state) != bool(m_oe))
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{
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m_oe = state ? 1U : 0U;
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if (m_oe)
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m_q_cb(0U, m_data[LENGTH - 1], 0xffU);
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else
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m_q_cb(0U, 0xffU, 0x00U);
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}
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}
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u8 fifo2812_device::read()
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{
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if (machine().side_effects_disabled())
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{
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return m_data[LENGTH - 1];
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}
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else
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{
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assert(!m_pd);
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pd_w(1);
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u8 const data(m_data[LENGTH - 1]);
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pd_w(0);
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return data;
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}
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}
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void fifo2812_device::write(u8 data)
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{
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assert(!m_pl);
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d_w(data);
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pl_w(1);
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pl_w(0);
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}
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void fifo2812_device::device_resolve_objects()
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{
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m_q_cb.resolve_safe();
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m_ir_cb.resolve_safe();
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m_or_cb.resolve_safe();
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m_flag_cb.resolve_safe();
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m_d = 0U;
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m_mr = 1U;
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m_pl = 0U;
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m_pd = 0U;
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m_oe = 1U;
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}
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void fifo2812_device::device_start()
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{
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save_item(NAME(m_control));
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save_item(NAME(m_data));
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save_item(NAME(m_count));
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save_item(NAME(m_d));
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save_item(NAME(m_mr));
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save_item(NAME(m_pl));
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save_item(NAME(m_pd));
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save_item(NAME(m_oe));
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}
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void fifo2812_device::device_reset()
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{
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u32 const prev_ir(BIT(m_control, 0));
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u32 const prev_or(BIT(m_control, LENGTH - 1));
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u8 const prev_q(m_data[LENGTH - 1]);
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bool const prev_flag(15U <= m_count);
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m_control = 0U;
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std::fill(std::begin(m_data), std::end(m_data), 0U);
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m_count = 0U;
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if (m_oe && (0U != prev_q))
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m_q_cb(0U, 0U, 0xffU);
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if (prev_ir)
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m_ir_cb(0);
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if (prev_or)
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m_or_cb(0);
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if (prev_flag)
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m_flag_cb(0);
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}
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84
src/devices/machine/2812fifo.h
Normal file
84
src/devices/machine/2812fifo.h
Normal file
@ -0,0 +1,84 @@
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// license:BSD-3-Clause
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// copyright-holders:Vas Crabb
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/**************************************************************************
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2812 32*8 First-In First-Out Memory (AMD, Plessey, and others)
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____ ____
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D0 1 |* \_/ | 28 D1
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Vgg 2 | | 27 D2
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OR 3 | | 26 D3
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/MR 4 | | 25 /IR
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PD 5 | | 24 Vss
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SD 6 | | 23 D4
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Q0 7 | 2812 | 22 D5
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Q1 8 | | 21 D6
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Q2 9 | | 20 D7
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Q3 10 | | 19 FLAG
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OE 11 | | 18 PL
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Q4 12 | | 17 SL
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Q5 13 | | 16 Vdd
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Q6 14 |___________| 15 Q7
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**************************************************************************/
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#ifndef MAME_MACHINE_2812FIFO_H
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#define MAME_MACHINE_2812FIFO_H
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#pragma once
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#include <array>
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class fifo2812_device : public device_t
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{
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public:
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// standard constructor
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fifo2812_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock = 0);
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// callbacks
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auto q_cb() { return m_q_cb.bind(); }
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auto ir_cb() { return m_ir_cb.bind(); }
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auto or_cb() { return m_or_cb.bind(); }
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auto flag_cb() { return m_flag_cb.bind(); }
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// control signal interface
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void d_w(u8 data) { m_d = data; }
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DECLARE_WRITE_LINE_MEMBER(mr_w);
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DECLARE_WRITE_LINE_MEMBER(pl_w);
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DECLARE_WRITE_LINE_MEMBER(pd_w);
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DECLARE_WRITE_LINE_MEMBER(oe_w);
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u8 q_r() const { return m_oe ? m_data[LENGTH - 1] : 0xff; }
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DECLARE_READ_LINE_MEMBER(ir_r) const { return BIT(m_control, 0); }
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DECLARE_READ_LINE_MEMBER(or_r) const { return BIT(m_control, LENGTH - 1); }
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DECLARE_READ_LINE_MEMBER(flag_r);
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// read/write interface
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u8 read();
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void write(u8 data);
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protected:
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// device_t implementation
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virtual void device_resolve_objects() override;
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virtual void device_start() override;
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virtual void device_reset() override;
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private:
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enum { LENGTH = 32 };
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// output callbacks
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devcb_write8 m_q_cb;
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devcb_write_line m_ir_cb;
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devcb_write_line m_or_cb;
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devcb_write_line m_flag_cb;
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// registers/state
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u32 m_control;
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std::array<u8, LENGTH> m_data;
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u8 m_count;
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// input line states
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u8 m_d, m_mr, m_pl, m_pd, m_oe;
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};
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DECLARE_DEVICE_TYPE(FIFO2812, fifo2812_device)
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#endif // MAME_MACHINE_2812FIFO_H
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@ -660,10 +660,6 @@ void ptm6840_device::set_gate(int idx, int state)
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m_gate[idx] = state;
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}
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WRITE_LINE_MEMBER( ptm6840_device::set_g1 ) { set_gate(0, state); }
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WRITE_LINE_MEMBER( ptm6840_device::set_g2 ) { set_gate(1, state); }
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WRITE_LINE_MEMBER( ptm6840_device::set_g3 ) { set_gate(2, state); }
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//-------------------------------------------------
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// set_clock - set clock status (0 or 1)
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@ -682,10 +678,6 @@ void ptm6840_device::set_clock(int idx, int state)
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}
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}
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WRITE_LINE_MEMBER( ptm6840_device::set_c1 ) { set_clock(0, state); }
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WRITE_LINE_MEMBER( ptm6840_device::set_c2 ) { set_clock(1, state); }
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WRITE_LINE_MEMBER( ptm6840_device::set_c3 ) { set_clock(2, state); }
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//-------------------------------------------------
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// set_ext_clock - set external clock frequency
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@ -43,14 +43,14 @@ public:
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uint8_t read(offs_t offset);
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void set_gate(int idx, int state);
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DECLARE_WRITE_LINE_MEMBER( set_g1 );
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DECLARE_WRITE_LINE_MEMBER( set_g2 );
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DECLARE_WRITE_LINE_MEMBER( set_g3 );
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DECLARE_WRITE_LINE_MEMBER( set_g1 ) { set_gate(0, state); }
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DECLARE_WRITE_LINE_MEMBER( set_g2 ) { set_gate(1, state); }
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DECLARE_WRITE_LINE_MEMBER( set_g3 ) { set_gate(2, state); }
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void set_clock(int idx, int state);
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DECLARE_WRITE_LINE_MEMBER( set_c1 );
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DECLARE_WRITE_LINE_MEMBER( set_c2 );
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DECLARE_WRITE_LINE_MEMBER( set_c3 );
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DECLARE_WRITE_LINE_MEMBER( set_c1 ) { set_clock(0, state); }
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DECLARE_WRITE_LINE_MEMBER( set_c2 ) { set_clock(1, state); }
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DECLARE_WRITE_LINE_MEMBER( set_c3 ) { set_clock(2, state); }
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void update_interrupts();
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