mirror of
https://github.com/holub/mame
synced 2025-04-20 07:22:04 +03:00
drivers starting with letters: removed read* and write* macros (nw)
This commit is contained in:
parent
760977494c
commit
11723fc8a3
@ -105,7 +105,7 @@ void _8080bw_state::invaders_samples_audio(machine_config &config)
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/* */
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/*******************************************************/
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WRITE8_MEMBER(_8080bw_state::invadpt2_sh_port_1_w)
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void _8080bw_state::invadpt2_sh_port_1_w(uint8_t data)
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{
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uint8_t rising_bits = data & ~m_port_1_last_extra;
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@ -123,7 +123,7 @@ WRITE8_MEMBER(_8080bw_state::invadpt2_sh_port_1_w)
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m_port_1_last_extra = data;
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}
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WRITE8_MEMBER(_8080bw_state::invadpt2_sh_port_2_w)
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void _8080bw_state::invadpt2_sh_port_2_w(uint8_t data)
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{
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/* FLEET (movement)
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@ -154,7 +154,7 @@ WRITE8_MEMBER(_8080bw_state::invadpt2_sh_port_2_w)
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/* */
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/*******************************************************/
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WRITE8_MEMBER(_8080bw_state::spacerng_sh_port_2_w)
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void _8080bw_state::spacerng_sh_port_2_w(uint8_t data)
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{
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uint8_t rising_bits = data & ~m_port_2_last_extra;
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@ -175,7 +175,7 @@ WRITE8_MEMBER(_8080bw_state::spacerng_sh_port_2_w)
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/* */
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/*******************************************************/
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WRITE8_MEMBER(_8080bw_state::spcewars_sh_port_w)
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void _8080bw_state::spcewars_sh_port_w(uint8_t data)
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{
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uint8_t rising_bits = data & ~m_port_1_last_extra;
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@ -213,7 +213,7 @@ const char *const lrescue_sample_names[] =
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nullptr
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};
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WRITE8_MEMBER(_8080bw_state::lrescue_sh_port_1_w)
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void _8080bw_state::lrescue_sh_port_1_w(uint8_t data)
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{
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uint8_t rising_bits = data & ~m_port_1_last_extra;
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@ -230,7 +230,7 @@ WRITE8_MEMBER(_8080bw_state::lrescue_sh_port_1_w)
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m_port_1_last_extra = data;
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}
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WRITE8_MEMBER(_8080bw_state::lrescue_sh_port_2_w)
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void _8080bw_state::lrescue_sh_port_2_w(uint8_t data)
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{
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uint8_t rising_bits = data & ~m_port_2_last_extra;
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@ -256,10 +256,10 @@ WRITE8_MEMBER(_8080bw_state::lrescue_sh_port_2_w)
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/* */
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/*******************************************************/
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WRITE8_MEMBER(_8080bw_state::cosmo_sh_port_2_w)
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void _8080bw_state::cosmo_sh_port_2_w(uint8_t data)
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{
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/* inverted flip screen bit */
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invadpt2_sh_port_2_w(space, offset, data ^ 0x20);
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invadpt2_sh_port_2_w(data ^ 0x20);
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}
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@ -315,12 +315,12 @@ DISCRETE_SOUND_START(ballbomb_discrete)
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DISCRETE_SOUND_END
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WRITE8_MEMBER( _8080bw_state::ballbomb_01_w )
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void _8080bw_state::ballbomb_01_w(uint8_t data)
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{
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m_discrete->write(BALLBOMB_MUSIC_DATA, data|0x80);
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}
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WRITE8_MEMBER(_8080bw_state::ballbomb_sh_port_1_w)
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void _8080bw_state::ballbomb_sh_port_1_w(uint8_t data)
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{
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uint8_t rising_bits = data & ~m_port_1_last_extra;
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@ -337,7 +337,7 @@ WRITE8_MEMBER(_8080bw_state::ballbomb_sh_port_1_w)
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m_port_1_last_extra = data;
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}
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WRITE8_MEMBER(_8080bw_state::ballbomb_sh_port_2_w)
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void _8080bw_state::ballbomb_sh_port_2_w(uint8_t data)
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{
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uint8_t rising_bits = data & ~m_port_2_last_extra;
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@ -395,7 +395,7 @@ DISCRETE_SOUND_START(indianbt_discrete)
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DISCRETE_SOUND_END
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WRITE8_MEMBER(_8080bw_state::indianbt_sh_port_1_w)
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void _8080bw_state::indianbt_sh_port_1_w(uint8_t data)
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{
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/* bit 4 occurs every 5.25 seconds during gameplay */
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uint8_t rising_bits = data & ~m_port_1_last_extra;
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@ -410,7 +410,7 @@ WRITE8_MEMBER(_8080bw_state::indianbt_sh_port_1_w)
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m_port_1_last_extra = data;
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}
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WRITE8_MEMBER(_8080bw_state::indianbt_sh_port_2_w)
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void _8080bw_state::indianbt_sh_port_2_w(uint8_t data)
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{
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uint8_t rising_bits = data & ~m_port_2_last_extra;
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@ -424,12 +424,12 @@ WRITE8_MEMBER(_8080bw_state::indianbt_sh_port_2_w)
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m_port_2_last_extra = data;
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}
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WRITE8_MEMBER(_8080bw_state::indianbt_sh_port_3_w)
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void _8080bw_state::indianbt_sh_port_3_w(uint8_t data)
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{
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m_discrete->write(INDIANBT_MUSIC_DATA, data);
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}
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WRITE8_MEMBER(_8080bw_state::indianbtbr_sh_port_1_w)
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void _8080bw_state::indianbtbr_sh_port_1_w(uint8_t data)
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{
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uint8_t rising_bits = data & ~m_port_1_last_extra;
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@ -442,7 +442,7 @@ WRITE8_MEMBER(_8080bw_state::indianbtbr_sh_port_1_w)
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m_port_1_last_extra = data;
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}
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WRITE8_MEMBER(_8080bw_state::indianbtbr_sh_port_2_w)
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void _8080bw_state::indianbtbr_sh_port_2_w(uint8_t data)
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{
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uint8_t rising_bits = data & ~m_port_2_last_extra;
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@ -768,12 +768,12 @@ DISCRETE_SOUND_START(polaris_discrete)
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DISCRETE_SOUND_END
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WRITE8_MEMBER(_8080bw_state::polaris_sh_port_1_w)
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void _8080bw_state::polaris_sh_port_1_w(uint8_t data)
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{
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m_discrete->write(POLARIS_MUSIC_DATA, data);
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}
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WRITE8_MEMBER(_8080bw_state::polaris_sh_port_2_w)
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void _8080bw_state::polaris_sh_port_2_w(uint8_t data)
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{
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/* 0x01 - SX0 - Shot */
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m_discrete->write(POLARIS_SX0_EN, data & 0x01);
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@ -793,7 +793,7 @@ WRITE8_MEMBER(_8080bw_state::polaris_sh_port_2_w)
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m_discrete->write(POLARIS_SX5_EN, data & 0x20);
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}
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WRITE8_MEMBER(_8080bw_state::polaris_sh_port_3_w)
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void _8080bw_state::polaris_sh_port_3_w(uint8_t data)
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{
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machine().bookkeeping().coin_lockout_global_w(data & 0x04); /* SX8 */
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@ -920,7 +920,7 @@ static const double schaser_effect_rc[8] =
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(1.0/ (1.0/RES_K(15) + 1.0/RES_K(39) + 1.0/RES_K(82)) + RES_K(20)) * CAP_U(1)
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};
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WRITE8_MEMBER(_8080bw_state::schaser_sh_port_1_w)
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void _8080bw_state::schaser_sh_port_1_w(uint8_t data)
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{
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int effect;
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@ -987,7 +987,7 @@ WRITE8_MEMBER(_8080bw_state::schaser_sh_port_1_w)
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m_sn->mixer_b_w(m_schaser_explosion);
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}
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WRITE8_MEMBER(_8080bw_state::schaser_sh_port_2_w)
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void _8080bw_state::schaser_sh_port_2_w(uint8_t data)
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{
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/* bit 0 - Music (DAC) (SX6)
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bit 1 - Sound Enable (SX7)
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@ -1039,9 +1039,8 @@ TIMER_DEVICE_CALLBACK_MEMBER(_8080bw_state::schaser_effect_555_cb)
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void _8080bw_state::schaser_reinit_555_time_remain()
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{
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address_space &space = m_maincpu->space(AS_PROGRAM);
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m_schaser_effect_555_time_remain = attotime::from_double(m_schaser_effect_555_time_remain_savable);
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schaser_sh_port_2_w(space, 0, m_port_2_last_extra);
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schaser_sh_port_2_w(m_port_2_last_extra);
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}
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@ -1057,12 +1056,10 @@ MACHINE_START_MEMBER(_8080bw_state,schaser_sh)
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MACHINE_RESET_MEMBER(_8080bw_state,schaser_sh)
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{
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address_space &space = m_maincpu->space(AS_PROGRAM);
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m_schaser_effect_555_is_low = 0;
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m_schaser_effect_555_timer->adjust(attotime::never);
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schaser_sh_port_1_w(space, 0, 0);
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schaser_sh_port_2_w(space, 0, 0);
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schaser_sh_port_1_w(0);
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schaser_sh_port_2_w(0);
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m_schaser_effect_555_time_remain = attotime::zero;
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m_schaser_effect_555_time_remain_savable = m_schaser_effect_555_time_remain.as_double();
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}
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@ -1075,12 +1072,12 @@ MACHINE_RESET_MEMBER(_8080bw_state,schaser_sh)
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/* */
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/*******************************************************/
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WRITE8_MEMBER(_8080bw_state::invrvnge_port03_w)
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void _8080bw_state::invrvnge_port03_w(uint8_t data)
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{
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m_sound_data = data;
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}
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WRITE8_MEMBER(_8080bw_state::invrvnge_port05_w)
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void _8080bw_state::invrvnge_port05_w(uint8_t data)
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{
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/*
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00 - normal play
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@ -1109,7 +1106,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(_8080bw_state::nmi_timer)
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/* - Press Left or Right to choose game to play */
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/****************************************************/
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WRITE8_MEMBER(_8080bw_state::rollingc_sh_port_w)
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void _8080bw_state::rollingc_sh_port_w(uint8_t data)
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{
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uint8_t rising_bits = data & ~m_port_3_last_extra;
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@ -1140,12 +1137,12 @@ const char *const lupin3_sample_names[] =
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nullptr
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};
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WRITE8_MEMBER( _8080bw_state::lupin3_00_w )
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void _8080bw_state::lupin3_00_w (uint8_t data)
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{
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m_discrete->write(INDIANBT_MUSIC_DATA, data);
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}
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WRITE8_MEMBER(_8080bw_state::lupin3_sh_port_1_w)
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void _8080bw_state::lupin3_sh_port_1_w(uint8_t data)
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{
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uint8_t rising_bits = data & ~m_port_1_last_extra;
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static uint8_t lupin3_step = 2;
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@ -1169,7 +1166,7 @@ WRITE8_MEMBER(_8080bw_state::lupin3_sh_port_1_w)
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m_port_1_last_extra = data;
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}
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WRITE8_MEMBER(_8080bw_state::lupin3_sh_port_2_w)
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void _8080bw_state::lupin3_sh_port_2_w(uint8_t data)
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{
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uint8_t rising_bits = data & ~m_port_2_last_extra;
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@ -1193,7 +1190,7 @@ WRITE8_MEMBER(_8080bw_state::lupin3_sh_port_2_w)
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/* Much more work needs to be done */
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/*****************************************/
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WRITE8_MEMBER(_8080bw_state::schasercv_sh_port_1_w)
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void _8080bw_state::schasercv_sh_port_1_w(uint8_t data)
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{
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/* bit 2 = 2nd speedup
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bit 3 = 1st speedup
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@ -1207,7 +1204,7 @@ WRITE8_MEMBER(_8080bw_state::schasercv_sh_port_1_w)
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m_port_1_last_extra = data;
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}
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WRITE8_MEMBER(_8080bw_state::schasercv_sh_port_2_w)
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void _8080bw_state::schasercv_sh_port_2_w(uint8_t data)
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{
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m_speaker->level_w(BIT(data, 0)); /* End-of-Level */
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@ -1223,7 +1220,7 @@ WRITE8_MEMBER(_8080bw_state::schasercv_sh_port_2_w)
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/* Much more work needs to be done */
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/*****************************************/
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WRITE8_MEMBER(_8080bw_state::crashrd_port03_w)
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void _8080bw_state::crashrd_port03_w(uint8_t data)
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{
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int effect;
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@ -1287,7 +1284,7 @@ WRITE8_MEMBER(_8080bw_state::crashrd_port03_w)
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m_sn->mixer_b_w(m_schaser_explosion);
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}
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WRITE8_MEMBER(_8080bw_state::crashrd_port05_w)
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void _8080bw_state::crashrd_port05_w(uint8_t data)
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{
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// bit 0 = bitstream audio
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// bit 4 = not sure
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@ -1301,7 +1298,7 @@ WRITE8_MEMBER(_8080bw_state::crashrd_port05_w)
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/* No information available as what the correct sounds are */
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/*******************************************************************/
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WRITE8_MEMBER(_8080bw_state::yosakdon_sh_port_1_w)
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void _8080bw_state::yosakdon_sh_port_1_w(uint8_t data)
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{
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uint8_t rising_bits = data & ~m_port_1_last_extra;
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@ -1316,7 +1313,7 @@ WRITE8_MEMBER(_8080bw_state::yosakdon_sh_port_1_w)
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m_port_1_last_extra = data;
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}
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WRITE8_MEMBER(_8080bw_state::yosakdon_sh_port_2_w)
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void _8080bw_state::yosakdon_sh_port_2_w(uint8_t data)
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{
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uint8_t rising_bits = data & ~m_port_2_last_extra;
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@ -1339,7 +1336,7 @@ WRITE8_MEMBER(_8080bw_state::yosakdon_sh_port_2_w)
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/* Proper samples are unavailable */
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/*****************************************/
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WRITE8_MEMBER(_8080bw_state::shuttlei_sh_port_1_w)
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void _8080bw_state::shuttlei_sh_port_1_w(uint8_t data)
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{
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/* bit 3 is high while you are alive and playing */
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uint8_t rising_bits = data & ~m_port_1_last_extra;
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@ -1352,7 +1349,7 @@ WRITE8_MEMBER(_8080bw_state::shuttlei_sh_port_1_w)
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m_port_1_last_extra = data;
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}
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WRITE8_MEMBER(_8080bw_state::shuttlei_sh_port_2_w)
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void _8080bw_state::shuttlei_sh_port_2_w(uint8_t data)
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{
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switch (data)
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{
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@ -1380,12 +1377,12 @@ WRITE8_MEMBER(_8080bw_state::shuttlei_sh_port_2_w)
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/* Proper samples are unavailable */
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/*****************************************/
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WRITE8_MEMBER( _8080bw_state::darthvdr_00_w )
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void _8080bw_state::darthvdr_00_w(uint8_t data)
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{
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m_flip_screen = BIT(data, 0) & ioport(CABINET_PORT_TAG)->read();
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}
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WRITE8_MEMBER( _8080bw_state::darthvdr_08_w )
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void _8080bw_state::darthvdr_08_w(uint8_t data)
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{
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uint8_t rising_bits = data & ~m_port_1_last_extra;
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@ -86,7 +86,7 @@ constexpr XTAL AUDIO_CLOCK_1942P(MASTER_CLOCK_1942P/16);
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} // anonymous namespace
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WRITE8_MEMBER(_1942_state::_1942_bankswitch_w)
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void _1942_state::_1942_bankswitch_w(uint8_t data)
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{
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membank("bank1")->set_entry(data & 0x03);
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}
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@ -137,12 +137,12 @@ void _1942_state::_1942_map(address_map &map)
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map(0xe000, 0xefff).ram();
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}
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WRITE8_MEMBER(_1942p_state::_1942p_f600_w)
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void _1942p_state::_1942p_f600_w(uint8_t data)
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{
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// printf("_1942p_f600_w %02x\n", data);
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}
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WRITE8_MEMBER(_1942p_state::_1942p_palette_w)
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void _1942p_state::_1942p_palette_w(offs_t offset, uint8_t data)
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{
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m_protopal[offset] = data;
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@ -112,7 +112,7 @@ Graphics: CY37256P160-83AC x 2 (Ultra37000 CPLD family - 160 pin TQFP, 256 Macro
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*
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*************************************/
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WRITE8_MEMBER(_20pacgal_state::irqack_w)
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void _20pacgal_state::irqack_w(uint8_t data)
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{
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m_irq_mask = data & 1;
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@ -120,7 +120,7 @@ WRITE8_MEMBER(_20pacgal_state::irqack_w)
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m_maincpu->set_input_line(0, CLEAR_LINE);
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}
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WRITE8_MEMBER(_20pacgal_state::timer_pulse_w)
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void _20pacgal_state::timer_pulse_w(uint8_t data)
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{
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//printf("timer pulse %02x\n", data);
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}
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@ -131,7 +131,7 @@ WRITE8_MEMBER(_20pacgal_state::timer_pulse_w)
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*
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*************************************/
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WRITE8_MEMBER(_20pacgal_state::_20pacgal_coin_counter_w)
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void _20pacgal_state::_20pacgal_coin_counter_w(uint8_t data)
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{
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machine().bookkeeping().coin_counter_w(0, data & 1);
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}
|
||||
@ -144,7 +144,7 @@ WRITE8_MEMBER(_20pacgal_state::_20pacgal_coin_counter_w)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
WRITE8_MEMBER(_20pacgal_state::ram_bank_select_w)
|
||||
void _20pacgal_state::ram_bank_select_w(uint8_t data)
|
||||
{
|
||||
if (m_game_selected != (data & 1))
|
||||
{
|
||||
@ -154,7 +154,7 @@ WRITE8_MEMBER(_20pacgal_state::ram_bank_select_w)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(_20pacgal_state::ram_48000_w)
|
||||
void _20pacgal_state::ram_48000_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
if (m_game_selected)
|
||||
{
|
||||
@ -171,17 +171,17 @@ WRITE8_MEMBER(_20pacgal_state::ram_48000_w)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
WRITE8_MEMBER(_20pacgal_state::sprite_gfx_w)
|
||||
void _20pacgal_state::sprite_gfx_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
m_sprite_gfx_ram[offset] = data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(_20pacgal_state::sprite_ram_w)
|
||||
void _20pacgal_state::sprite_ram_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
m_sprite_ram[offset] = data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(_20pacgal_state::sprite_lookup_w)
|
||||
void _20pacgal_state::sprite_lookup_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
m_sprite_color_lookup[offset] = data;
|
||||
}
|
||||
@ -233,7 +233,7 @@ void _20pacgal_state::_20pacgal_map(address_map &map)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
READ8_MEMBER( _25pacman_state::_25pacman_io_87_r )
|
||||
uint8_t _25pacman_state::_25pacman_io_87_r()
|
||||
{
|
||||
return 0xff;
|
||||
}
|
||||
|
@ -234,14 +234,14 @@ Notes - Has jumper setting for 122HZ or 61HZ)
|
||||
|
||||
|
||||
#if 0
|
||||
WRITE8_MEMBER(fortyl_state::fortyl_coin_counter_w)
|
||||
void fortyl_state::fortyl_coin_counter_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
machine().bookkeeping().coin_counter_w(offset,data);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
WRITE8_MEMBER(fortyl_state::bank_select_w)
|
||||
void fortyl_state::bank_select_w(uint8_t data)
|
||||
{
|
||||
if ((data != 0x02) && (data != 0xfd))
|
||||
{
|
||||
@ -252,7 +252,7 @@ WRITE8_MEMBER(fortyl_state::bank_select_w)
|
||||
membank("bank1")->set_entry(data & 1);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(fortyl_state::pix1_w)
|
||||
void fortyl_state::pix1_w(uint8_t data)
|
||||
{
|
||||
// if (data > 7)
|
||||
// logerror("pix1 = %2x\n", data);
|
||||
@ -260,7 +260,7 @@ WRITE8_MEMBER(fortyl_state::pix1_w)
|
||||
m_pix1 = data;
|
||||
}
|
||||
|
||||
READ8_MEMBER(fortyl_state::fortyl_mcu_status_r)
|
||||
uint8_t fortyl_state::fortyl_mcu_status_r()
|
||||
{
|
||||
// bit 0 = when 1, MCU is ready to receive data from main CPU
|
||||
// bit 1 = when 1, MCU has sent data to the main CPU
|
||||
@ -269,7 +269,7 @@ READ8_MEMBER(fortyl_state::fortyl_mcu_status_r)
|
||||
((CLEAR_LINE != m_bmcu->mcu_semaphore_r()) ? 0x02 : 0x00);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(fortyl_state::pix1_mcu_w)
|
||||
void fortyl_state::pix1_mcu_w(uint8_t data)
|
||||
{
|
||||
// if (data > 7)
|
||||
// logerror("pix1 = %2x\n", data);
|
||||
@ -277,7 +277,7 @@ WRITE8_MEMBER(fortyl_state::pix1_mcu_w)
|
||||
m_pix1 = data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(fortyl_state::pix2_w)
|
||||
void fortyl_state::pix2_w(uint8_t data)
|
||||
{
|
||||
// if ((data!=0x00) && (data != 0xff))
|
||||
// logerror("pix2 = %2x\n", data);
|
||||
@ -287,13 +287,13 @@ WRITE8_MEMBER(fortyl_state::pix2_w)
|
||||
}
|
||||
|
||||
#if 0
|
||||
READ8_MEMBER(fortyl_state::pix1_r)
|
||||
uint8_t fortyl_state::pix1_r()
|
||||
{
|
||||
return m_pix1;
|
||||
}
|
||||
#endif
|
||||
|
||||
READ8_MEMBER(fortyl_state::pix2_r)
|
||||
uint8_t fortyl_state::pix2_r()
|
||||
{
|
||||
int res;
|
||||
int d1 = m_pix1 & 7;
|
||||
@ -319,7 +319,7 @@ void fortyl_state::driver_init()
|
||||
|
||||
/***************************************************************************/
|
||||
|
||||
READ8_MEMBER(fortyl_state::snd_flag_r)
|
||||
uint8_t fortyl_state::snd_flag_r()
|
||||
{
|
||||
return (m_soundlatch2->pending_r() ? 2 : 0) | 0xfd;
|
||||
}
|
||||
|
@ -163,12 +163,12 @@
|
||||
* Custom Handlers *
|
||||
***********************************/
|
||||
|
||||
WRITE8_MEMBER(_4enraya_state::sound_data_w)
|
||||
void _4enraya_state::sound_data_w(uint8_t data)
|
||||
{
|
||||
m_soundlatch = data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(_4enraya_state::sound_control_w)
|
||||
void _4enraya_state::sound_control_w(uint8_t data)
|
||||
{
|
||||
// BDIR must be high
|
||||
if (~data & 4)
|
||||
@ -192,7 +192,7 @@ WRITE8_MEMBER(_4enraya_state::sound_control_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER(_4enraya_state::fenraya_custom_map_r)
|
||||
uint8_t _4enraya_state::fenraya_custom_map_r(offs_t offset)
|
||||
{
|
||||
uint8_t prom_routing = (m_prom[offset >> 12] & 0xf) ^ 0xf;
|
||||
uint8_t res = 0;
|
||||
@ -220,7 +220,7 @@ READ8_MEMBER(_4enraya_state::fenraya_custom_map_r)
|
||||
return res;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(_4enraya_state::fenraya_custom_map_w)
|
||||
void _4enraya_state::fenraya_custom_map_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
uint8_t prom_routing = (m_prom[offset >> 12] & 0xf) ^ 0xf;
|
||||
|
||||
@ -241,7 +241,7 @@ WRITE8_MEMBER(_4enraya_state::fenraya_custom_map_w)
|
||||
|
||||
if (prom_routing & 8) // gfx control / RAM wait
|
||||
{
|
||||
fenraya_videoram_w(space, offset & 0xfff, data);
|
||||
fenraya_videoram_w(offset & 0xfff, data);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -852,7 +852,7 @@ void _8080bw_state::init_spacecom()
|
||||
/* */
|
||||
/*******************************************************/
|
||||
|
||||
READ8_MEMBER(_8080bw_state::invrvnge_02_r)
|
||||
uint8_t _8080bw_state::invrvnge_02_r()
|
||||
{
|
||||
uint8_t data = ioport("IN2")->read();
|
||||
if (m_flip_screen) return data;
|
||||
@ -1332,22 +1332,22 @@ INPUT_PORTS_END
|
||||
/* */
|
||||
/*******************************************************/
|
||||
|
||||
READ8_MEMBER(_8080bw_state::rollingc_scattered_colorram_r)
|
||||
uint8_t _8080bw_state::rollingc_scattered_colorram_r(offs_t offset)
|
||||
{
|
||||
return m_scattered_colorram[(offset & 0x1f) | ((offset & 0x1f00) >> 3)];
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(_8080bw_state::rollingc_scattered_colorram_w)
|
||||
void _8080bw_state::rollingc_scattered_colorram_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
m_scattered_colorram[(offset & 0x1f) | ((offset & 0x1f00) >> 3)] = data;
|
||||
}
|
||||
|
||||
READ8_MEMBER(_8080bw_state::rollingc_scattered_colorram2_r)
|
||||
uint8_t _8080bw_state::rollingc_scattered_colorram2_r(offs_t offset)
|
||||
{
|
||||
return m_scattered_colorram2[(offset & 0x1f) | ((offset & 0x1f00) >> 3)];
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(_8080bw_state::rollingc_scattered_colorram2_w)
|
||||
void _8080bw_state::rollingc_scattered_colorram2_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
m_scattered_colorram2[(offset & 0x1f) | ((offset & 0x1f00) >> 3)] = data;
|
||||
}
|
||||
@ -1429,12 +1429,12 @@ void _8080bw_state::rollingc(machine_config &config)
|
||||
/*******************************************************/
|
||||
|
||||
|
||||
READ8_MEMBER(_8080bw_state::schaser_scattered_colorram_r)
|
||||
uint8_t _8080bw_state::schaser_scattered_colorram_r(offs_t offset)
|
||||
{
|
||||
return m_scattered_colorram[(offset & 0x1f) | ((offset & 0x1f80) >> 2)];
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(_8080bw_state::schaser_scattered_colorram_w)
|
||||
void _8080bw_state::schaser_scattered_colorram_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
m_scattered_colorram[(offset & 0x1f) | ((offset & 0x1f80) >> 2)] = data;
|
||||
}
|
||||
@ -1596,7 +1596,7 @@ void _8080bw_state::schaser(machine_config &config)
|
||||
/*******************************************************/
|
||||
|
||||
|
||||
READ8_MEMBER(_8080bw_state::schasercv_02_r)
|
||||
uint8_t _8080bw_state::schasercv_02_r()
|
||||
{
|
||||
uint8_t data = ioport("IN2")->read();
|
||||
if (m_flip_screen) return data;
|
||||
@ -1978,7 +1978,7 @@ MACHINE_START_MEMBER(_8080bw_state,polaris)
|
||||
save_item(NAME(m_polaris_cloud_pos));
|
||||
}
|
||||
|
||||
READ8_MEMBER(_8080bw_state::polaris_port00_r)
|
||||
uint8_t _8080bw_state::polaris_port00_r()
|
||||
{
|
||||
uint8_t data = ioport("IN0")->read();
|
||||
if (m_flip_screen) return data;
|
||||
@ -2394,7 +2394,7 @@ INPUT_PORTS_END
|
||||
|
||||
*/
|
||||
|
||||
READ8_MEMBER(_8080bw_state::indianbt_r)
|
||||
uint8_t _8080bw_state::indianbt_r()
|
||||
{
|
||||
switch(m_maincpu->pc())
|
||||
{
|
||||
@ -2405,7 +2405,7 @@ READ8_MEMBER(_8080bw_state::indianbt_r)
|
||||
return machine().rand();
|
||||
}
|
||||
|
||||
READ8_MEMBER(_8080bw_state::indianbtbr_01_r)
|
||||
uint8_t _8080bw_state::indianbtbr_01_r()
|
||||
{
|
||||
uint8_t data = ioport("IN1")->read();
|
||||
if (!m_flip_screen) return data;
|
||||
@ -2493,7 +2493,7 @@ void _8080bw_state::indianbtbr(machine_config &config)
|
||||
/* */
|
||||
/*******************************************************/
|
||||
|
||||
WRITE8_MEMBER(_8080bw_state::steelwkr_sh_port_3_w)
|
||||
void _8080bw_state::steelwkr_sh_port_3_w(uint8_t data)
|
||||
{
|
||||
machine().bookkeeping().coin_lockout_global_w(!(~data & 0x03)); /* possibly */
|
||||
}
|
||||
@ -2724,14 +2724,14 @@ static INPUT_PORTS_START( skylove )
|
||||
INVADERS_CAB_TYPE_PORT
|
||||
INPUT_PORTS_END
|
||||
|
||||
READ8_MEMBER(_8080bw_state::shuttlei_ff_r)
|
||||
uint8_t _8080bw_state::shuttlei_ff_r()
|
||||
{
|
||||
uint8_t data = ioport("INPUTS")->read();
|
||||
if (!m_flip_screen) return data;
|
||||
return (data & 0x3b) | ioport("P2")->read();
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(_8080bw_state::shuttlei_ff_w)
|
||||
void _8080bw_state::shuttlei_ff_w(uint8_t data)
|
||||
{
|
||||
/* bit 0 goes high when first coin inserted
|
||||
bit 1 also goes high when subsequent coins are inserted
|
||||
@ -2828,7 +2828,7 @@ IRQ_CALLBACK_MEMBER(_8080bw_state::darthvdr_interrupt_vector)
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
READ8_MEMBER(_8080bw_state::darthvdr_01_r)
|
||||
uint8_t _8080bw_state::darthvdr_01_r()
|
||||
{
|
||||
uint8_t data = ioport("P2")->read();
|
||||
if (m_flip_screen) return data;
|
||||
@ -3204,12 +3204,12 @@ INPUT_CHANGED_MEMBER(_8080bw_state::claybust_gun_trigger)
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER(_8080bw_state::claybust_gun_lo_r)
|
||||
uint8_t _8080bw_state::claybust_gun_lo_r()
|
||||
{
|
||||
return m_claybust_gun_pos & 0xff;
|
||||
}
|
||||
|
||||
READ8_MEMBER(_8080bw_state::claybust_gun_hi_r)
|
||||
uint8_t _8080bw_state::claybust_gun_hi_r()
|
||||
{
|
||||
return m_claybust_gun_pos >> 8;
|
||||
}
|
||||
@ -3503,12 +3503,12 @@ void _8080bw_state::invmulti_map(address_map &map)
|
||||
map(0xe000, 0xe000).mirror(0x1fff).w(FUNC(_8080bw_state::invmulti_bank_w));
|
||||
}
|
||||
|
||||
READ8_MEMBER(_8080bw_state::invmulti_eeprom_r)
|
||||
uint8_t _8080bw_state::invmulti_eeprom_r()
|
||||
{
|
||||
return m_eeprom->do_read();
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(_8080bw_state::invmulti_eeprom_w)
|
||||
void _8080bw_state::invmulti_eeprom_w(uint8_t data)
|
||||
{
|
||||
// d0: latch bit
|
||||
m_eeprom->di_write(data & 1);
|
||||
@ -3520,7 +3520,7 @@ WRITE8_MEMBER(_8080bw_state::invmulti_eeprom_w)
|
||||
m_eeprom->clk_write((data & 0x10) ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(_8080bw_state::invmulti_bank_w)
|
||||
void _8080bw_state::invmulti_bank_w(uint8_t data)
|
||||
{
|
||||
// d0, d4, d6: bank
|
||||
int bank = (data & 1) | (data >> 3 & 2) | (data >> 4 & 4);
|
||||
|
@ -26,7 +26,7 @@
|
||||
*
|
||||
*************************************/
|
||||
|
||||
READ8_MEMBER(_88games_state::bankedram_r)
|
||||
uint8_t _88games_state::bankedram_r(offs_t offset)
|
||||
{
|
||||
if (m_videobank)
|
||||
return m_ram[offset];
|
||||
@ -39,7 +39,7 @@ READ8_MEMBER(_88games_state::bankedram_r)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(_88games_state::bankedram_w)
|
||||
void _88games_state::bankedram_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
if (m_videobank)
|
||||
m_ram[offset] = data;
|
||||
@ -47,7 +47,7 @@ WRITE8_MEMBER(_88games_state::bankedram_w)
|
||||
m_k051316->write(offset, data);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(_88games_state::k88games_5f84_w)
|
||||
void _88games_state::k88games_5f84_w(uint8_t data)
|
||||
{
|
||||
/* bits 0/1 coin counters */
|
||||
machine().bookkeeping().coin_counter_w(0, data & 0x01);
|
||||
@ -61,13 +61,13 @@ WRITE8_MEMBER(_88games_state::k88games_5f84_w)
|
||||
popmessage("5f84 = %02x", data);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(_88games_state::k88games_sh_irqtrigger_w)
|
||||
void _88games_state::k88games_sh_irqtrigger_w(uint8_t data)
|
||||
{
|
||||
m_audiocpu->set_input_line_and_vector(0, HOLD_LINE, 0xff); // Z80
|
||||
}
|
||||
|
||||
|
||||
WRITE8_MEMBER(_88games_state::speech_control_w)
|
||||
void _88games_state::speech_control_w(uint8_t data)
|
||||
{
|
||||
m_speech_chip = BIT(data, 2);
|
||||
|
||||
@ -75,13 +75,13 @@ WRITE8_MEMBER(_88games_state::speech_control_w)
|
||||
m_upd7759[m_speech_chip]->start_w(BIT(data, 0));
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(_88games_state::speech_msg_w)
|
||||
void _88games_state::speech_msg_w(uint8_t data)
|
||||
{
|
||||
m_upd7759[m_speech_chip]->port_w(data);
|
||||
}
|
||||
|
||||
/* special handlers to combine 052109 & 051960 */
|
||||
READ8_MEMBER(_88games_state::k052109_051960_r)
|
||||
uint8_t _88games_state::k052109_051960_r(offs_t offset)
|
||||
{
|
||||
if (m_k052109->get_rmrd_line() == CLEAR_LINE)
|
||||
{
|
||||
@ -96,7 +96,7 @@ READ8_MEMBER(_88games_state::k052109_051960_r)
|
||||
return m_k052109->read(offset);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(_88games_state::k052109_051960_w)
|
||||
void _88games_state::k052109_051960_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
if (offset >= 0x3800 && offset < 0x3808)
|
||||
m_k051960->k051937_w(offset - 0x3800, data);
|
||||
|
@ -47,12 +47,12 @@ protected:
|
||||
void _1942_map(address_map &map);
|
||||
void sound_map(address_map &map);
|
||||
|
||||
DECLARE_WRITE8_MEMBER(_1942_bankswitch_w);
|
||||
DECLARE_WRITE8_MEMBER(_1942_fgvideoram_w);
|
||||
DECLARE_WRITE8_MEMBER(_1942_bgvideoram_w);
|
||||
DECLARE_WRITE8_MEMBER(_1942_palette_bank_w);
|
||||
DECLARE_WRITE8_MEMBER(_1942_scroll_w);
|
||||
DECLARE_WRITE8_MEMBER(_1942_c804_w);
|
||||
void _1942_bankswitch_w(uint8_t data);
|
||||
void _1942_fgvideoram_w(offs_t offset, uint8_t data);
|
||||
void _1942_bgvideoram_w(offs_t offset, uint8_t data);
|
||||
void _1942_palette_bank_w(uint8_t data);
|
||||
void _1942_scroll_w(offs_t offset, uint8_t data);
|
||||
void _1942_c804_w(uint8_t data);
|
||||
void _1942_palette(palette_device &palette) const;
|
||||
TIMER_DEVICE_CALLBACK_MEMBER(_1942_scanline);
|
||||
uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
|
||||
@ -97,8 +97,8 @@ protected:
|
||||
void _1942p_sound_io(address_map &map);
|
||||
void _1942p_sound_map(address_map &map);
|
||||
|
||||
DECLARE_WRITE8_MEMBER(_1942p_f600_w);
|
||||
DECLARE_WRITE8_MEMBER(_1942p_palette_w);
|
||||
void _1942p_f600_w(uint8_t data);
|
||||
void _1942p_palette_w(offs_t offset, uint8_t data);
|
||||
|
||||
void _1942p_palette(palette_device &palette) const;
|
||||
|
||||
|
@ -69,14 +69,14 @@ protected:
|
||||
uint8_t m_sprite_pal_base;
|
||||
|
||||
uint8_t m_irq_mask;
|
||||
DECLARE_WRITE8_MEMBER(irqack_w);
|
||||
DECLARE_WRITE8_MEMBER(timer_pulse_w);
|
||||
DECLARE_WRITE8_MEMBER(_20pacgal_coin_counter_w);
|
||||
DECLARE_WRITE8_MEMBER(ram_bank_select_w);
|
||||
DECLARE_WRITE8_MEMBER(ram_48000_w);
|
||||
DECLARE_WRITE8_MEMBER(sprite_gfx_w);
|
||||
DECLARE_WRITE8_MEMBER(sprite_ram_w);
|
||||
DECLARE_WRITE8_MEMBER(sprite_lookup_w);
|
||||
void irqack_w(uint8_t data);
|
||||
void timer_pulse_w(uint8_t data);
|
||||
void _20pacgal_coin_counter_w(uint8_t data);
|
||||
void ram_bank_select_w(uint8_t data);
|
||||
void ram_48000_w(offs_t offset, uint8_t data);
|
||||
void sprite_gfx_w(offs_t offset, uint8_t data);
|
||||
void sprite_ram_w(offs_t offset, uint8_t data);
|
||||
void sprite_lookup_w(offs_t offset, uint8_t data);
|
||||
|
||||
virtual void machine_start() override;
|
||||
virtual void machine_reset() override;
|
||||
@ -108,7 +108,7 @@ public:
|
||||
void _25pacman(machine_config &config);
|
||||
|
||||
private:
|
||||
DECLARE_READ8_MEMBER( _25pacman_io_87_r );
|
||||
uint8_t _25pacman_io_87_r();
|
||||
|
||||
virtual void machine_start() override;
|
||||
|
||||
|
@ -174,16 +174,16 @@ private:
|
||||
uint8_t m_nvmem[0x8000];
|
||||
|
||||
// uint8_t m_video_bits[512];
|
||||
DECLARE_READ8_MEMBER(nvarea_r);
|
||||
DECLARE_WRITE8_MEMBER(nvarea_w);
|
||||
DECLARE_READ32_MEMBER(slow2_r);
|
||||
DECLARE_WRITE32_MEMBER(slow2_w);
|
||||
DECLARE_READ32_MEMBER(svf_r);
|
||||
DECLARE_WRITE32_MEMBER(svf_w);
|
||||
DECLARE_READ32_MEMBER(madam_r);
|
||||
DECLARE_WRITE32_MEMBER(madam_w);
|
||||
DECLARE_READ32_MEMBER(clio_r);
|
||||
DECLARE_WRITE32_MEMBER(clio_w);
|
||||
uint8_t nvarea_r(offs_t offset);
|
||||
void nvarea_w(offs_t offset, uint8_t data);
|
||||
uint32_t slow2_r(offs_t offset);
|
||||
void slow2_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
uint32_t svf_r(offs_t offset);
|
||||
void svf_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
uint32_t madam_r(offs_t offset);
|
||||
void madam_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
uint32_t clio_r(offs_t offset);
|
||||
void clio_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
|
||||
|
||||
TIMER_DEVICE_CALLBACK_MEMBER( timer_x16_cb );
|
||||
|
@ -57,20 +57,20 @@ private:
|
||||
virtual void machine_reset() override;
|
||||
virtual void video_start() override;
|
||||
|
||||
DECLARE_WRITE8_MEMBER(bank_select_w);
|
||||
DECLARE_WRITE8_MEMBER(pix1_w);
|
||||
DECLARE_WRITE8_MEMBER(pix2_w);
|
||||
DECLARE_READ8_MEMBER(pix2_r);
|
||||
DECLARE_READ8_MEMBER(snd_flag_r);
|
||||
DECLARE_READ8_MEMBER(fortyl_mcu_status_r);
|
||||
DECLARE_WRITE8_MEMBER(fortyl_pixram_sel_w);
|
||||
DECLARE_READ8_MEMBER(fortyl_pixram_r);
|
||||
DECLARE_WRITE8_MEMBER(fortyl_pixram_w);
|
||||
DECLARE_WRITE8_MEMBER(fortyl_bg_videoram_w);
|
||||
DECLARE_READ8_MEMBER(fortyl_bg_videoram_r);
|
||||
DECLARE_WRITE8_MEMBER(fortyl_bg_colorram_w);
|
||||
DECLARE_READ8_MEMBER(fortyl_bg_colorram_r);
|
||||
DECLARE_WRITE8_MEMBER(pix1_mcu_w);
|
||||
void bank_select_w(uint8_t data);
|
||||
void pix1_w(uint8_t data);
|
||||
void pix2_w(uint8_t data);
|
||||
uint8_t pix2_r();
|
||||
uint8_t snd_flag_r();
|
||||
uint8_t fortyl_mcu_status_r();
|
||||
void fortyl_pixram_sel_w(uint8_t data);
|
||||
uint8_t fortyl_pixram_r(offs_t offset);
|
||||
void fortyl_pixram_w(offs_t offset, uint8_t data);
|
||||
void fortyl_bg_videoram_w(offs_t offset, uint8_t data);
|
||||
uint8_t fortyl_bg_videoram_r(offs_t offset);
|
||||
void fortyl_bg_colorram_w(offs_t offset, uint8_t data);
|
||||
uint8_t fortyl_bg_colorram_r(offs_t offset);
|
||||
void pix1_mcu_w(uint8_t data);
|
||||
void sound_control_0_w(uint8_t data);
|
||||
void sound_control_1_w(uint8_t data);
|
||||
void sound_control_2_w(uint8_t data);
|
||||
|
@ -31,13 +31,13 @@ public:
|
||||
|
||||
void _4enraya(machine_config &config);
|
||||
|
||||
DECLARE_WRITE8_MEMBER(fenraya_videoram_w);
|
||||
void fenraya_videoram_w(offs_t offset, uint8_t data);
|
||||
|
||||
protected:
|
||||
DECLARE_WRITE8_MEMBER(sound_data_w);
|
||||
DECLARE_READ8_MEMBER(fenraya_custom_map_r);
|
||||
DECLARE_WRITE8_MEMBER(fenraya_custom_map_w);
|
||||
DECLARE_WRITE8_MEMBER(sound_control_w);
|
||||
void sound_data_w(uint8_t data);
|
||||
uint8_t fenraya_custom_map_r(offs_t offset);
|
||||
void fenraya_custom_map_w(offs_t offset, uint8_t data);
|
||||
void sound_control_w(uint8_t data);
|
||||
TILE_GET_INFO_MEMBER(get_tile_info);
|
||||
uint32_t screen_update_4enraya(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
|
||||
|
||||
|
@ -136,60 +136,60 @@ private:
|
||||
bool m_timer_state;
|
||||
|
||||
TIMER_DEVICE_CALLBACK_MEMBER(nmi_timer);
|
||||
DECLARE_READ8_MEMBER(indianbt_r);
|
||||
DECLARE_READ8_MEMBER(polaris_port00_r);
|
||||
DECLARE_WRITE8_MEMBER(steelwkr_sh_port_3_w);
|
||||
DECLARE_WRITE8_MEMBER(invadpt2_sh_port_1_w);
|
||||
DECLARE_WRITE8_MEMBER(invadpt2_sh_port_2_w);
|
||||
DECLARE_WRITE8_MEMBER(spacerng_sh_port_2_w);
|
||||
DECLARE_WRITE8_MEMBER(spcewars_sh_port_w);
|
||||
DECLARE_WRITE8_MEMBER(lrescue_sh_port_1_w);
|
||||
DECLARE_WRITE8_MEMBER(lrescue_sh_port_2_w);
|
||||
DECLARE_WRITE8_MEMBER(cosmo_sh_port_2_w);
|
||||
DECLARE_READ8_MEMBER(darthvdr_01_r);
|
||||
DECLARE_WRITE8_MEMBER(darthvdr_00_w);
|
||||
DECLARE_WRITE8_MEMBER(darthvdr_08_w);
|
||||
uint8_t indianbt_r();
|
||||
uint8_t polaris_port00_r();
|
||||
void steelwkr_sh_port_3_w(uint8_t data);
|
||||
void invadpt2_sh_port_1_w(uint8_t data);
|
||||
void invadpt2_sh_port_2_w(uint8_t data);
|
||||
void spacerng_sh_port_2_w(uint8_t data);
|
||||
void spcewars_sh_port_w(uint8_t data);
|
||||
void lrescue_sh_port_1_w(uint8_t data);
|
||||
void lrescue_sh_port_2_w(uint8_t data);
|
||||
void cosmo_sh_port_2_w(uint8_t data);
|
||||
uint8_t darthvdr_01_r();
|
||||
void darthvdr_00_w(uint8_t data);
|
||||
void darthvdr_08_w(uint8_t data);
|
||||
IRQ_CALLBACK_MEMBER(darthvdr_interrupt_vector);
|
||||
DECLARE_WRITE8_MEMBER(ballbomb_01_w);
|
||||
DECLARE_WRITE8_MEMBER(ballbomb_sh_port_1_w);
|
||||
DECLARE_WRITE8_MEMBER(ballbomb_sh_port_2_w);
|
||||
DECLARE_WRITE8_MEMBER(indianbt_sh_port_1_w);
|
||||
DECLARE_WRITE8_MEMBER(indianbt_sh_port_2_w);
|
||||
DECLARE_WRITE8_MEMBER(indianbtbr_sh_port_1_w);
|
||||
DECLARE_WRITE8_MEMBER(indianbtbr_sh_port_2_w);
|
||||
DECLARE_READ8_MEMBER(indianbtbr_01_r);
|
||||
DECLARE_WRITE8_MEMBER(schaser_sh_port_1_w);
|
||||
DECLARE_WRITE8_MEMBER(schaser_sh_port_2_w);
|
||||
DECLARE_WRITE8_MEMBER(rollingc_sh_port_w);
|
||||
DECLARE_READ8_MEMBER(invrvnge_02_r);
|
||||
DECLARE_WRITE8_MEMBER(invrvnge_port03_w);
|
||||
DECLARE_WRITE8_MEMBER(invrvnge_port05_w);
|
||||
DECLARE_WRITE8_MEMBER(lupin3_00_w);
|
||||
DECLARE_WRITE8_MEMBER(lupin3_sh_port_1_w);
|
||||
DECLARE_WRITE8_MEMBER(lupin3_sh_port_2_w);
|
||||
DECLARE_READ8_MEMBER(schasercv_02_r);
|
||||
DECLARE_WRITE8_MEMBER(schasercv_sh_port_1_w);
|
||||
DECLARE_WRITE8_MEMBER(schasercv_sh_port_2_w);
|
||||
DECLARE_WRITE8_MEMBER(crashrd_port03_w);
|
||||
DECLARE_WRITE8_MEMBER(crashrd_port05_w);
|
||||
DECLARE_WRITE8_MEMBER(yosakdon_sh_port_1_w);
|
||||
DECLARE_WRITE8_MEMBER(yosakdon_sh_port_2_w);
|
||||
DECLARE_READ8_MEMBER(shuttlei_ff_r);
|
||||
DECLARE_WRITE8_MEMBER(shuttlei_ff_w);
|
||||
DECLARE_WRITE8_MEMBER(shuttlei_sh_port_1_w);
|
||||
DECLARE_WRITE8_MEMBER(shuttlei_sh_port_2_w);
|
||||
DECLARE_READ8_MEMBER(claybust_gun_lo_r);
|
||||
DECLARE_READ8_MEMBER(claybust_gun_hi_r);
|
||||
DECLARE_READ8_MEMBER(invmulti_eeprom_r);
|
||||
DECLARE_WRITE8_MEMBER(invmulti_eeprom_w);
|
||||
DECLARE_WRITE8_MEMBER(invmulti_bank_w);
|
||||
void ballbomb_01_w(uint8_t data);
|
||||
void ballbomb_sh_port_1_w(uint8_t data);
|
||||
void ballbomb_sh_port_2_w(uint8_t data);
|
||||
void indianbt_sh_port_1_w(uint8_t data);
|
||||
void indianbt_sh_port_2_w(uint8_t data);
|
||||
void indianbtbr_sh_port_1_w(uint8_t data);
|
||||
void indianbtbr_sh_port_2_w(uint8_t data);
|
||||
uint8_t indianbtbr_01_r();
|
||||
void schaser_sh_port_1_w(uint8_t data);
|
||||
void schaser_sh_port_2_w(uint8_t data);
|
||||
void rollingc_sh_port_w(uint8_t data);
|
||||
uint8_t invrvnge_02_r();
|
||||
void invrvnge_port03_w(uint8_t data);
|
||||
void invrvnge_port05_w(uint8_t data);
|
||||
void lupin3_00_w(uint8_t data);
|
||||
void lupin3_sh_port_1_w(uint8_t data);
|
||||
void lupin3_sh_port_2_w(uint8_t data);
|
||||
uint8_t schasercv_02_r();
|
||||
void schasercv_sh_port_1_w(uint8_t data);
|
||||
void schasercv_sh_port_2_w(uint8_t data);
|
||||
void crashrd_port03_w(uint8_t data);
|
||||
void crashrd_port05_w(uint8_t data);
|
||||
void yosakdon_sh_port_1_w(uint8_t data);
|
||||
void yosakdon_sh_port_2_w(uint8_t data);
|
||||
uint8_t shuttlei_ff_r();
|
||||
void shuttlei_ff_w(uint8_t data);
|
||||
void shuttlei_sh_port_1_w(uint8_t data);
|
||||
void shuttlei_sh_port_2_w(uint8_t data);
|
||||
uint8_t claybust_gun_lo_r();
|
||||
uint8_t claybust_gun_hi_r();
|
||||
uint8_t invmulti_eeprom_r();
|
||||
void invmulti_eeprom_w(uint8_t data);
|
||||
void invmulti_bank_w(uint8_t data);
|
||||
|
||||
DECLARE_READ8_MEMBER(rollingc_scattered_colorram_r);
|
||||
DECLARE_WRITE8_MEMBER(rollingc_scattered_colorram_w);
|
||||
DECLARE_READ8_MEMBER(rollingc_scattered_colorram2_r);
|
||||
DECLARE_WRITE8_MEMBER(rollingc_scattered_colorram2_w);
|
||||
DECLARE_READ8_MEMBER(schaser_scattered_colorram_r);
|
||||
DECLARE_WRITE8_MEMBER(schaser_scattered_colorram_w);
|
||||
uint8_t rollingc_scattered_colorram_r(offs_t offset);
|
||||
void rollingc_scattered_colorram_w(offs_t offset, uint8_t data);
|
||||
uint8_t rollingc_scattered_colorram2_r(offs_t offset);
|
||||
void rollingc_scattered_colorram2_w(offs_t offset, uint8_t data);
|
||||
uint8_t schaser_scattered_colorram_r(offs_t offset);
|
||||
void schaser_scattered_colorram_w(offs_t offset, uint8_t data);
|
||||
|
||||
DECLARE_MACHINE_START(extra_8080bw);
|
||||
DECLARE_MACHINE_START(rollingc);
|
||||
@ -225,10 +225,10 @@ private:
|
||||
DECLARE_WRITE_LINE_MEMBER(polaris_60hz_w);
|
||||
TIMER_DEVICE_CALLBACK_MEMBER(claybust_gun_callback);
|
||||
TIMER_DEVICE_CALLBACK_MEMBER(schaser_effect_555_cb);
|
||||
DECLARE_WRITE8_MEMBER(indianbt_sh_port_3_w);
|
||||
DECLARE_WRITE8_MEMBER(polaris_sh_port_1_w);
|
||||
DECLARE_WRITE8_MEMBER(polaris_sh_port_2_w);
|
||||
DECLARE_WRITE8_MEMBER(polaris_sh_port_3_w);
|
||||
void indianbt_sh_port_3_w(uint8_t data);
|
||||
void polaris_sh_port_1_w(uint8_t data);
|
||||
void polaris_sh_port_2_w(uint8_t data);
|
||||
void polaris_sh_port_3_w(uint8_t data);
|
||||
|
||||
void schaser_reinit_555_time_remain();
|
||||
inline void set_pixel( bitmap_rgb32 &bitmap, uint8_t y, uint8_t x, int color );
|
||||
@ -276,7 +276,7 @@ private:
|
||||
};
|
||||
|
||||
|
||||
/*----------- defined in audio/8080bw.c -----------*/
|
||||
/*----------- defined in audio/8080bw.cpp -----------*/
|
||||
extern const char *const lrescue_sample_names[];
|
||||
extern const char *const lupin3_sample_names[];
|
||||
|
||||
|
@ -57,14 +57,14 @@ private:
|
||||
/* memory pointers */
|
||||
required_shared_ptr<uint8_t> m_ram;
|
||||
|
||||
DECLARE_READ8_MEMBER(bankedram_r);
|
||||
DECLARE_WRITE8_MEMBER(bankedram_w);
|
||||
DECLARE_WRITE8_MEMBER(k88games_5f84_w);
|
||||
DECLARE_WRITE8_MEMBER(k88games_sh_irqtrigger_w);
|
||||
DECLARE_WRITE8_MEMBER(speech_control_w);
|
||||
DECLARE_WRITE8_MEMBER(speech_msg_w);
|
||||
DECLARE_READ8_MEMBER(k052109_051960_r);
|
||||
DECLARE_WRITE8_MEMBER(k052109_051960_w);
|
||||
uint8_t bankedram_r(offs_t offset);
|
||||
void bankedram_w(offs_t offset, uint8_t data);
|
||||
void k88games_5f84_w(uint8_t data);
|
||||
void k88games_sh_irqtrigger_w(uint8_t data);
|
||||
void speech_control_w(uint8_t data);
|
||||
void speech_msg_w(uint8_t data);
|
||||
uint8_t k052109_051960_r(offs_t offset);
|
||||
void k052109_051960_w(offs_t offset, uint8_t data);
|
||||
virtual void machine_start() override;
|
||||
virtual void machine_reset() override;
|
||||
uint32_t screen_update_88games(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
|
||||
|
@ -106,19 +106,19 @@ void sega_315_5881_crypt_device::device_reset()
|
||||
*
|
||||
************************************************/
|
||||
|
||||
READ16_MEMBER(sega_315_5881_crypt_device::ready_r)
|
||||
uint16_t sega_315_5881_crypt_device::ready_r()
|
||||
{
|
||||
// bit 0: busy flag
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(sega_315_5881_crypt_device::addrlo_w)
|
||||
void sega_315_5881_crypt_device::addrlo_w(uint16_t data)
|
||||
{
|
||||
set_addr_low(data&0xffff);
|
||||
first_read = true;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(sega_315_5881_crypt_device::addrhi_w)
|
||||
void sega_315_5881_crypt_device::addrhi_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
set_addr_high(0);
|
||||
if (data != 0)
|
||||
@ -126,13 +126,13 @@ WRITE16_MEMBER(sega_315_5881_crypt_device::addrhi_w)
|
||||
first_read = true;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(sega_315_5881_crypt_device::subkey_le_w)
|
||||
void sega_315_5881_crypt_device::subkey_le_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
printf("subkey %08x (%08x)\n", data, mem_mask);
|
||||
set_subkey(data & 0xffff);
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(sega_315_5881_crypt_device::subkey_be_w)
|
||||
void sega_315_5881_crypt_device::subkey_be_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
uint16_t subkey;
|
||||
printf("subkey %08x (%08x)\n", data, mem_mask);
|
||||
@ -141,16 +141,16 @@ WRITE16_MEMBER(sega_315_5881_crypt_device::subkey_be_w)
|
||||
set_subkey(subkey);
|
||||
}
|
||||
|
||||
READ16_MEMBER(sega_315_5881_crypt_device::decrypt_le_r)
|
||||
uint16_t sega_315_5881_crypt_device::decrypt_le_r()
|
||||
{
|
||||
uint16_t retval = decrypt_be_r(space,offset,mem_mask);
|
||||
uint16_t retval = decrypt_be_r();
|
||||
// endian swap the sub-key for little endian CPUs
|
||||
retval = ((retval & 0xff00) >> 8) | ((retval & 0x00ff) << 8);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
READ16_MEMBER(sega_315_5881_crypt_device::decrypt_be_r)
|
||||
uint16_t sega_315_5881_crypt_device::decrypt_be_r()
|
||||
{
|
||||
if (first_read == true)
|
||||
{
|
||||
|
@ -17,13 +17,13 @@ public:
|
||||
// construction/destruction
|
||||
sega_315_5881_crypt_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
DECLARE_READ16_MEMBER(ready_r);
|
||||
DECLARE_WRITE16_MEMBER(subkey_le_w);
|
||||
DECLARE_WRITE16_MEMBER(subkey_be_w);
|
||||
DECLARE_WRITE16_MEMBER(addrlo_w);
|
||||
DECLARE_WRITE16_MEMBER(addrhi_w);
|
||||
DECLARE_READ16_MEMBER(decrypt_le_r);
|
||||
DECLARE_READ16_MEMBER(decrypt_be_r);
|
||||
uint16_t ready_r();
|
||||
void subkey_le_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
void subkey_be_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
void addrlo_w(uint16_t data);
|
||||
void addrhi_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
uint16_t decrypt_le_r();
|
||||
uint16_t decrypt_be_r();
|
||||
|
||||
void iomap_64be(address_map &map);
|
||||
void iomap_le(address_map &map);
|
||||
|
@ -69,7 +69,7 @@ void sega_315_6154_device::regenerate_config_mapping()
|
||||
}
|
||||
}
|
||||
|
||||
READ32_MEMBER(sega_315_6154_device::registers_r)
|
||||
u32 sega_315_6154_device::registers_r(offs_t offset)
|
||||
{
|
||||
return m_registers[offset];
|
||||
}
|
||||
@ -85,7 +85,7 @@ static inline void parse_address_register(u32 reg, u32 *base)
|
||||
base[3] = reg << 24;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(sega_315_6154_device::registers_w)
|
||||
void sega_315_6154_device::registers_w(offs_t offset, u32 data, u32 mem_mask)
|
||||
{
|
||||
COMBINE_DATA(m_registers + offset);
|
||||
|
||||
|
@ -16,8 +16,8 @@ public:
|
||||
sega_315_6154_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
address_space *memory() { return memory_space; }
|
||||
|
||||
DECLARE_READ32_MEMBER(registers_r);
|
||||
DECLARE_WRITE32_MEMBER(registers_w);
|
||||
u32 registers_r(offs_t offset);
|
||||
void registers_w(offs_t offset, u32 data, u32 mem_mask = 0xffffffff);
|
||||
template<int Aperture>
|
||||
u32 aperture_r(address_space &space, offs_t offset, u32 mem_mask = 0xffffffff);
|
||||
template<int Aperture>
|
||||
|
@ -170,8 +170,8 @@ TIMER_DEVICE_CALLBACK_MEMBER( _3do_state::timer_x16_cb )
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER(_3do_state::nvarea_r) { return m_nvmem[offset]; }
|
||||
WRITE8_MEMBER(_3do_state::nvarea_w) { m_nvmem[offset] = data; }
|
||||
uint8_t _3do_state::nvarea_r(offs_t offset) { return m_nvmem[offset]; }
|
||||
void _3do_state::nvarea_w(offs_t offset, uint8_t data) { m_nvmem[offset] = data; }
|
||||
|
||||
|
||||
|
||||
@ -200,7 +200,7 @@ WRITE8_MEMBER(_3do_state::nvarea_w) { m_nvmem[offset] = data; }
|
||||
3022630
|
||||
*/
|
||||
|
||||
READ32_MEMBER(_3do_state::slow2_r){
|
||||
uint32_t _3do_state::slow2_r(offs_t offset){
|
||||
uint32_t data = 0;
|
||||
|
||||
logerror( "%08X: UNK_318 read offset = %08X\n", m_maincpu->pc(), offset );
|
||||
@ -215,7 +215,7 @@ READ32_MEMBER(_3do_state::slow2_r){
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(_3do_state::slow2_w)
|
||||
void _3do_state::slow2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
logerror( "%08X: UNK_318 write offset = %08X, data = %08X, mask = %08X\n", m_maincpu->pc(), offset, data, mem_mask );
|
||||
|
||||
@ -237,7 +237,7 @@ WRITE32_MEMBER(_3do_state::slow2_w)
|
||||
|
||||
|
||||
|
||||
READ32_MEMBER(_3do_state::svf_r)
|
||||
uint32_t _3do_state::svf_r(offs_t offset)
|
||||
{
|
||||
uint32_t addr = ( offset & ( 0x07fc / 4 ) ) << 9;
|
||||
uint32_t *p = m_vram + addr;
|
||||
@ -262,7 +262,7 @@ READ32_MEMBER(_3do_state::svf_r)
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(_3do_state::svf_w)
|
||||
void _3do_state::svf_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
uint32_t addr = ( offset & ( 0x07fc / 4 ) ) << 9;
|
||||
uint32_t *p = m_vram + addr;
|
||||
@ -302,7 +302,7 @@ WRITE32_MEMBER(_3do_state::svf_w)
|
||||
|
||||
|
||||
|
||||
READ32_MEMBER(_3do_state::madam_r){
|
||||
uint32_t _3do_state::madam_r(offs_t offset){
|
||||
logerror( "%08X: MADAM read offset = %08X\n", m_maincpu->pc(), offset*4 );
|
||||
|
||||
switch( offset ) {
|
||||
@ -461,7 +461,7 @@ READ32_MEMBER(_3do_state::madam_r){
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(_3do_state::madam_w){
|
||||
void _3do_state::madam_w(offs_t offset, uint32_t data, uint32_t mem_mask){
|
||||
if(offset == 0)
|
||||
{
|
||||
if(data == 0x0a)
|
||||
@ -655,7 +655,7 @@ WRITE32_MEMBER(_3do_state::madam_w){
|
||||
|
||||
|
||||
|
||||
READ32_MEMBER(_3do_state::clio_r)
|
||||
uint32_t _3do_state::clio_r(offs_t offset)
|
||||
{
|
||||
if (!machine().side_effects_disabled())
|
||||
{
|
||||
@ -782,7 +782,7 @@ READ32_MEMBER(_3do_state::clio_r)
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(_3do_state::clio_w)
|
||||
void _3do_state::clio_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
if(offset != 0x200/4 && offset != 0x40/4 && offset != 0x44/4 && offset != 0x48/4 && offset != 0x4c/4 &&
|
||||
offset != 0x118/4 && offset != 0x11c/4)
|
||||
|
@ -338,7 +338,7 @@ void m2_bda_device::device_timer(emu_timer &timer, device_timer_id id, int param
|
||||
// cpu_id_r - read from CPU ID register
|
||||
//-------------------------------------------------
|
||||
|
||||
READ32_MEMBER( m2_bda_device::cpu_id_r )
|
||||
uint32_t m2_bda_device::cpu_id_r(address_space &space)
|
||||
{
|
||||
uint32_t data = 0;
|
||||
|
||||
@ -359,7 +359,7 @@ READ32_MEMBER( m2_bda_device::cpu_id_r )
|
||||
// cpu_id_w - Write to CPU ID register
|
||||
//-------------------------------------------------
|
||||
|
||||
WRITE32_MEMBER( m2_bda_device::cpu_id_w )
|
||||
void m2_bda_device::cpu_id_w(address_space &space, uint32_t data)
|
||||
{
|
||||
// TODO: How should this work?
|
||||
logerror("%s: CPUID: %x\n", machine().describe_context(), data);
|
||||
@ -469,17 +469,17 @@ void m2_bda_device::configure_ppc_address_map(address_space &space)
|
||||
space.install_ram(TE_TRAM_BASE, TE_TRAM_BASE + TE_TRAM_MASK, m_te->tram_ptr());
|
||||
|
||||
// Install BDA sub-devices
|
||||
space.install_readwrite_handler(POWERBUS_BASE, POWERBUS_BASE + DEVICE_MASK,read32_delegate(*m_powerbus, FUNC(m2_powerbus_device::read)), write32_delegate(*m_powerbus, FUNC(m2_powerbus_device::write)), 0xffffffffffffffffULL);
|
||||
space.install_readwrite_handler(MEMCTL_BASE, MEMCTL_BASE + DEVICE_MASK, read32_delegate(*m_memctl, FUNC(m2_memctl_device::read)), write32_delegate(*m_memctl, FUNC(m2_memctl_device::write)), 0xffffffffffffffffULL);
|
||||
space.install_readwrite_handler(VDU_BASE, VDU_BASE + DEVICE_MASK, read32_delegate(*m_vdu, FUNC(m2_vdu_device::read)), write32_delegate(*m_vdu, FUNC(m2_vdu_device::write)), 0xffffffffffffffffULL);
|
||||
space.install_readwrite_handler(POWERBUS_BASE, POWERBUS_BASE + DEVICE_MASK,read32sm_delegate(*m_powerbus, FUNC(m2_powerbus_device::read)), write32sm_delegate(*m_powerbus, FUNC(m2_powerbus_device::write)), 0xffffffffffffffffULL);
|
||||
space.install_readwrite_handler(MEMCTL_BASE, MEMCTL_BASE + DEVICE_MASK, read32s_delegate(*m_memctl, FUNC(m2_memctl_device::read)), write32s_delegate(*m_memctl, FUNC(m2_memctl_device::write)), 0xffffffffffffffffULL);
|
||||
space.install_readwrite_handler(VDU_BASE, VDU_BASE + DEVICE_MASK, read32s_delegate(*m_vdu, FUNC(m2_vdu_device::read)), write32s_delegate(*m_vdu, FUNC(m2_vdu_device::write)), 0xffffffffffffffffULL);
|
||||
space.install_readwrite_handler(TE_BASE, TE_BASE + DEVICE_MASK, read32sm_delegate(*m_te, FUNC(m2_te_device::read)), write32sm_delegate(*m_te, FUNC(m2_te_device::write)), 0xffffffffffffffffULL);
|
||||
space.install_readwrite_handler(DSP_BASE, DSP_BASE + DEVICE_MASK, read32_delegate(*m_dspp, FUNC(dspp_device::read)), write32_delegate(*m_dspp, FUNC(dspp_device::write)), 0xffffffffffffffffULL);
|
||||
space.install_readwrite_handler(CTRLPORT_BASE, CTRLPORT_BASE + DEVICE_MASK,read32_delegate(*m_ctrlport, FUNC(m2_ctrlport_device::read)), write32_delegate(*m_ctrlport, FUNC(m2_ctrlport_device::write)), 0xffffffffffffffffULL);
|
||||
space.install_readwrite_handler(MPEG_BASE, MPEG_BASE + DEVICE_MASK, read32_delegate(*m_mpeg, FUNC(m2_mpeg_device::read)), write32_delegate(*m_mpeg, FUNC(m2_mpeg_device::write)), 0xffffffffffffffffULL);
|
||||
space.install_readwrite_handler(DSP_BASE, DSP_BASE + DEVICE_MASK, read32_delegate(*m_dspp, FUNC(dspp_device::read)), write32_delegate(*m_dspp, FUNC(dspp_device::write)), 0xffffffffffffffffULL);
|
||||
space.install_readwrite_handler(CTRLPORT_BASE, CTRLPORT_BASE + DEVICE_MASK,read32sm_delegate(*m_ctrlport, FUNC(m2_ctrlport_device::read)), write32sm_delegate(*m_ctrlport, FUNC(m2_ctrlport_device::write)), 0xffffffffffffffffULL);
|
||||
space.install_readwrite_handler(MPEG_BASE, MPEG_BASE + DEVICE_MASK, read32sm_delegate(*m_mpeg, FUNC(m2_mpeg_device::read)), write32sm_delegate(*m_mpeg, FUNC(m2_mpeg_device::write)), 0xffffffffffffffffULL);
|
||||
|
||||
space.install_readwrite_handler(CPUID_BASE, CPUID_BASE + DEVICE_MASK, read32_delegate(*this, FUNC(m2_bda_device::cpu_id_r)), write32_delegate(*this, FUNC(m2_bda_device::cpu_id_w)), 0xffffffffffffffffULL);
|
||||
space.install_readwrite_handler(CPUID_BASE, CPUID_BASE + DEVICE_MASK, read32mo_delegate(*this, FUNC(m2_bda_device::cpu_id_r)), write32mo_delegate(*this, FUNC(m2_bda_device::cpu_id_w)), 0xffffffffffffffffULL);
|
||||
|
||||
space.install_readwrite_handler(SLOT4_BASE, SLOT4_BASE + SLOT_MASK, read32_delegate(*m_cde, FUNC(m2_cde_device::read)), write32_delegate(*m_cde, FUNC(m2_cde_device::write)), 0xffffffffffffffffULL);
|
||||
space.install_readwrite_handler(SLOT4_BASE, SLOT4_BASE + SLOT_MASK, read32_delegate(*m_cde, FUNC(m2_cde_device::read)), write32_delegate(*m_cde, FUNC(m2_cde_device::write)), 0xffffffffffffffffULL);
|
||||
}
|
||||
|
||||
|
||||
@ -541,7 +541,7 @@ void m2_powerbus_device::device_reset()
|
||||
// read -
|
||||
//-------------------------------------------------
|
||||
|
||||
READ32_MEMBER( m2_powerbus_device::read )
|
||||
uint32_t m2_powerbus_device::read(offs_t offset)
|
||||
{
|
||||
const uint32_t byte_offs = offset << 2;
|
||||
uint32_t data = 0;
|
||||
@ -570,7 +570,7 @@ READ32_MEMBER( m2_powerbus_device::read )
|
||||
// write -
|
||||
//-------------------------------------------------
|
||||
|
||||
WRITE32_MEMBER( m2_powerbus_device::write )
|
||||
void m2_powerbus_device::write(offs_t offset, uint32_t data)
|
||||
{
|
||||
uint32_t byte_offs = offset << 2;
|
||||
|
||||
@ -682,7 +682,7 @@ void m2_memctl_device::device_reset()
|
||||
// read -
|
||||
//-------------------------------------------------
|
||||
|
||||
READ32_MEMBER( m2_memctl_device::read )
|
||||
uint32_t m2_memctl_device::read(offs_t offset, uint32_t mem_mask)
|
||||
{
|
||||
uint32_t byte_offs = offset << 2;
|
||||
uint32_t data = 0;
|
||||
@ -745,7 +745,7 @@ READ32_MEMBER( m2_memctl_device::read )
|
||||
// write -
|
||||
//-------------------------------------------------
|
||||
|
||||
WRITE32_MEMBER( m2_memctl_device::write )
|
||||
void m2_memctl_device::write(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
uint32_t byte_offs = offset << 2;
|
||||
|
||||
@ -895,7 +895,7 @@ void m2_vdu_device::device_timer(emu_timer &timer, device_timer_id id, int param
|
||||
// read -
|
||||
//-------------------------------------------------
|
||||
|
||||
READ32_MEMBER( m2_vdu_device::read )
|
||||
uint32_t m2_vdu_device::read(offs_t offset, uint32_t mem_mask)
|
||||
{
|
||||
uint32_t byte_offs = offset << 2;
|
||||
uint32_t data = 0;
|
||||
@ -939,7 +939,7 @@ READ32_MEMBER( m2_vdu_device::read )
|
||||
// write -
|
||||
//-------------------------------------------------
|
||||
|
||||
WRITE32_MEMBER( m2_vdu_device::write )
|
||||
void m2_vdu_device::write(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
uint32_t byte_offs = offset << 2;
|
||||
m2_reg_wmode wmode = byte_offs & 0x400 ? REG_CLEAR : REG_WRITE;
|
||||
@ -1441,7 +1441,7 @@ void m2_ctrlport_device::device_reset()
|
||||
// read -
|
||||
//-------------------------------------------------
|
||||
|
||||
READ32_MEMBER( m2_ctrlport_device::read )
|
||||
uint32_t m2_ctrlport_device::read(offs_t offset)
|
||||
{
|
||||
//const uint32_t byte_offs = offset << 2;
|
||||
uint32_t data = machine().rand();
|
||||
@ -1460,7 +1460,7 @@ READ32_MEMBER( m2_ctrlport_device::read )
|
||||
// write -
|
||||
//-------------------------------------------------
|
||||
|
||||
WRITE32_MEMBER( m2_ctrlport_device::write )
|
||||
void m2_ctrlport_device::write(offs_t offset, uint32_t data)
|
||||
{
|
||||
//uint32_t byte_offs = offset << 2;
|
||||
|
||||
@ -1627,7 +1627,7 @@ void m2_cde_device::update_interrupts()
|
||||
// read -
|
||||
//-------------------------------------------------
|
||||
|
||||
READ32_MEMBER( m2_cde_device::read )
|
||||
uint32_t m2_cde_device::read(address_space &space, offs_t offset, uint32_t mem_mask)
|
||||
{
|
||||
const uint32_t byte_offs = offset << 2;
|
||||
uint32_t data = 0;
|
||||
@ -1730,7 +1730,7 @@ READ32_MEMBER( m2_cde_device::read )
|
||||
// write -
|
||||
//-------------------------------------------------
|
||||
|
||||
WRITE32_MEMBER( m2_cde_device::write )
|
||||
void m2_cde_device::write(address_space &space, offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
uint32_t byte_offs = offset << 2;
|
||||
uint32_t dmach = byte_offs & 0x20 ? 1 : 0;
|
||||
@ -1889,7 +1889,7 @@ WRITE32_MEMBER( m2_cde_device::write )
|
||||
// sdbg_in -
|
||||
//-------------------------------------------------
|
||||
|
||||
WRITE32_MEMBER( m2_cde_device::sdbg_in )
|
||||
void m2_cde_device::sdbg_in(uint32_t data)
|
||||
{
|
||||
m_sdbg_in = data;
|
||||
set_interrupt(CDE_SDBG_RD_DONE);
|
||||
@ -2062,7 +2062,7 @@ void m2_mpeg_device::device_reset()
|
||||
// read
|
||||
//-------------------------------------------------
|
||||
|
||||
READ32_MEMBER( m2_mpeg_device::read )
|
||||
uint32_t m2_mpeg_device::read(offs_t offset)
|
||||
{
|
||||
logerror("%s: MPEG READ: %08X\n", machine().describe_context(), offset);
|
||||
return 0;
|
||||
@ -2072,7 +2072,7 @@ READ32_MEMBER( m2_mpeg_device::read )
|
||||
// write
|
||||
//-------------------------------------------------
|
||||
|
||||
WRITE32_MEMBER( m2_mpeg_device::write )
|
||||
void m2_mpeg_device::write(offs_t offset, uint32_t data)
|
||||
{
|
||||
logerror("%s: MPEG WRITE: %08X %08X\n", machine().describe_context(), offset, data);
|
||||
}
|
||||
|
@ -139,8 +139,8 @@ public:
|
||||
}
|
||||
|
||||
// Interface
|
||||
DECLARE_READ32_MEMBER( cpu_id_r );
|
||||
DECLARE_WRITE32_MEMBER( cpu_id_w );
|
||||
uint32_t cpu_id_r(address_space &space);
|
||||
void cpu_id_w(address_space &space, uint32_t data);
|
||||
|
||||
uint8_t read_bus8(offs_t offset);
|
||||
uint16_t read_bus16(offs_t offset);
|
||||
@ -253,8 +253,8 @@ public:
|
||||
update_interrupts();
|
||||
}
|
||||
|
||||
DECLARE_WRITE32_MEMBER( write );
|
||||
DECLARE_READ32_MEMBER( read );
|
||||
void write(offs_t offset, uint32_t data);
|
||||
uint32_t read(offs_t offset);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override;
|
||||
@ -297,8 +297,8 @@ public:
|
||||
template <std::size_t Line> auto gpio_in_handler() { return m_gpio_in[Line].bind(); }
|
||||
template <std::size_t Line> auto gpio_out_handler() { return m_gpio_out[Line].bind(); }
|
||||
|
||||
DECLARE_READ32_MEMBER(read);
|
||||
DECLARE_WRITE32_MEMBER(write);
|
||||
uint32_t read(offs_t offset, uint32_t mem_mask = ~0);
|
||||
void write(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override;
|
||||
@ -392,8 +392,8 @@ public:
|
||||
auto vint1_int_handler() { return m_vint1_int_handler.bind(); }
|
||||
template <typename T> void set_screen(T &&screen_tag) { m_screen.set_tag(std::forward<T>(screen_tag)); }
|
||||
|
||||
DECLARE_READ32_MEMBER(read);
|
||||
DECLARE_WRITE32_MEMBER(write);
|
||||
uint32_t read(offs_t offset, uint32_t mem_mask = ~0);
|
||||
void write(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
|
||||
uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
|
||||
|
||||
@ -455,8 +455,8 @@ class m2_ctrlport_device : public device_t
|
||||
public:
|
||||
m2_ctrlport_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
DECLARE_READ32_MEMBER(read);
|
||||
DECLARE_WRITE32_MEMBER(write);
|
||||
uint32_t read(offs_t offset);
|
||||
void write(offs_t offset, uint32_t data);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override;
|
||||
@ -477,8 +477,8 @@ class m2_mpeg_device : public device_t
|
||||
public:
|
||||
m2_mpeg_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
DECLARE_READ32_MEMBER(read);
|
||||
DECLARE_WRITE32_MEMBER(write);
|
||||
uint32_t read(offs_t offset);
|
||||
void write(offs_t offset, uint32_t data);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override;
|
||||
@ -511,10 +511,10 @@ public:
|
||||
void set_syscfg(uint32_t syscfg) { m_syscfg = syscfg; }
|
||||
auto sdbg_out() { return m_sdbg_out_handler.bind(); }
|
||||
|
||||
DECLARE_READ32_MEMBER(read);
|
||||
DECLARE_WRITE32_MEMBER(write);
|
||||
uint32_t read(address_space &space, offs_t offset, uint32_t mem_mask = ~0);
|
||||
void write(address_space &space, offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
|
||||
DECLARE_WRITE32_MEMBER(sdbg_in);
|
||||
void sdbg_in(uint32_t data);
|
||||
|
||||
void set_external_interrupt(uint32_t which, uint32_t state)
|
||||
{
|
||||
|
@ -916,7 +916,7 @@ void fd1094_device::default_state_change(uint8_t state)
|
||||
// (state change)
|
||||
//-------------------------------------------------
|
||||
|
||||
WRITE32_MEMBER(fd1094_device::cmp_callback)
|
||||
void fd1094_device::cmp_callback(offs_t offset, uint32_t data)
|
||||
{
|
||||
if (offset == 0 && (data & 0x0000ffff) == 0x0000ffff)
|
||||
change_state(data >> 16);
|
||||
|
@ -102,7 +102,7 @@ protected:
|
||||
IRQ_CALLBACK_MEMBER( irq_callback );
|
||||
|
||||
// static helpers
|
||||
DECLARE_WRITE32_MEMBER(cmp_callback);
|
||||
void cmp_callback(offs_t offset, uint32_t data);
|
||||
DECLARE_WRITE_LINE_MEMBER(rte_callback);
|
||||
|
||||
// internal state
|
||||
|
@ -152,20 +152,20 @@ void _1942p_state::video_start()
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
WRITE8_MEMBER(_1942_state::_1942_fgvideoram_w)
|
||||
void _1942_state::_1942_fgvideoram_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
m_fg_videoram[offset] = data;
|
||||
m_fg_tilemap->mark_tile_dirty(offset & 0x3ff);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(_1942_state::_1942_bgvideoram_w)
|
||||
void _1942_state::_1942_bgvideoram_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
m_bg_videoram[offset] = data;
|
||||
m_bg_tilemap->mark_tile_dirty((offset & 0x0f) | ((offset >> 1) & 0x01f0));
|
||||
}
|
||||
|
||||
|
||||
WRITE8_MEMBER(_1942_state::_1942_palette_bank_w)
|
||||
void _1942_state::_1942_palette_bank_w(uint8_t data)
|
||||
{
|
||||
if (m_palette_bank != data)
|
||||
{
|
||||
@ -174,14 +174,14 @@ WRITE8_MEMBER(_1942_state::_1942_palette_bank_w)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(_1942_state::_1942_scroll_w)
|
||||
void _1942_state::_1942_scroll_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
m_scroll[offset] = data;
|
||||
m_bg_tilemap->set_scrollx(0, m_scroll[0] | (m_scroll[1] << 8));
|
||||
}
|
||||
|
||||
|
||||
WRITE8_MEMBER(_1942_state::_1942_c804_w)
|
||||
void _1942_state::_1942_c804_w(uint8_t data)
|
||||
{
|
||||
/* bit 7: flip screen
|
||||
bit 4: cpu B reset
|
||||
|
@ -116,7 +116,7 @@ void fortyl_state::fortyl_set_scroll_x( int offset )
|
||||
---- -x-- Pix RAM color bank select
|
||||
---- ---x Flip Screen set
|
||||
*/
|
||||
WRITE8_MEMBER(fortyl_state::fortyl_pixram_sel_w)
|
||||
void fortyl_state::fortyl_pixram_sel_w(uint8_t data)
|
||||
{
|
||||
int offs;
|
||||
int f = data & 0x01;
|
||||
@ -145,7 +145,7 @@ WRITE8_MEMBER(fortyl_state::fortyl_pixram_sel_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER(fortyl_state::fortyl_pixram_r)
|
||||
uint8_t fortyl_state::fortyl_pixram_r(offs_t offset)
|
||||
{
|
||||
if (m_pixram_sel)
|
||||
return m_pixram2[offset];
|
||||
@ -181,7 +181,7 @@ void fortyl_state::fortyl_plot_pix( int offset )
|
||||
}
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(fortyl_state::fortyl_pixram_w)
|
||||
void fortyl_state::fortyl_pixram_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
if (m_pixram_sel)
|
||||
m_pixram2[offset] = data;
|
||||
@ -192,18 +192,18 @@ WRITE8_MEMBER(fortyl_state::fortyl_pixram_w)
|
||||
}
|
||||
|
||||
|
||||
WRITE8_MEMBER(fortyl_state::fortyl_bg_videoram_w)
|
||||
void fortyl_state::fortyl_bg_videoram_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
m_videoram[offset] = data;
|
||||
m_bg_tilemap->mark_tile_dirty(offset);
|
||||
}
|
||||
|
||||
READ8_MEMBER(fortyl_state::fortyl_bg_videoram_r)
|
||||
uint8_t fortyl_state::fortyl_bg_videoram_r(offs_t offset)
|
||||
{
|
||||
return m_videoram[offset];
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(fortyl_state::fortyl_bg_colorram_w)
|
||||
void fortyl_state::fortyl_bg_colorram_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
if (m_colorram[offset] != data)
|
||||
{
|
||||
@ -217,7 +217,7 @@ WRITE8_MEMBER(fortyl_state::fortyl_bg_colorram_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER(fortyl_state::fortyl_bg_colorram_r)
|
||||
uint8_t fortyl_state::fortyl_bg_colorram_r(offs_t offset)
|
||||
{
|
||||
return m_colorram[offset];
|
||||
}
|
||||
|
@ -11,7 +11,7 @@
|
||||
#include "emu.h"
|
||||
#include "includes/4enraya.h"
|
||||
|
||||
WRITE8_MEMBER(_4enraya_state::fenraya_videoram_w)
|
||||
void _4enraya_state::fenraya_videoram_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
m_videoram[(offset & 0x3ff) * 2] = data;
|
||||
m_videoram[(offset & 0x3ff) * 2 + 1] = (offset & 0xc00) >> 10;
|
||||
|
Loading…
Reference in New Issue
Block a user