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electron64: Implemented Master RAM Board, and promoted to working.

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This commit is contained in:
Nigel Barnes 2018-03-23 13:24:18 +00:00
parent 64ff86b5a9
commit 117ea91e45
3 changed files with 126 additions and 67 deletions
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27
src/mame/drivers/electron.cpp
View File

@ -98,6 +98,11 @@ void electron_state::electron_mem(address_map &map)
map(0xfe00, 0xfeff).rw(this, FUNC(electron_state::electron_sheila_r), FUNC(electron_state::electron_sheila_w)); /* SHEILA */
}
void electron_state::electron64_opcodes(address_map &map)
{
map(0x0000, 0xffff).r(this, FUNC(electron_state::electron64_fetch_r));
}
INPUT_CHANGED_MEMBER(electron_state::trigger_reset)
{
m_maincpu->set_input_line(INPUT_LINE_RESET, newval ? ASSERT_LINE : CLEAR_LINE);
@ -201,7 +206,7 @@ static INPUT_PORTS_START( electron64 )
PORT_INCLUDE(electron)
PORT_START("MRB")
PORT_CONFNAME(0x03, 0x01, "MRB Mode")
PORT_CONFNAME(0x03, 0x02, "MRB Mode")
PORT_CONFSETTING(0x00, "Normal")
PORT_CONFSETTING(0x01, "Turbo")
PORT_CONFSETTING(0x02, "64K")
@ -261,6 +266,18 @@ MACHINE_CONFIG_START(electron_state::btm2105)
MACHINE_CONFIG_END
MACHINE_CONFIG_START(electron_state::electron64)
electron(config);
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_PROGRAM_MAP(electron_mem)
MCFG_CPU_OPCODES_MAP(electron64_opcodes)
MCFG_RAM_MODIFY(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("64K")
MACHINE_CONFIG_END
/* Electron Rom Load */
ROM_START(electron)
ROM_REGION( 0x4000, "mos", 0 )
@ -279,7 +296,7 @@ ROM_END
#define rom_btm2105 rom_electron
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
COMP ( 1983, electron, 0, 0, electron, electron, electron_state, 0, "Acorn", "Acorn Electron", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS )
COMP ( 1985, btm2105, electron, 0, btm2105, electron, electron_state, 0, "British Telecom Business Systems", "BT Merlin M2105", MACHINE_NOT_WORKING )
COMP ( 1987, electron64, electron, 0, electron, electron64, electron_state, 0, "Acorn/Slogger", "Acorn Electron (64K Master RAM Board)", MACHINE_NOT_WORKING )
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
COMP ( 1983, electron, 0, 0, electron, electron, electron_state, 0, "Acorn", "Acorn Electron", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS )
COMP ( 1985, btm2105, electron, 0, btm2105, electron, electron_state, 0, "British Telecom Business Systems", "BT Merlin M2105", MACHINE_NOT_WORKING )
COMP ( 1987, electron64, electron, 0, electron64, electron64, electron_state, 0, "Acorn/Slogger", "Acorn Electron (64K Master RAM Board)", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS )

111
src/mame/includes/electron.h
View File

@ -52,8 +52,66 @@ public:
, m_mrb(*this, "MRB")
{ }
/* ULA context */
emu_timer *m_tape_timer;
int m_map4[256];
int m_map16[256];
emu_timer *m_scanline_timer;
DECLARE_READ8_MEMBER(electron64_fetch_r);
DECLARE_READ8_MEMBER(electron_mem_r);
DECLARE_WRITE8_MEMBER(electron_mem_w);
DECLARE_READ8_MEMBER(electron_paged_r);
DECLARE_WRITE8_MEMBER(electron_paged_w);
DECLARE_READ8_MEMBER(electron_mos_r);
DECLARE_WRITE8_MEMBER(electron_mos_w);
DECLARE_READ8_MEMBER(electron_fred_r);
DECLARE_WRITE8_MEMBER(electron_fred_w);
DECLARE_READ8_MEMBER(electron_jim_r);
DECLARE_WRITE8_MEMBER(electron_jim_w);
DECLARE_READ8_MEMBER(electron_sheila_r);
DECLARE_WRITE8_MEMBER(electron_sheila_w);
DECLARE_PALETTE_INIT(electron);
uint32_t screen_update_electron(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
TIMER_CALLBACK_MEMBER(electron_tape_timer_handler);
TIMER_CALLBACK_MEMBER(setup_beep);
TIMER_CALLBACK_MEMBER(electron_scanline_interrupt);
inline uint8_t read_vram( uint16_t addr );
inline void electron_plot_pixel(bitmap_ind16 &bitmap, int x, int y, uint32_t color);
void electron_interrupt_handler(int mode, int interrupt);
DECLARE_INPUT_CHANGED_MEMBER( trigger_reset );
void electron(machine_config &config);
void btm2105(machine_config &config);
void electron_mem(address_map &map);
void electron64(machine_config &config);
void electron64_opcodes(address_map &map);
protected:
virtual void machine_start() override;
virtual void machine_reset() override;
virtual void video_start() override;
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
private:
required_device<cpu_device> m_maincpu;
required_device<screen_device> m_screen;
required_device<cassette_image_device> m_cassette;
required_device<beep_device> m_beeper;
required_memory_region m_region_basic;
required_memory_region m_region_mos;
required_ioport_array<14> m_keybd;
required_device<electron_expansion_slot_device> m_exp;
required_device<ram_device> m_ram;
optional_ioport m_mrb;
void waitforramsync();
void electron_tape_start();
void electron_tape_stop();
/* ULA context */
struct ULA
{
uint8_t interrupt_status;
@ -82,55 +140,8 @@ public:
};
ULA m_ula;
emu_timer *m_tape_timer;
int m_map4[256];
int m_map16[256];
emu_timer *m_scanline_timer;
DECLARE_READ8_MEMBER(electron_mem_r);
DECLARE_WRITE8_MEMBER(electron_mem_w);
DECLARE_READ8_MEMBER(electron_paged_r);
DECLARE_WRITE8_MEMBER(electron_paged_w);
DECLARE_READ8_MEMBER(electron_mos_r);
DECLARE_WRITE8_MEMBER(electron_mos_w);
DECLARE_READ8_MEMBER(electron_fred_r);
DECLARE_WRITE8_MEMBER(electron_fred_w);
DECLARE_READ8_MEMBER(electron_jim_r);
DECLARE_WRITE8_MEMBER(electron_jim_w);
DECLARE_READ8_MEMBER(electron_sheila_r);
DECLARE_WRITE8_MEMBER(electron_sheila_w);
void waitforramsync();
void electron_tape_start();
void electron_tape_stop();
virtual void machine_start() override;
virtual void machine_reset() override;
virtual void video_start() override;
DECLARE_PALETTE_INIT(electron);
uint32_t screen_update_electron(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
TIMER_CALLBACK_MEMBER(electron_tape_timer_handler);
TIMER_CALLBACK_MEMBER(setup_beep);
TIMER_CALLBACK_MEMBER(electron_scanline_interrupt);
required_device<cpu_device> m_maincpu;
required_device<screen_device> m_screen;
required_device<cassette_image_device> m_cassette;
required_device<beep_device> m_beeper;
required_memory_region m_region_basic;
required_memory_region m_region_mos;
required_ioport_array<14> m_keybd;
required_device<electron_expansion_slot_device> m_exp;
required_device<ram_device> m_ram;
optional_ioport m_mrb;
inline uint8_t read_vram( uint16_t addr );
inline void electron_plot_pixel(bitmap_ind16 &bitmap, int x, int y, uint32_t color);
void electron_interrupt_handler(int mode, int interrupt);
DECLARE_INPUT_CHANGED_MEMBER( trigger_reset );
void electron(machine_config &config);
void btm2105(machine_config &config);
void electron_mem(address_map &map);
protected:
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
bool m_mrb_mapped;
bool m_vdu_drivers;
};
#endif // MAME_INCLUDES_ELECTRON_H

55
src/mame/machine/electron.cpp
View File

@ -142,21 +142,52 @@ TIMER_CALLBACK_MEMBER(electron_state::electron_tape_timer_handler)
}
}
READ8_MEMBER(electron_state::electron64_fetch_r)
{
m_vdu_drivers = (offset & 0xe000) == 0xc000 ? true : false;
return m_maincpu->space(AS_PROGRAM).read_byte(offset);
}
READ8_MEMBER(electron_state::electron_mem_r)
{
/* The processor will run at 1MHz during an access cycle to the RAM */
m_maincpu->set_clock_scale(0.5f);
switch (m_mrb.read_safe(0))
{
case 0x00: /* Normal */
/* The processor will run at 1MHz during an access cycle to the RAM */
m_maincpu->set_clock_scale(0.5f);
//waitforramsync();
break;
//waitforramsync();
case 0x01: /* Turbo */
if (m_mrb_mapped && offset < 0x3000) offset += 0x8000;
break;
case 0x02: /* Shadow */
if (m_mrb_mapped && (offset < 0x3000 || !m_vdu_drivers)) offset += 0x8000;
break;
}
return m_ram->read(offset);
}
WRITE8_MEMBER(electron_state::electron_mem_w)
{
/* The processor will run at 1MHz during an access cycle to the RAM */
m_maincpu->set_clock_scale(0.5f);
switch (m_mrb.read_safe(0))
{
case 0x00: /* Normal */
/* The processor will run at 1MHz during an access cycle to the RAM */
m_maincpu->set_clock_scale(0.5f);
//waitforramsync();
break;
//waitforramsync();
case 0x01: /* Turbo */
if (m_mrb_mapped && offset < 0x3000) offset += 0x8000;
break;
case 0x02: /* Shadow */
if (m_mrb_mapped && (offset < 0x3000 || !m_vdu_drivers)) offset += 0x8000;
break;
}
m_ram->write(offset, data);
}
@ -252,14 +283,11 @@ WRITE8_MEMBER(electron_state::electron_fred_w)
/* The processor will run at 2MHz during an access cycle to the ROM */
m_maincpu->set_clock_scale(1.0f);
/* Master RAM Board */
if (offset == 0x7f) m_mrb_mapped = !(data & 0x80);
//logerror("FRED: write fc%02x\n", offset);
m_exp->expbus_w(space, 0xfc00 + offset, data);
/* Master RAM Board */
if (offset == 0x7f && m_mrb.read_safe(0))
{
}
}
READ8_MEMBER(electron_state::electron_jim_r)
@ -469,6 +497,9 @@ void electron_state::machine_reset()
m_ula.screen_addr = 0;
m_ula.tape_running = 0;
m_ula.vram = (uint8_t *)m_ram->pointer() + m_ula.screen_base;
m_mrb_mapped = true;
m_vdu_drivers = false;
}
void electron_state::machine_start()